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8332615: RISC-V: Support vector unsigned comparison instructions for machines with RVV

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Reviewed-by: fyang
This commit is contained in:
Gui Cao 2024-05-24 07:12:22 +00:00 committed by Fei Yang
parent a71b404785
commit 9b61a7608e
2 changed files with 6 additions and 2 deletions

4
src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp

@ -2762,6 +2762,10 @@ void C2_MacroAssembler::compare_integral_v(VectorRegister vd, VectorRegister src
case BoolTest::ge: vmsge_vv(vd, src1, src2, vm); break;
case BoolTest::lt: vmslt_vv(vd, src1, src2, vm); break;
case BoolTest::gt: vmsgt_vv(vd, src1, src2, vm); break;
case BoolTest::ule: vmsleu_vv(vd, src1, src2, vm); break;
case BoolTest::uge: vmsgeu_vv(vd, src1, src2, vm); break;
case BoolTest::ult: vmsltu_vv(vd, src1, src2, vm); break;
case BoolTest::ugt: vmsgtu_vv(vd, src1, src2, vm); break;
default:
assert(false, "unsupported compare condition");
ShouldNotReachHere();

4
src/hotspot/cpu/riscv/matcher_riscv.hpp

@ -148,8 +148,8 @@
}
// Does the CPU supports vector unsigned comparison instructions?
static constexpr bool supports_vector_comparison_unsigned(int vlen, BasicType bt) {
return false;
static bool supports_vector_comparison_unsigned(int vlen, BasicType bt) {
return UseRVV;
}
// Some microarchitectures have mask registers used on vectors