8239090: Improve CPU feature support in VM_Version
Reviewed-by: iveresov, simonis
This commit is contained in:
Paul Hohensee
parent
8f7c9a7b18
commit
9e453d9792
@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2001, 2019, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2001, 2020, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -37,7 +37,9 @@
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#define VM_INT_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant) \
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LP64_ONLY(declare_constant(frame::arg_reg_save_area_bytes)) \
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declare_constant(frame::interpreter_frame_sender_sp_offset) \
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declare_constant(frame::interpreter_frame_last_sp_offset) \
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declare_constant(frame::interpreter_frame_last_sp_offset)
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#define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant) \
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declare_constant(VM_Version::CPU_CX8) \
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declare_constant(VM_Version::CPU_CMOV) \
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declare_constant(VM_Version::CPU_FXSR) \
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@ -68,22 +70,21 @@
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declare_constant(VM_Version::CPU_AVX512DQ) \
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declare_constant(VM_Version::CPU_AVX512PF) \
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declare_constant(VM_Version::CPU_AVX512ER) \
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declare_constant(VM_Version::CPU_AVX512CD)
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#define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant) \
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declare_preprocessor_constant("VM_Version::CPU_AVX512BW", CPU_AVX512BW) \
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declare_preprocessor_constant("VM_Version::CPU_AVX512VL", CPU_AVX512VL) \
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declare_preprocessor_constant("VM_Version::CPU_SHA", CPU_SHA) \
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declare_preprocessor_constant("VM_Version::CPU_FMA", CPU_FMA) \
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declare_preprocessor_constant("VM_Version::CPU_VZEROUPPER", CPU_VZEROUPPER) \
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declare_preprocessor_constant("VM_Version::CPU_AVX512_VPOPCNTDQ", CPU_AVX512_VPOPCNTDQ) \
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declare_preprocessor_constant("VM_Version::CPU_AVX512_VPCLMULQDQ", CPU_AVX512_VPCLMULQDQ) \
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declare_preprocessor_constant("VM_Version::CPU_AVX512_VAES", CPU_AVX512_VAES) \
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declare_preprocessor_constant("VM_Version::CPU_AVX512_VNNI", CPU_AVX512_VNNI) \
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declare_preprocessor_constant("VM_Version::CPU_FLUSH", CPU_FLUSH) \
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declare_preprocessor_constant("VM_Version::CPU_FLUSHOPT", CPU_FLUSHOPT) \
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declare_preprocessor_constant("VM_Version::CPU_CLWB", CPU_CLWB) \
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declare_preprocessor_constant("VM_Version::CPU_AVX512_VBMI2", CPU_AVX512_VBMI2) \
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declare_preprocessor_constant("VM_Version::CPU_AVX512_VBMI", CPU_AVX512_VBMI)
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declare_constant(VM_Version::CPU_AVX512CD) \
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declare_constant(VM_Version::CPU_AVX512BW) \
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declare_constant(VM_Version::CPU_AVX512VL) \
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declare_constant(VM_Version::CPU_SHA) \
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declare_constant(VM_Version::CPU_FMA) \
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declare_constant(VM_Version::CPU_VZEROUPPER) \
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declare_constant(VM_Version::CPU_AVX512_VPOPCNTDQ) \
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declare_constant(VM_Version::CPU_AVX512_VPCLMULQDQ) \
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declare_constant(VM_Version::CPU_AVX512_VAES) \
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declare_constant(VM_Version::CPU_AVX512_VNNI) \
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declare_constant(VM_Version::CPU_FLUSH) \
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declare_constant(VM_Version::CPU_FLUSHOPT) \
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declare_constant(VM_Version::CPU_CLWB) \
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declare_constant(VM_Version::CPU_AVX512_VBMI2) \
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declare_constant(VM_Version::CPU_AVX512_VBMI) \
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declare_constant(VM_Version::CPU_HV)
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#endif // CPU_X86_VMSTRUCTS_X86_HPP
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@ -44,6 +44,7 @@ int VM_Version::_model;
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int VM_Version::_stepping;
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bool VM_Version::_has_intel_jcc_erratum;
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VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
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const char* VM_Version::_features_names[] = { FEATURES_NAMES };
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// Address of instruction which causes SEGV
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address VM_Version::_cpuinfo_segv_addr = 0;
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@ -772,65 +773,14 @@ void VM_Version::get_processor_features() {
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}
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char buf[512];
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int res = jio_snprintf(buf, sizeof(buf),
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"(%u cores per cpu, %u threads per core) family %d model %d stepping %d microcode 0x%x"
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"%s%s%s%s%s%s%s%s%s%s" "%s%s%s%s%s%s%s%s%s%s" "%s%s%s%s%s%s%s%s%s%s" "%s%s%s%s%s%s%s%s%s%s" "%s%s%s%s%s%s",
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cores_per_cpu(), threads_per_core(),
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cpu_family(), _model, _stepping, os::cpu_microcode_revision(),
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(supports_cmov() ? ", cmov" : ""),
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(supports_cmpxchg8() ? ", cx8" : ""),
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(supports_fxsr() ? ", fxsr" : ""),
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(supports_mmx() ? ", mmx" : ""),
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(supports_sse() ? ", sse" : ""),
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(supports_sse2() ? ", sse2" : ""),
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(supports_sse3() ? ", sse3" : ""),
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(supports_ssse3()? ", ssse3": ""),
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(supports_sse4_1() ? ", sse4.1" : ""),
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(supports_sse4_2() ? ", sse4.2" : ""),
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(supports_popcnt() ? ", popcnt" : ""),
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(supports_vzeroupper() ? ", vzeroupper" : ""),
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(supports_avx() ? ", avx" : ""),
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(supports_avx2() ? ", avx2" : ""),
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(supports_aes() ? ", aes" : ""),
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(supports_clmul() ? ", clmul" : ""),
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(supports_erms() ? ", erms" : ""),
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(supports_rtm() ? ", rtm" : ""),
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(supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
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(supports_lzcnt() ? ", lzcnt": ""),
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(supports_sse4a() ? ", sse4a": ""),
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(supports_ht() ? ", ht": ""),
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(supports_tsc() ? ", tsc": ""),
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(supports_tscinv_bit() ? ", tscinvbit": ""),
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(supports_tscinv() ? ", tscinv": ""),
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(supports_bmi1() ? ", bmi1" : ""),
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(supports_bmi2() ? ", bmi2" : ""),
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(supports_adx() ? ", adx" : ""),
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(supports_evex() ? ", avx512f" : ""),
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(supports_avx512dq() ? ", avx512dq" : ""),
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(supports_avx512pf() ? ", avx512pf" : ""),
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(supports_avx512er() ? ", avx512er" : ""),
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(supports_avx512cd() ? ", avx512cd" : ""),
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(supports_avx512bw() ? ", avx512bw" : ""),
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(supports_avx512vl() ? ", avx512vl" : ""),
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(supports_avx512_vpopcntdq() ? ", avx512_vpopcntdq" : ""),
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(supports_avx512_vpclmulqdq() ? ", avx512_vpclmulqdq" : ""),
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(supports_avx512_vbmi() ? ", avx512_vbmi" : ""),
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(supports_avx512_vbmi2() ? ", avx512_vbmi2" : ""),
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(supports_avx512_vaes() ? ", avx512_vaes" : ""),
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(supports_avx512_vnni() ? ", avx512_vnni" : ""),
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(supports_sha() ? ", sha" : ""),
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(supports_fma() ? ", fma" : ""),
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(supports_clflush() ? ", clflush" : ""),
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(supports_clflushopt() ? ", clflushopt" : ""),
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(supports_clwb() ? ", clwb" : ""));
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assert(res > 0, "not enough temporary space allocated"); // increase 'buf' size
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int res = jio_snprintf(
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buf, sizeof(buf),
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"(%u cores per cpu, %u threads per core) family %d model %d stepping %d microcode 0x%x",
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cores_per_cpu(), threads_per_core(),
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cpu_family(), _model, _stepping, os::cpu_microcode_revision());
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assert(res > 0, "not enough temporary space allocated");
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assert(exact_log2(CPU_MAX_FEATURE) + 1 == sizeof(_features_names) / sizeof(char*), "wrong size features_names");
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insert_features_names(buf + res, sizeof(buf) - res, _features_names);
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_features_string = os::strdup(buf);
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@ -298,59 +298,87 @@ protected:
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static address _cpuinfo_segv_addr; // address of instruction which causes SEGV
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static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
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enum Feature_Flag {
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CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX)
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CPU_CMOV = (1 << 1),
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CPU_FXSR = (1 << 2),
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CPU_HT = (1 << 3),
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CPU_MMX = (1 << 4),
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CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions
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// may not necessarily support other 3dnow instructions
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CPU_SSE = (1 << 6),
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CPU_SSE2 = (1 << 7),
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CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX)
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CPU_SSSE3 = (1 << 9),
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CPU_SSE4A = (1 << 10),
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CPU_SSE4_1 = (1 << 11),
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CPU_SSE4_2 = (1 << 12),
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CPU_POPCNT = (1 << 13),
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CPU_LZCNT = (1 << 14),
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CPU_TSC = (1 << 15),
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CPU_TSCINV = (1 << 16),
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CPU_AVX = (1 << 17),
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CPU_AVX2 = (1 << 18),
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CPU_AES = (1 << 19),
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CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions
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CPU_CLMUL = (1 << 21), // carryless multiply for CRC
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CPU_BMI1 = (1 << 22),
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CPU_BMI2 = (1 << 23),
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CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions
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CPU_ADX = (1 << 25),
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CPU_AVX512F = (1 << 26), // AVX 512bit foundation instructions
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CPU_AVX512DQ = (1 << 27),
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CPU_AVX512PF = (1 << 28),
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CPU_AVX512ER = (1 << 29),
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CPU_AVX512CD = (1 << 30)
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// Keeping sign bit 31 unassigned.
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enum Feature_Flag : uint64_t {
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CPU_CX8 = (1ULL << 0), // next bits are from cpuid 1 (EDX)
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CPU_CMOV = (1ULL << 1),
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CPU_FXSR = (1ULL << 2),
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CPU_HT = (1ULL << 3),
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CPU_MMX = (1ULL << 4),
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CPU_3DNOW_PREFETCH = (1ULL << 5), // Processor supports 3dnow prefetch and prefetchw instructions
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// may not necessarily support other 3dnow instructions
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CPU_SSE = (1ULL << 6),
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CPU_SSE2 = (1ULL << 7),
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CPU_SSE3 = (1ULL << 8), // SSE3 comes from cpuid 1 (ECX)
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CPU_SSSE3 = (1ULL << 9),
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CPU_SSE4A = (1ULL << 10),
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CPU_SSE4_1 = (1ULL << 11),
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CPU_SSE4_2 = (1ULL << 12),
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CPU_POPCNT = (1ULL << 13),
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CPU_LZCNT = (1ULL << 14),
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CPU_TSC = (1ULL << 15),
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CPU_TSCINV_BIT = (1ULL << 16),
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CPU_TSCINV = (1ULL << 17),
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CPU_AVX = (1ULL << 18),
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CPU_AVX2 = (1ULL << 19),
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CPU_AES = (1ULL << 20),
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CPU_ERMS = (1ULL << 21), // enhanced 'rep movsb/stosb' instructions
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CPU_CLMUL = (1ULL << 22), // carryless multiply for CRC
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CPU_BMI1 = (1ULL << 23),
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CPU_BMI2 = (1ULL << 24),
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CPU_RTM = (1ULL << 25), // Restricted Transactional Memory instructions
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CPU_ADX = (1ULL << 26),
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CPU_AVX512F = (1ULL << 27), // AVX 512bit foundation instructions
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CPU_AVX512DQ = (1ULL << 28),
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CPU_AVX512PF = (1ULL << 29),
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CPU_AVX512ER = (1ULL << 30),
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CPU_AVX512CD = (1ULL << 31),
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CPU_AVX512BW = (1ULL << 32), // Byte and word vector instructions
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CPU_AVX512VL = (1ULL << 33), // EVEX instructions with smaller vector length
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CPU_SHA = (1ULL << 34), // SHA instructions
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CPU_FMA = (1ULL << 35), // FMA instructions
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CPU_VZEROUPPER = (1ULL << 36), // Vzeroupper instruction
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CPU_AVX512_VPOPCNTDQ = (1ULL << 37), // Vector popcount
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CPU_AVX512_VPCLMULQDQ = (1ULL << 38), // Vector carryless multiplication
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CPU_AVX512_VAES = (1ULL << 39), // Vector AES instruction
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CPU_AVX512_VNNI = (1ULL << 40), // Vector Neural Network Instructions
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CPU_FLUSH = (1ULL << 41), // flush instruction
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CPU_FLUSHOPT = (1ULL << 42), // flusopth instruction
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CPU_CLWB = (1ULL << 43), // clwb instruction
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CPU_AVX512_VBMI2 = (1ULL << 44), // VBMI2 shift left double instructions
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CPU_AVX512_VBMI = (1ULL << 45), // Vector BMI instructions
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CPU_HV = (1ULL << 46), // Hypervisor instructions
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CPU_MAX_FEATURE = CPU_HV
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};
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#define CPU_AVX512BW ((uint64_t)UCONST64( 0x100000000)) // enums are limited to 31 bit
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#define CPU_AVX512VL ((uint64_t)UCONST64( 0x200000000)) // EVEX instructions with smaller vector length
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#define CPU_SHA ((uint64_t)UCONST64( 0x400000000)) // SHA instructions
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#define CPU_FMA ((uint64_t)UCONST64( 0x800000000)) // FMA instructions
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#define CPU_VZEROUPPER ((uint64_t)UCONST64( 0x1000000000)) // Vzeroupper instruction
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#define CPU_AVX512_VPOPCNTDQ ((uint64_t)UCONST64( 0x2000000000)) // Vector popcount
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#define CPU_AVX512_VPCLMULQDQ ((uint64_t)UCONST64( 0x4000000000)) // Vector carryless multiplication
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#define CPU_AVX512_VAES ((uint64_t)UCONST64( 0x8000000000)) // Vector AES instructions
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#define CPU_AVX512_VNNI ((uint64_t)UCONST64( 0x10000000000)) // Vector Neural Network Instructions
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#define CPU_FLUSH ((uint64_t)UCONST64( 0x20000000000)) // flush instruction
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#define CPU_FLUSHOPT ((uint64_t)UCONST64( 0x40000000000)) // flushopt instruction
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#define CPU_CLWB ((uint64_t)UCONST64( 0x80000000000)) // clwb instruction
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#define CPU_AVX512_VBMI2 ((uint64_t)UCONST64(0x100000000000)) // VBMI2 shift left double instructions
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#define CPU_AVX512_VBMI ((uint64_t)UCONST64(0x200000000000)) // Vector BMI instructions
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#define CPU_HV_PRESENT ((uint64_t)UCONST64(0x400000000000)) // for hypervisor detection
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#define FEATURES_NAMES \
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"cx8", "cmov", "fxsr", "ht", \
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"mmx", "3dnowpref", "sse", "sse2", \
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"sse3", "ssse3", "sse4a", "sse4.1", \
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"sse4.2", "popcnt", "lzcnt", "tsc", \
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"tscinvbit", "tscinv", "avx", "avx2", \
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"aes", "erms", "clmul", "bmi1", \
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"bmi2", "rtm", "adx", "avx512f", \
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"avx512dq", "avx512pf", "avx512er", "avx512cd", \
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"avx512bw", "avx512vl", "sha", "fma", \
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"vzeroupper", "avx512_vpopcntdq", "avx512_vpclmulqdq", "avx512_vaes", \
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"avx512_vnni", "clflush", "clflushopt", "clwb", \
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"avx512_vmbi2", "avx512_vmbi", "hv"
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// NB! When adding new CPU feature detection consider updating vmStructs_x86.hpp, vmStructs_jvmci.hpp, and VM_Version::get_processor_features().
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static const char* _features_names[];
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// NB! When adding new CPU feature detection consider updating vmStructs_x86.hpp, vmStructs_jvmci.hpp, and VM_Version::get_processor_features().
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enum Extended_Family {
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// AMD
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@ -582,13 +610,13 @@ enum Extended_Family {
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}
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}
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if (_cpuid_info.std_cpuid1_ecx.bits.hv != 0)
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result |= CPU_HV_PRESENT;
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result |= CPU_HV;
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if (_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
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result |= CPU_BMI1;
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if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
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result |= CPU_TSC;
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if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
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result |= CPU_TSCINV;
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result |= CPU_TSCINV_BIT;
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if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
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result |= CPU_AES;
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if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
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@ -618,6 +646,7 @@ enum Extended_Family {
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if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
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result |= CPU_SSE4A;
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}
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// Intel features.
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if (is_intel()) {
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if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
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@ -641,6 +670,13 @@ enum Extended_Family {
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}
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}
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// Composite features.
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if (supports_tscinv_bit() &&
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((is_amd_family() && !is_amd_Barcelona()) ||
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is_intel_tsc_synched_at_init())) {
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result |= CPU_TSCINV;
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}
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return result;
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}
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@ -827,54 +863,54 @@ public:
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//
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// Feature identification
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//
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static bool supports_cpuid() { return _features != 0; }
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static bool supports_cmpxchg8() { return (_features & CPU_CX8) != 0; }
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static bool supports_cmov() { return (_features & CPU_CMOV) != 0; }
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static bool supports_fxsr() { return (_features & CPU_FXSR) != 0; }
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static bool supports_ht() { return (_features & CPU_HT) != 0; }
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static bool supports_mmx() { return (_features & CPU_MMX) != 0; }
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static bool supports_sse() { return (_features & CPU_SSE) != 0; }
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static bool supports_sse2() { return (_features & CPU_SSE2) != 0; }
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static bool supports_sse3() { return (_features & CPU_SSE3) != 0; }
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static bool supports_ssse3() { return (_features & CPU_SSSE3)!= 0; }
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static bool supports_sse4_1() { return (_features & CPU_SSE4_1) != 0; }
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static bool supports_sse4_2() { return (_features & CPU_SSE4_2) != 0; }
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static bool supports_popcnt() { return (_features & CPU_POPCNT) != 0; }
|
||||
static bool supports_avx() { return (_features & CPU_AVX) != 0; }
|
||||
static bool supports_avx2() { return (_features & CPU_AVX2) != 0; }
|
||||
static bool supports_tsc() { return (_features & CPU_TSC) != 0; }
|
||||
static bool supports_aes() { return (_features & CPU_AES) != 0; }
|
||||
static bool supports_erms() { return (_features & CPU_ERMS) != 0; }
|
||||
static bool supports_clmul() { return (_features & CPU_CLMUL) != 0; }
|
||||
static bool supports_rtm() { return (_features & CPU_RTM) != 0; }
|
||||
static bool supports_bmi1() { return (_features & CPU_BMI1) != 0; }
|
||||
static bool supports_bmi2() { return (_features & CPU_BMI2) != 0; }
|
||||
static bool supports_adx() { return (_features & CPU_ADX) != 0; }
|
||||
static bool supports_evex() { return (_features & CPU_AVX512F) != 0; }
|
||||
static bool supports_avx512dq() { return (_features & CPU_AVX512DQ) != 0; }
|
||||
static bool supports_avx512pf() { return (_features & CPU_AVX512PF) != 0; }
|
||||
static bool supports_avx512er() { return (_features & CPU_AVX512ER) != 0; }
|
||||
static bool supports_avx512cd() { return (_features & CPU_AVX512CD) != 0; }
|
||||
static bool supports_avx512bw() { return (_features & CPU_AVX512BW) != 0; }
|
||||
static bool supports_avx512vl() { return (_features & CPU_AVX512VL) != 0; }
|
||||
static bool supports_avx512vlbw() { return (supports_evex() && supports_avx512bw() && supports_avx512vl()); }
|
||||
static bool supports_avx512vldq() { return (supports_evex() && supports_avx512dq() && supports_avx512vl()); }
|
||||
static bool supports_cpuid() { return _features != 0; }
|
||||
static bool supports_cmpxchg8() { return (_features & CPU_CX8) != 0; }
|
||||
static bool supports_cmov() { return (_features & CPU_CMOV) != 0; }
|
||||
static bool supports_fxsr() { return (_features & CPU_FXSR) != 0; }
|
||||
static bool supports_ht() { return (_features & CPU_HT) != 0; }
|
||||
static bool supports_mmx() { return (_features & CPU_MMX) != 0; }
|
||||
static bool supports_sse() { return (_features & CPU_SSE) != 0; }
|
||||
static bool supports_sse2() { return (_features & CPU_SSE2) != 0; }
|
||||
static bool supports_sse3() { return (_features & CPU_SSE3) != 0; }
|
||||
static bool supports_ssse3() { return (_features & CPU_SSSE3)!= 0; }
|
||||
static bool supports_sse4_1() { return (_features & CPU_SSE4_1) != 0; }
|
||||
static bool supports_sse4_2() { return (_features & CPU_SSE4_2) != 0; }
|
||||
static bool supports_popcnt() { return (_features & CPU_POPCNT) != 0; }
|
||||
static bool supports_avx() { return (_features & CPU_AVX) != 0; }
|
||||
static bool supports_avx2() { return (_features & CPU_AVX2) != 0; }
|
||||
static bool supports_tsc() { return (_features & CPU_TSC) != 0; }
|
||||
static bool supports_aes() { return (_features & CPU_AES) != 0; }
|
||||
static bool supports_erms() { return (_features & CPU_ERMS) != 0; }
|
||||
static bool supports_clmul() { return (_features & CPU_CLMUL) != 0; }
|
||||
static bool supports_rtm() { return (_features & CPU_RTM) != 0; }
|
||||
static bool supports_bmi1() { return (_features & CPU_BMI1) != 0; }
|
||||
static bool supports_bmi2() { return (_features & CPU_BMI2) != 0; }
|
||||
static bool supports_adx() { return (_features & CPU_ADX) != 0; }
|
||||
static bool supports_evex() { return (_features & CPU_AVX512F) != 0; }
|
||||
static bool supports_avx512dq() { return (_features & CPU_AVX512DQ) != 0; }
|
||||
static bool supports_avx512pf() { return (_features & CPU_AVX512PF) != 0; }
|
||||
static bool supports_avx512er() { return (_features & CPU_AVX512ER) != 0; }
|
||||
static bool supports_avx512cd() { return (_features & CPU_AVX512CD) != 0; }
|
||||
static bool supports_avx512bw() { return (_features & CPU_AVX512BW) != 0; }
|
||||
static bool supports_avx512vl() { return (_features & CPU_AVX512VL) != 0; }
|
||||
static bool supports_avx512vlbw() { return (supports_evex() && supports_avx512bw() && supports_avx512vl()); }
|
||||
static bool supports_avx512vldq() { return (supports_evex() && supports_avx512dq() && supports_avx512vl()); }
|
||||
static bool supports_avx512vlbwdq() { return (supports_evex() && supports_avx512vl() &&
|
||||
supports_avx512bw() && supports_avx512dq()); }
|
||||
static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); }
|
||||
static bool supports_avx512nobw() { return (supports_evex() && !supports_avx512bw()); }
|
||||
static bool supports_avx256only() { return (supports_avx2() && !supports_evex()); }
|
||||
static bool supports_avxonly() { return ((supports_avx2() || supports_avx()) && !supports_evex()); }
|
||||
static bool supports_sha() { return (_features & CPU_SHA) != 0; }
|
||||
static bool supports_fma() { return (_features & CPU_FMA) != 0 && supports_avx(); }
|
||||
static bool supports_vzeroupper() { return (_features & CPU_VZEROUPPER) != 0; }
|
||||
static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); }
|
||||
static bool supports_avx512nobw() { return (supports_evex() && !supports_avx512bw()); }
|
||||
static bool supports_avx256only() { return (supports_avx2() && !supports_evex()); }
|
||||
static bool supports_avxonly() { return ((supports_avx2() || supports_avx()) && !supports_evex()); }
|
||||
static bool supports_sha() { return (_features & CPU_SHA) != 0; }
|
||||
static bool supports_fma() { return (_features & CPU_FMA) != 0 && supports_avx(); }
|
||||
static bool supports_vzeroupper() { return (_features & CPU_VZEROUPPER) != 0; }
|
||||
static bool supports_avx512_vpopcntdq() { return (_features & CPU_AVX512_VPOPCNTDQ) != 0; }
|
||||
static bool supports_avx512_vpclmulqdq() { return (_features & CPU_AVX512_VPCLMULQDQ) != 0; }
|
||||
static bool supports_avx512_vaes() { return (_features & CPU_AVX512_VAES) != 0; }
|
||||
static bool supports_avx512_vnni() { return (_features & CPU_AVX512_VNNI) != 0; }
|
||||
static bool supports_avx512_vbmi() { return (_features & CPU_AVX512_VBMI) != 0; }
|
||||
static bool supports_avx512_vbmi2() { return (_features & CPU_AVX512_VBMI2) != 0; }
|
||||
static bool supports_hv() { return (_features & CPU_HV_PRESENT) != 0; }
|
||||
static bool supports_avx512_vaes() { return (_features & CPU_AVX512_VAES) != 0; }
|
||||
static bool supports_avx512_vnni() { return (_features & CPU_AVX512_VNNI) != 0; }
|
||||
static bool supports_avx512_vbmi() { return (_features & CPU_AVX512_VBMI) != 0; }
|
||||
static bool supports_avx512_vbmi2() { return (_features & CPU_AVX512_VBMI2) != 0; }
|
||||
static bool supports_hv() { return (_features & CPU_HV) != 0; }
|
||||
|
||||
// Intel features
|
||||
static bool is_intel_family_core() { return is_intel() &&
|
||||
@ -917,12 +953,10 @@ public:
|
||||
|
||||
// Intel and AMD newer cores support fast timestamps well
|
||||
static bool supports_tscinv_bit() {
|
||||
return (_features & CPU_TSCINV) != 0;
|
||||
return (_features & CPU_TSCINV_BIT) != 0;
|
||||
}
|
||||
static bool supports_tscinv() {
|
||||
return supports_tscinv_bit() &&
|
||||
((is_amd_family() && !is_amd_Barcelona()) ||
|
||||
is_intel_tsc_synched_at_init());
|
||||
return (_features & CPU_TSCINV) != 0;
|
||||
}
|
||||
|
||||
// Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
|
||||
@ -998,10 +1032,10 @@ public:
|
||||
// not synchronize with other memory ops. it needs a preceding
|
||||
// and trailing StoreStore fence
|
||||
//
|
||||
// clwb is an optional, intel-specific instruction optional which
|
||||
// clwb is an optional intel-specific instruction which
|
||||
// writes back without evicting the line. it also does not
|
||||
// synchronize with other memory ops. so, it also needs a preceding
|
||||
// and trailing StoreStore fence.
|
||||
// synchronize with other memory ops. so, it needs preceding
|
||||
// and trailing StoreStore fences.
|
||||
|
||||
#ifdef _LP64
|
||||
static bool supports_clflush() {
|
||||
@ -1017,13 +1051,12 @@ public:
|
||||
assert ((!Universe::is_fully_initialized() || (_features & CPU_FLUSH) != 0), "clflush should be available");
|
||||
return true;
|
||||
}
|
||||
static bool supports_clflushopt() { return ((_features & CPU_FLUSHOPT) != 0); }
|
||||
static bool supports_clwb() { return ((_features & CPU_CLWB) != 0); }
|
||||
#else
|
||||
static bool supports_clflush() { return ((_features & CPU_FLUSH) != 0); }
|
||||
static bool supports_clflushopt() { return false; }
|
||||
static bool supports_clwb() { return false; }
|
||||
#endif // _LP64
|
||||
// Note: CPU_FLUSHOPT and CPU_CLWB bits should always be zero for 32-bit
|
||||
static bool supports_clflushopt() { return ((_features & CPU_FLUSHOPT) != 0); }
|
||||
static bool supports_clwb() { return ((_features & CPU_CLWB) != 0); }
|
||||
|
||||
// support functions for virtualization detection
|
||||
private:
|
||||
|
||||
@ -49,7 +49,8 @@
|
||||
static_field(CompilerToVM::Data, SharedRuntime_ic_miss_stub, address) \
|
||||
static_field(CompilerToVM::Data, SharedRuntime_handle_wrong_method_stub, address) \
|
||||
static_field(CompilerToVM::Data, SharedRuntime_deopt_blob_unpack, address) \
|
||||
static_field(CompilerToVM::Data, SharedRuntime_deopt_blob_unpack_with_exception_in_tls, address) \
|
||||
static_field(CompilerToVM::Data, SharedRuntime_deopt_blob_unpack_with_exception_in_tls, \
|
||||
address) \
|
||||
static_field(CompilerToVM::Data, SharedRuntime_deopt_blob_uncommon_trap, address) \
|
||||
\
|
||||
static_field(CompilerToVM::Data, ThreadLocalAllocBuffer_alignment_reserve, size_t) \
|
||||
@ -752,7 +753,9 @@
|
||||
#define VM_INT_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant) \
|
||||
LP64_ONLY(declare_constant(frame::arg_reg_save_area_bytes)) \
|
||||
declare_constant(frame::interpreter_frame_sender_sp_offset) \
|
||||
declare_constant(frame::interpreter_frame_last_sp_offset) \
|
||||
declare_constant(frame::interpreter_frame_last_sp_offset)
|
||||
|
||||
#define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant) \
|
||||
declare_constant(VM_Version::CPU_CX8) \
|
||||
declare_constant(VM_Version::CPU_CMOV) \
|
||||
declare_constant(VM_Version::CPU_FXSR) \
|
||||
@ -783,23 +786,22 @@
|
||||
declare_constant(VM_Version::CPU_AVX512DQ) \
|
||||
declare_constant(VM_Version::CPU_AVX512PF) \
|
||||
declare_constant(VM_Version::CPU_AVX512ER) \
|
||||
declare_constant(VM_Version::CPU_AVX512CD)
|
||||
|
||||
#define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant) \
|
||||
declare_preprocessor_constant("VM_Version::CPU_AVX512BW", CPU_AVX512BW) \
|
||||
declare_preprocessor_constant("VM_Version::CPU_AVX512VL", CPU_AVX512VL) \
|
||||
declare_preprocessor_constant("VM_Version::CPU_SHA", CPU_SHA) \
|
||||
declare_preprocessor_constant("VM_Version::CPU_FMA", CPU_FMA) \
|
||||
declare_preprocessor_constant("VM_Version::CPU_VZEROUPPER", CPU_VZEROUPPER) \
|
||||
declare_preprocessor_constant("VM_Version::CPU_AVX512_VPOPCNTDQ", CPU_AVX512_VPOPCNTDQ) \
|
||||
declare_preprocessor_constant("VM_Version::CPU_AVX512_VPCLMULQDQ", CPU_AVX512_VPCLMULQDQ) \
|
||||
declare_preprocessor_constant("VM_Version::CPU_AVX512_VAES", CPU_AVX512_VAES) \
|
||||
declare_preprocessor_constant("VM_Version::CPU_AVX512_VNNI", CPU_AVX512_VNNI) \
|
||||
declare_preprocessor_constant("VM_Version::CPU_FLUSH", CPU_FLUSH) \
|
||||
declare_preprocessor_constant("VM_Version::CPU_FLUSHOPT", CPU_FLUSHOPT) \
|
||||
declare_preprocessor_constant("VM_Version::CPU_CLWB", CPU_CLWB) \
|
||||
declare_preprocessor_constant("VM_Version::CPU_AVX512_VBMI2", CPU_AVX512_VBMI2) \
|
||||
declare_preprocessor_constant("VM_Version::CPU_AVX512_VBMI", CPU_AVX512_VBMI)
|
||||
declare_constant(VM_Version::CPU_AVX512CD) \
|
||||
declare_constant(VM_Version::CPU_AVX512BW) \
|
||||
declare_constant(VM_Version::CPU_AVX512VL) \
|
||||
declare_constant(VM_Version::CPU_SHA) \
|
||||
declare_constant(VM_Version::CPU_FMA) \
|
||||
declare_constant(VM_Version::CPU_VZEROUPPER) \
|
||||
declare_constant(VM_Version::CPU_AVX512_VPOPCNTDQ) \
|
||||
declare_constant(VM_Version::CPU_AVX512_VPCLMULQDQ) \
|
||||
declare_constant(VM_Version::CPU_AVX512_VAES) \
|
||||
declare_constant(VM_Version::CPU_AVX512_VNNI) \
|
||||
declare_constant(VM_Version::CPU_FLUSH) \
|
||||
declare_constant(VM_Version::CPU_FLUSHOPT) \
|
||||
declare_constant(VM_Version::CPU_CLWB) \
|
||||
declare_constant(VM_Version::CPU_AVX512_VBMI2) \
|
||||
declare_constant(VM_Version::CPU_AVX512_VBMI) \
|
||||
declare_constant(VM_Version::CPU_HV)
|
||||
|
||||
#endif
|
||||
|
||||
@ -822,7 +824,6 @@
|
||||
#define VM_ADDRESSES_OS(declare_address, declare_preprocessor_address, declare_function)
|
||||
#endif
|
||||
|
||||
|
||||
//
|
||||
// Instantiation of VMStructEntries, VMTypeEntries and VMIntConstantEntries
|
||||
//
|
||||
|
||||
@ -291,6 +291,22 @@ unsigned int Abstract_VM_Version::jvm_version() {
|
||||
(Abstract_VM_Version::vm_build_number() & 0xFF);
|
||||
}
|
||||
|
||||
void Abstract_VM_Version::insert_features_names(char* buf, size_t buflen, const char* features_names[]) {
|
||||
uint64_t features = _features;
|
||||
uint features_names_index = 0;
|
||||
|
||||
while (features != 0) {
|
||||
if (features & 1) {
|
||||
int res = jio_snprintf(buf, buflen, ", %s", features_names[features_names_index]);
|
||||
assert(res > 0, "not enough temporary space allocated");
|
||||
buf += res;
|
||||
buflen -= res;
|
||||
}
|
||||
features >>= 1;
|
||||
++features_names_index;
|
||||
}
|
||||
}
|
||||
|
||||
bool Abstract_VM_Version::print_matching_lines_from_file(const char* filename, outputStream* st, const char* keywords_to_match[]) {
|
||||
char line[500];
|
||||
FILE* fp = fopen(filename, "r");
|
||||
|
||||
@ -119,13 +119,9 @@ class Abstract_VM_Version: AllStatic {
|
||||
static const char* jdk_debug_level();
|
||||
static const char* printable_jdk_debug_level();
|
||||
|
||||
static uint64_t features() {
|
||||
return _features;
|
||||
}
|
||||
|
||||
static const char* features_string() {
|
||||
return _features_string;
|
||||
}
|
||||
static uint64_t features() { return _features; }
|
||||
static const char* features_string() { return _features_string; }
|
||||
static void insert_features_names(char* buf, size_t buflen, const char* features_names[]);
|
||||
|
||||
static VirtualizationType get_detected_virtualization() {
|
||||
return _detected_virtualization;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user