8340731: Cleanup remaining IA64 references in hotspot code
Reviewed-by: dholmes, aph
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@ -229,8 +229,6 @@ size_t os::rss() {
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// Cpu architecture string
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#if defined(ZERO)
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static char cpu_arch[] = ZERO_LIBARCH;
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#elif defined(IA64)
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static char cpu_arch[] = "ia64";
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#elif defined(IA32)
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static char cpu_arch[] = "i386";
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#elif defined(AMD64)
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@ -1192,8 +1190,6 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
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static Elf32_Half running_arch_code=EM_386;
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#elif (defined AMD64)
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static Elf32_Half running_arch_code=EM_X86_64;
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#elif (defined IA64)
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static Elf32_Half running_arch_code=EM_IA_64;
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#elif (defined __powerpc64__)
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static Elf32_Half running_arch_code=EM_PPC64;
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#elif (defined __powerpc__)
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@ -1214,7 +1210,7 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
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static Elf32_Half running_arch_code=EM_68K;
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#else
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#error Method os::dll_load requires that one of following is defined:\
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IA32, AMD64, IA64, __powerpc__, ARM, S390, ALPHA, MIPS, MIPSEL, PARISC, M68K
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IA32, AMD64, __powerpc__, ARM, S390, ALPHA, MIPS, MIPSEL, PARISC, M68K
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#endif
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// Identify compatibility class for VM's architecture and library's architecture
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@ -55,8 +55,7 @@ static size_t scan_default_hugepagesize() {
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// large_page_size on Linux is used to round up heap size. x86 uses either
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// 2M or 4M page, depending on whether PAE (Physical Address Extensions)
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// mode is enabled. AMD64/EM64T uses 2M page in 64bit mode. IA64 can use
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// page as large as 1G.
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// mode is enabled. AMD64/EM64T uses 2M page in 64bit mode.
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//
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// Here we try to figure out page size by parsing /proc/meminfo and looking
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// for a line with the following format:
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@ -461,26 +461,17 @@ bool os::Linux::get_tick_information(CPUPerfTicks* pticks, int which_logical_cpu
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}
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#ifndef SYS_gettid
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// i386: 224, ia64: 1105, amd64: 186, sparc: 143
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#ifdef __ia64__
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#define SYS_gettid 1105
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// i386: 224, amd64: 186, sparc: 143
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#if defined(__i386__)
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#define SYS_gettid 224
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#elif defined(__amd64__)
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#define SYS_gettid 186
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#elif defined(__sparc__)
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#define SYS_gettid 143
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#else
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#ifdef __i386__
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#define SYS_gettid 224
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#else
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#ifdef __amd64__
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#define SYS_gettid 186
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#else
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#ifdef __sparc__
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#define SYS_gettid 143
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#else
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#error define gettid for the arch
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#endif
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#endif
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#endif
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#error "Define SYS_gettid for this architecture"
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#endif
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#endif
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#endif // SYS_gettid
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// pid_t gettid()
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//
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@ -1778,8 +1769,6 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
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static Elf32_Half running_arch_code=EM_386;
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#elif (defined AMD64) || (defined X32)
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static Elf32_Half running_arch_code=EM_X86_64;
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#elif (defined IA64)
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static Elf32_Half running_arch_code=EM_IA_64;
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#elif (defined __sparc) && (defined _LP64)
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static Elf32_Half running_arch_code=EM_SPARCV9;
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#elif (defined __sparc) && (!defined _LP64)
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@ -1812,7 +1801,7 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
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static Elf32_Half running_arch_code=EM_LOONGARCH;
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#else
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#error Method os::dll_load requires that one of following is defined:\
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AARCH64, ALPHA, ARM, AMD64, IA32, IA64, LOONGARCH64, M68K, MIPS, MIPSEL, PARISC, __powerpc__, __powerpc64__, RISCV, S390, SH, __sparc
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AARCH64, ALPHA, ARM, AMD64, IA32, LOONGARCH64, M68K, MIPS, MIPSEL, PARISC, __powerpc__, __powerpc64__, RISCV, S390, SH, __sparc
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#endif
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// Identify compatibility class for VM's architecture and library's architecture
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@ -2719,8 +2708,6 @@ void os::get_summary_cpu_info(char* cpuinfo, size_t length) {
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strncpy(cpuinfo, "ARM", length);
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#elif defined(IA32)
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strncpy(cpuinfo, "x86_32", length);
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#elif defined(IA64)
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strncpy(cpuinfo, "IA64", length);
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#elif defined(PPC)
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strncpy(cpuinfo, "PPC64", length);
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#elif defined(RISCV)
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@ -960,10 +960,6 @@ static bool get_signal_code_description(const siginfo_t* si, enum_sigcode_desc_t
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{ SIGILL, ILL_PRVREG, "ILL_PRVREG", "Privileged register." },
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{ SIGILL, ILL_COPROC, "ILL_COPROC", "Coprocessor error." },
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{ SIGILL, ILL_BADSTK, "ILL_BADSTK", "Internal stack error." },
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#if defined(IA64) && defined(LINUX)
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{ SIGILL, ILL_BADIADDR, "ILL_BADIADDR", "Unimplemented instruction address" },
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{ SIGILL, ILL_BREAK, "ILL_BREAK", "Application Break instruction" },
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#endif
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{ SIGFPE, FPE_INTDIV, "FPE_INTDIV", "Integer divide by zero." },
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{ SIGFPE, FPE_INTOVF, "FPE_INTOVF", "Integer overflow." },
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{ SIGFPE, FPE_FLTDIV, "FPE_FLTDIV", "Floating-point divide by zero." },
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@ -977,9 +973,6 @@ static bool get_signal_code_description(const siginfo_t* si, enum_sigcode_desc_t
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#if defined(AIX)
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// no explanation found what keyerr would be
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{ SIGSEGV, SEGV_KEYERR, "SEGV_KEYERR", "key error" },
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#endif
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#if defined(IA64) && !defined(AIX)
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{ SIGSEGV, SEGV_PSTKOVF, "SEGV_PSTKOVF", "Paragraph stack overflow" },
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#endif
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{ SIGBUS, BUS_ADRALN, "BUS_ADRALN", "Invalid address alignment." },
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{ SIGBUS, BUS_ADRERR, "BUS_ADRERR", "Nonexistent physical address." },
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@ -956,7 +956,6 @@ void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) {
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// Each entry is reg_pressure_per_value,number_of_regs
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// RegL RegI RegFlags RegF RegD INTPRESSURE FLOATPRESSURE
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// IA32 2 1 1 1 1 6 6
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// IA64 1 1 1 1 1 50 41
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// SPARC 2 2 2 2 2 48 (24) 52 (26)
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// SPARCV9 2 2 2 2 2 48 (24) 52 (26)
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// AMD64 1 1 1 1 1 14 15
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@ -224,10 +224,6 @@ void GraphKit::gen_stub(address C_function,
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store_to_memory(control(), adr_sp, null(), T_ADDRESS, MemNode::unordered);
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// Clear last_Java_pc
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store_to_memory(control(), adr_last_Java_pc, null(), T_ADDRESS, MemNode::unordered);
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#if (defined(IA64) && !defined(AIX))
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Node* adr_last_Java_fp = basic_plus_adr(top(), thread, in_bytes(JavaThread::last_Java_fp_offset()));
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store_to_memory(control(), adr_last_Java_fp, null(), T_ADDRESS, MemNode::unordered);
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#endif
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// For is-fancy-jump, the C-return value is also the branch target
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Node* target = map()->in(TypeFunc::Parms);
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@ -196,7 +196,7 @@ private:
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// non-pinned LoadNode by the pinned LoadNode.
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ControlDependency _control_dependency;
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// On platforms with weak memory ordering (e.g., PPC, Ia64) we distinguish
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// On platforms with weak memory ordering (e.g., PPC) we distinguish
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// loads that can be reordered, and such requiring acquire semantics to
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// adhere to the Java specification. The required behaviour is stored in
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// this field.
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@ -566,7 +566,7 @@ public:
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// Store value; requires Store, Address and Value
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class StoreNode : public MemNode {
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private:
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// On platforms with weak memory ordering (e.g., PPC, Ia64) we distinguish
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// On platforms with weak memory ordering (e.g., PPC) we distinguish
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// stores that can be reordered, and such requiring release semantics to
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// adhere to the Java specification. The required behaviour is stored in
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// this field.
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@ -383,7 +383,7 @@ bool PhaseOutput::need_stack_bang(int frame_size_in_bytes) const {
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bool PhaseOutput::need_register_stack_bang() const {
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// Determine if we need to generate a register stack overflow check.
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// This is only used on architectures which have split register
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// and memory stacks (ie. IA64).
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// and memory stacks.
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// Bang if the method is not a stub function and has java calls
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return (C->stub_function() == nullptr && C->has_java_calls());
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}
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@ -187,7 +187,6 @@ const char* Abstract_VM_Version::vm_release() {
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#define CPU AARCH64_ONLY("aarch64") \
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AMD64_ONLY("amd64") \
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IA32_ONLY("x86") \
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IA64_ONLY("ia64") \
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S390_ONLY("s390") \
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RISCV64_ONLY("riscv64")
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#endif // !ZERO
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@ -607,9 +607,6 @@ Deoptimization::UnrollBlock* Deoptimization::fetch_unroll_info_helper(JavaThread
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// where it will be very difficult to figure out what went wrong. Better
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// to die an early death here than some very obscure death later when the
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// trail is cold.
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// Note: on ia64 this guarantee can be fooled by frames with no memory stack
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// in that it will fail to detect a problem when there is one. This needs
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// more work in tiger timeframe.
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guarantee(array->unextended_sp() == unpack_sp, "vframe_array_head must contain the vframeArray to unpack");
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int number_of_frames = array->frames();
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@ -2342,8 +2339,7 @@ JRT_ENTRY(void, Deoptimization::uncommon_trap_inner(JavaThread* current, jint tr
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}
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// Setting +ProfileTraps fixes the following, on all platforms:
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// 4852688: ProfileInterpreter is off by default for ia64. The result is
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// infinite heroic-opt-uncommon-trap/deopt/recompile cycles, since the
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// The result is infinite heroic-opt-uncommon-trap/deopt/recompile cycles, since the
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// recompile relies on a MethodData* to record heroic opt failures.
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// Whether the interpreter is producing MDO data or not, we also need
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@ -164,10 +164,9 @@ class frame {
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void patch_pc(Thread* thread, address pc);
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// Every frame needs to return a unique id which distinguishes it from all other frames.
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// For sparc and ia32 use sp. ia64 can have memory frames that are empty so multiple frames
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// will have identical sp values. For ia64 the bsp (fp) value will serve. No real frame
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// should have an id() of null so it is a distinguishing value for an unmatchable frame.
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// We also have relationals which allow comparing a frame to anoth frame's id() allow
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// For sparc and ia32 use sp.
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// No real frame should have an id() of null so it is a distinguishing value for an unmatchable frame.
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// We also have relationals which allow comparing a frame to another frame's id() allowing
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// us to distinguish younger (more recent activation) from older (less recent activations)
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// A null id is only valid when comparing for equality.
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@ -116,11 +116,6 @@ JavaCallWrapper::~JavaCallWrapper() {
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ThreadStateTransition::transition_from_java(_thread, _thread_in_vm);
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// State has been restored now make the anchor frame visible for the profiler.
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// Do this after the transition because this allows us to put an assert
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// the Java->vm transition which checks to see that stack is not walkable
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// on sparc/ia64 which will catch violations of the resetting of last_Java_frame
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// invariants (i.e. _flags always cleared on return to Java)
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_thread->frame_anchor()->copy(&_anchor);
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// Release handles after we are marked as being inside the VM again, since this
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@ -859,8 +859,7 @@ class os: AllStatic {
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// We don't attempt to become a debugger, so we only follow frames if that
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// does not require a lookup in the unwind table, which is part of the binary
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// file but may be unsafe to read after a fatal error. So on x86, we can
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// only walk stack if %ebp is used as frame pointer; on ia64, it's not
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// possible to walk C stack without having the unwind table.
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// only walk stack if %ebp is used as frame pointer.
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static bool is_first_C_frame(frame *fr);
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static frame get_sender_for_C_frame(frame *fr);
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@ -200,7 +200,7 @@ bool Relocator::handle_code_changes() {
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bool Relocator::is_opcode_lookupswitch(Bytecodes::Code bc) {
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switch (bc) {
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case Bytecodes::_tableswitch: return false;
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case Bytecodes::_lookupswitch: // not rewritten on ia64
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case Bytecodes::_lookupswitch:
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case Bytecodes::_fast_linearswitch: // rewritten _lookupswitch
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case Bytecodes::_fast_binaryswitch: return true; // rewritten _lookupswitch
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default: ShouldNotReachHere();
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@ -34,11 +34,10 @@ ElfFuncDescTable::ElfFuncDescTable(FILE* file, Elf_Shdr shdr, int index) :
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_section(file, shdr), _file(file), _index(index) {
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assert(file, "null file handle");
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// The actual function address (i.e. function entry point) is always the
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// first value in the function descriptor (on IA64 and PPC64 they look as follows):
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// first value in the function descriptor (on PPC64 they look as follows):
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// PPC64: [function entry point, TOC pointer, environment pointer]
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// IA64 : [function entry point, GP (global pointer) value]
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// Unfortunately 'shdr.sh_entsize' doesn't always seem to contain this size (it's zero on PPC64) so we can't assert
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// assert(IA64_ONLY(2) PPC64_ONLY(3) * sizeof(address) == shdr.sh_entsize, "Size mismatch for '.opd' section entries");
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// assert(PPC64_ONLY(3) * sizeof(address) == shdr.sh_entsize, "Size mismatch for '.opd' section entries");
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_status = _section.status();
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}
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@ -35,9 +35,8 @@
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/*
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On PowerPC-64 (and other architectures like for example IA64) a pointer to a
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function is not just a plain code address, but instead a pointer to a so called
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function descriptor (which is simply a structure containing 3 pointers).
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On PowerPC-64 a pointer to a function is not just a plain code address, but instead a pointer
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to a so-called function descriptor (which is simply a structure containing 3 pointers).
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This fact is also reflected in the ELF ABI for PowerPC-64.
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On architectures like x86 or SPARC, the ELF symbol table contains the start
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@ -458,18 +458,6 @@
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#define NOT_IA32(code) code
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#endif
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// This is a REALLY BIG HACK, but on AIX <sys/systemcfg.h> unconditionally defines IA64.
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// At least on AIX 7.1 this is a real problem because 'systemcfg.h' is indirectly included
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// by 'pthread.h' and other common system headers.
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#if defined(IA64) && !defined(AIX)
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#define IA64_ONLY(code) code
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#define NOT_IA64(code)
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#else
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#define IA64_ONLY(code)
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#define NOT_IA64(code) code
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#endif
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#ifdef AMD64
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#define AMD64_ONLY(code) code
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#define NOT_AMD64(code)
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