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8340643: RISC-V: Small refactoring for sub/subw macro-assembler routines

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Reviewed-by: fyang, luhenry
This commit is contained in:
Gui Cao 2024-09-25 02:29:06 +00:00 committed by Fei Yang
parent c0fcb258bb
commit a37bb2e037
1 changed files with 2 additions and 14 deletions

16
src/hotspot/cpu/riscv/macroAssembler_riscv.cpp

@ -2085,23 +2085,11 @@ void MacroAssembler::addw(Register Rd, Register Rn, int32_t increment, Register
}
void MacroAssembler::sub(Register Rd, Register Rn, int64_t decrement, Register temp) {
if (is_simm12(-decrement)) {
addi(Rd, Rn, -decrement);
} else {
assert_different_registers(Rn, temp);
li(temp, decrement);
sub(Rd, Rn, temp);
}
add(Rd, Rn, -decrement, temp);
}
void MacroAssembler::subw(Register Rd, Register Rn, int32_t decrement, Register temp) {
if (is_simm12(-decrement)) {
addiw(Rd, Rn, -decrement);
} else {
assert_different_registers(Rn, temp);
li(temp, decrement);
subw(Rd, Rn, temp);
}
addw(Rd, Rn, -decrement, temp);
}
void MacroAssembler::andrw(Register Rd, Register Rs1, Register Rs2) {