8321269: Require platforms to define DEFAULT_CACHE_LINE_SIZE
Reviewed-by: stefank, stuefe, dholmes
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@ -42,6 +42,8 @@ const bool CCallingConventionRequiresIntsAsLongs = false;
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// and Operational Models for ARMv8"
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#define CPU_MULTI_COPY_ATOMIC
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#define DEFAULT_CACHE_LINE_SIZE 64
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// According to the ARMv8 ARM, "Concurrent modification and execution
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// of instructions can lead to the resulting instruction performing
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// any behavior that can be achieved by executing any sequence of
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@ -49,6 +49,8 @@ const bool HaveVFP = true;
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// arm32 is not specified as multi-copy-atomic
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// So we must not #define CPU_MULTI_COPY_ATOMIC
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#define DEFAULT_CACHE_LINE_SIZE 64
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#define STUBROUTINES_MD_HPP "stubRoutines_arm.hpp"
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#define INTERP_MASM_MD_HPP "interp_masm_arm.hpp"
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#define TEMPLATETABLE_MD_HPP "templateTable_arm.hpp"
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@ -30,6 +30,8 @@
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#define SUPPORTS_NATIVE_CX8
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#endif
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#define DEFAULT_CACHE_LINE_SIZE 64
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#define SUPPORT_MONITOR_COUNT
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#include <ffi.h>
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@ -604,7 +604,7 @@ const bool support_IRIW_for_not_multiple_copy_atomic_cpu = PPC64_ONLY(true) NOT_
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// The expected size in bytes of a cache line, used to pad data structures.
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#ifndef DEFAULT_CACHE_LINE_SIZE
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#define DEFAULT_CACHE_LINE_SIZE 64
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#error "Platform should define DEFAULT_CACHE_LINE_SIZE"
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#endif
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