diff --git a/src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp b/src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp index f204b8d9cfa..2293d70c8da 100644 --- a/src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp @@ -42,6 +42,8 @@ const bool CCallingConventionRequiresIntsAsLongs = false; // and Operational Models for ARMv8" #define CPU_MULTI_COPY_ATOMIC +#define DEFAULT_CACHE_LINE_SIZE 64 + // According to the ARMv8 ARM, "Concurrent modification and execution // of instructions can lead to the resulting instruction performing // any behavior that can be achieved by executing any sequence of diff --git a/src/hotspot/cpu/arm/globalDefinitions_arm.hpp b/src/hotspot/cpu/arm/globalDefinitions_arm.hpp index 5832b5451e9..2041cf9e17e 100644 --- a/src/hotspot/cpu/arm/globalDefinitions_arm.hpp +++ b/src/hotspot/cpu/arm/globalDefinitions_arm.hpp @@ -49,6 +49,8 @@ const bool HaveVFP = true; // arm32 is not specified as multi-copy-atomic // So we must not #define CPU_MULTI_COPY_ATOMIC +#define DEFAULT_CACHE_LINE_SIZE 64 + #define STUBROUTINES_MD_HPP "stubRoutines_arm.hpp" #define INTERP_MASM_MD_HPP "interp_masm_arm.hpp" #define TEMPLATETABLE_MD_HPP "templateTable_arm.hpp" diff --git a/src/hotspot/cpu/zero/globalDefinitions_zero.hpp b/src/hotspot/cpu/zero/globalDefinitions_zero.hpp index 138a22d5124..810f7de3cb3 100644 --- a/src/hotspot/cpu/zero/globalDefinitions_zero.hpp +++ b/src/hotspot/cpu/zero/globalDefinitions_zero.hpp @@ -30,6 +30,8 @@ #define SUPPORTS_NATIVE_CX8 #endif +#define DEFAULT_CACHE_LINE_SIZE 64 + #define SUPPORT_MONITOR_COUNT #include diff --git a/src/hotspot/share/utilities/globalDefinitions.hpp b/src/hotspot/share/utilities/globalDefinitions.hpp index 60938408dba..a6bf8a3e7d3 100644 --- a/src/hotspot/share/utilities/globalDefinitions.hpp +++ b/src/hotspot/share/utilities/globalDefinitions.hpp @@ -604,7 +604,7 @@ const bool support_IRIW_for_not_multiple_copy_atomic_cpu = PPC64_ONLY(true) NOT_ // The expected size in bytes of a cache line, used to pad data structures. #ifndef DEFAULT_CACHE_LINE_SIZE - #define DEFAULT_CACHE_LINE_SIZE 64 +#error "Platform should define DEFAULT_CACHE_LINE_SIZE" #endif