8343941: IGV: dump graph at different register allocation steps
Reviewed-by: chagedorn, dfenacci, dlunden
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bd6152f596
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@ -424,6 +424,9 @@ void PhaseChaitin::Register_Allocate() {
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live.compute(_lrg_map.max_lrg_id());
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live.compute(_lrg_map.max_lrg_id());
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_live = &live;
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_live = &live;
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}
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}
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C->print_method(PHASE_INITIAL_LIVENESS, 4);
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// Create the interference graph using virtual copies
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// Create the interference graph using virtual copies
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build_ifg_virtual(); // Include stack slots this time
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build_ifg_virtual(); // Include stack slots this time
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@ -464,6 +467,8 @@ void PhaseChaitin::Register_Allocate() {
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_live = &live;
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_live = &live;
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}
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}
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C->print_method(PHASE_AGGRESSIVE_COALESCING, 4);
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// Build physical interference graph
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// Build physical interference graph
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uint must_spill = 0;
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uint must_spill = 0;
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must_spill = build_ifg_physical(&live_arena);
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must_spill = build_ifg_physical(&live_arena);
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@ -504,6 +509,9 @@ void PhaseChaitin::Register_Allocate() {
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live.compute(_lrg_map.max_lrg_id()); // Compute LIVE
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live.compute(_lrg_map.max_lrg_id()); // Compute LIVE
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_live = &live;
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_live = &live;
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}
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}
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C->print_method(PHASE_INITIAL_SPILLING, 4);
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build_ifg_physical(&live_arena);
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build_ifg_physical(&live_arena);
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_ifg->SquareUp();
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_ifg->SquareUp();
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_ifg->Compute_Effective_Degree();
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_ifg->Compute_Effective_Degree();
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@ -518,6 +526,10 @@ void PhaseChaitin::Register_Allocate() {
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}
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}
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_lrg_map.compress_uf_map_for_nodes();
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_lrg_map.compress_uf_map_for_nodes();
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if (OptoCoalesce) {
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C->print_method(PHASE_CONSERVATIVE_COALESCING, 4);
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}
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#ifdef ASSERT
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#ifdef ASSERT
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verify(&live_arena, true);
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verify(&live_arena, true);
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#endif
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#endif
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@ -580,6 +592,9 @@ void PhaseChaitin::Register_Allocate() {
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live.compute(_lrg_map.max_lrg_id());
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live.compute(_lrg_map.max_lrg_id());
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_live = &live;
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_live = &live;
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}
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}
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C->print_method(PHASE_ITERATIVE_SPILLING, 4);
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must_spill = build_ifg_physical(&live_arena);
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must_spill = build_ifg_physical(&live_arena);
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_ifg->SquareUp();
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_ifg->SquareUp();
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_ifg->Compute_Effective_Degree();
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_ifg->Compute_Effective_Degree();
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@ -593,6 +608,11 @@ void PhaseChaitin::Register_Allocate() {
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coalesce.coalesce_driver();
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coalesce.coalesce_driver();
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}
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}
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_lrg_map.compress_uf_map_for_nodes();
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_lrg_map.compress_uf_map_for_nodes();
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if (OptoCoalesce) {
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C->print_method(PHASE_CONSERVATIVE_COALESCING, 4);
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}
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#ifdef ASSERT
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#ifdef ASSERT
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verify(&live_arena, true);
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verify(&live_arena, true);
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#endif
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#endif
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@ -607,6 +627,8 @@ void PhaseChaitin::Register_Allocate() {
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spills = Select();
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spills = Select();
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}
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}
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C->print_method(PHASE_AFTER_ITERATIVE_SPILLING, 4);
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// Count number of Simplify-Select trips per coloring success.
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// Count number of Simplify-Select trips per coloring success.
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_allocator_attempts += _trip_cnt + 1;
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_allocator_attempts += _trip_cnt + 1;
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_allocator_successes += 1;
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_allocator_successes += 1;
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@ -614,9 +636,13 @@ void PhaseChaitin::Register_Allocate() {
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// Peephole remove copies
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// Peephole remove copies
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post_allocate_copy_removal();
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post_allocate_copy_removal();
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C->print_method(PHASE_POST_ALLOCATION_COPY_REMOVAL, 4);
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// Merge multidefs if multiple defs representing the same value are used in a single block.
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// Merge multidefs if multiple defs representing the same value are used in a single block.
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merge_multidefs();
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merge_multidefs();
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C->print_method(PHASE_MERGE_MULTI_DEFS, 4);
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#ifdef ASSERT
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#ifdef ASSERT
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// Verify the graph after RA.
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// Verify the graph after RA.
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verify(&live_arena);
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verify(&live_arena);
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@ -645,6 +671,8 @@ void PhaseChaitin::Register_Allocate() {
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// Convert CISC spills
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// Convert CISC spills
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fixup_spills();
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fixup_spills();
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C->print_method(PHASE_FIX_UP_SPILLS, 4);
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// Log regalloc results
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// Log regalloc results
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CompileLog* log = Compile::current()->log();
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CompileLog* log = Compile::current()->log();
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if (log != nullptr) {
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if (log != nullptr) {
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@ -93,6 +93,15 @@
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flags(BEFORE_MATCHING, "Before matching") \
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flags(BEFORE_MATCHING, "Before matching") \
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flags(MATCHING, "After matching") \
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flags(MATCHING, "After matching") \
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flags(GLOBAL_CODE_MOTION, "Global code motion") \
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flags(GLOBAL_CODE_MOTION, "Global code motion") \
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flags(INITIAL_LIVENESS, "Initial liveness") \
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flags(AGGRESSIVE_COALESCING, "Aggressive coalescing") \
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flags(INITIAL_SPILLING, "Initial spilling") \
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flags(CONSERVATIVE_COALESCING, "Conservative coalescing") \
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flags(ITERATIVE_SPILLING, "Iterative spilling") \
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flags(AFTER_ITERATIVE_SPILLING, "After iterative spilling") \
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flags(POST_ALLOCATION_COPY_REMOVAL, "Post-allocation copy removal") \
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flags(MERGE_MULTI_DEFS, "Merge multiple definitions") \
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flags(FIX_UP_SPILLS, "Fix up spills") \
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flags(REGISTER_ALLOCATION, "Register Allocation") \
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flags(REGISTER_ALLOCATION, "Register Allocation") \
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flags(BLOCK_ORDERING, "Block Ordering") \
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flags(BLOCK_ORDERING, "Block Ordering") \
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flags(PEEPHOLE, "Peephole") \
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flags(PEEPHOLE, "Peephole") \
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@ -104,6 +104,15 @@ public enum CompilePhase {
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BEFORE_MATCHING("Before matching"),
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BEFORE_MATCHING("Before matching"),
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MATCHING("After matching", RegexType.MACH),
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MATCHING("After matching", RegexType.MACH),
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GLOBAL_CODE_MOTION("Global code motion", RegexType.MACH),
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GLOBAL_CODE_MOTION("Global code motion", RegexType.MACH),
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INITIAL_LIVENESS("Initial liveness", RegexType.MACH),
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AGGRESSIVE_COALESCING("Aggressive coalescing", RegexType.MACH),
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INITIAL_SPILLING("Initial spilling", RegexType.MACH),
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CONSERVATIVE_COALESCING("Conservative coalescing", RegexType.MACH, ActionOnRepeat.KEEP_FIRST),
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ITERATIVE_SPILLING("Iterative spilling", RegexType.MACH, ActionOnRepeat.KEEP_FIRST),
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AFTER_ITERATIVE_SPILLING("After iterative spilling", RegexType.MACH),
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POST_ALLOCATION_COPY_REMOVAL("Post-allocation copy removal", RegexType.MACH),
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MERGE_MULTI_DEFS("Merge multiple definitions", RegexType.MACH),
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FIX_UP_SPILLS("Fix up spills", RegexType.MACH),
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REGISTER_ALLOCATION("Register Allocation", RegexType.MACH),
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REGISTER_ALLOCATION("Register Allocation", RegexType.MACH),
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BLOCK_ORDERING("Block Ordering", RegexType.MACH),
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BLOCK_ORDERING("Block Ordering", RegexType.MACH),
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PEEPHOLE("Peephole", RegexType.MACH),
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PEEPHOLE("Peephole", RegexType.MACH),
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