8329035: New Data Destination instructions support
Reviewed-by: kvn, sviswanathan, jbhateja
This commit is contained in:
Steve Dohrmann
parent
7f1dae12e5
commit
ab9b72c50a
src/hotspot/cpu/x86
File diff suppressed because it is too large
Load Diff
@ -789,14 +789,26 @@ private:
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void vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc);
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void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_v, bool evex_r, bool evex_b,
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bool eevex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc);
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bool eevex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool no_flags = false);
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void evex_prefix_ndd(Address adr, int ndd_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc,
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InstructionAttr *attributes, bool no_flags = false);
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void evex_prefix_nf(Address adr, int ndd_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc,
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InstructionAttr *attributes, bool no_flags = false);
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void vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc,
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InstructionAttr *attributes);
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InstructionAttr *attributes, bool nds_is_ndd = false, bool no_flags = false);
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int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
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VexSimdPrefix pre, VexOpcode opc,
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InstructionAttr *attributes, bool src_is_gpr = false);
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InstructionAttr *attributes, bool src_is_gpr = false, bool nds_is_ndd = false, bool no_flags = false);
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int evex_prefix_and_encode_ndd(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
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InstructionAttr *attributes, bool no_flags = false);
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int evex_prefix_and_encode_nf(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
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InstructionAttr *attributes, bool no_flags = false);
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void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
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VexOpcode opc, InstructionAttr *attributes);
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@ -941,13 +953,20 @@ private:
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// the product flag UseIncDec value.
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void decl(Register dst);
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void edecl(Register dst, Register src, bool no_flags);
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void decl(Address dst);
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void edecl(Register dst, Address src, bool no_flags);
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void decq(Address dst);
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void edecq(Register dst, Address src, bool no_flags);
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void incl(Register dst);
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void eincl(Register dst, Register src, bool no_flags);
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void incl(Address dst);
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void eincl(Register dst, Address src, bool no_flags);
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void incq(Register dst);
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void eincq(Register dst, Register src, bool no_flags);
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void incq(Address dst);
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void eincq(Register dst, Address src, bool no_flags);
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// New cpus require use of movsd and movss to avoid partial register stall
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// when loading from memory. But for old Opteron use movlpd instead of movsd.
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@ -1031,6 +1050,7 @@ private:
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#endif
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void vzeroupper_uncached();
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void decq(Register dst);
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void edecq(Register dst, Register src, bool no_flags);
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void pusha();
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void popa();
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@ -1072,23 +1092,35 @@ private:
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void addw(Address dst, Register src);
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void addl(Address dst, int32_t imm32);
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void eaddl(Register dst, Address src, int32_t imm32, bool no_flags);
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void addl(Address dst, Register src);
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void eaddl(Register dst, Address src1, Register src2, bool no_flags);
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void addl(Register dst, int32_t imm32);
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void eaddl(Register dst, Register src, int32_t imm32, bool no_flags);
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void addl(Register dst, Address src);
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void eaddl(Register dst, Register src1, Address src2, bool no_flags);
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void addl(Register dst, Register src);
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void eaddl(Register dst, Register src1, Register src2, bool no_flags);
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void addq(Address dst, int32_t imm32);
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void eaddq(Register dst, Address src, int32_t imm32, bool no_flags);
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void addq(Address dst, Register src);
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void eaddq(Register dst, Address src1, Register src2, bool no_flags);
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void addq(Register dst, int32_t imm32);
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void eaddq(Register dst, Register src, int32_t imm32, bool no_flags);
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void addq(Register dst, Address src);
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void eaddq(Register dst, Register src1, Address src2, bool no_flags);
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void addq(Register dst, Register src);
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void eaddq(Register dst, Register src1, Register src2, bool no_flags);
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#ifdef _LP64
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//Add Unsigned Integers with Carry Flag
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void adcxq(Register dst, Register src);
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void eadcxq(Register dst, Register src1, Register src2);
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//Add Unsigned Integers with Overflow Flag
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void adoxq(Register dst, Register src);
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void eadoxq(Register dst, Register src1, Register src2);
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#endif
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void addr_nop_4();
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@ -1122,16 +1154,25 @@ private:
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void andb(Address dst, Register src);
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void andl(Address dst, int32_t imm32);
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void eandl(Register dst, Address src, int32_t imm32, bool no_flags);
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void andl(Register dst, int32_t imm32);
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void eandl(Register dst, Register src, int32_t imm32, bool no_flags);
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void andl(Register dst, Address src);
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void eandl(Register dst, Register src1, Address src2, bool no_flags);
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void andl(Register dst, Register src);
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void eandl(Register dst, Register src1, Register src2, bool no_flags);
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void andl(Address dst, Register src);
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void andq(Address dst, int32_t imm32);
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void eandq(Register dst, Address src, int32_t imm32, bool no_flags);
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void andq(Register dst, int32_t imm32);
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void eandq(Register dst, Register src, int32_t imm32, bool no_flags);
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void andq(Register dst, Address src);
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void eandq(Register dst, Register src1, Address src2, bool no_flags);
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void andq(Register dst, Register src);
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void eandq(Register dst, Register src1, Register src2, bool no_flags);
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void andq(Address dst, Register src);
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void eandq(Register dst, Address src1, Register src2, bool no_flags);
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// BMI instructions
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void andnl(Register dst, Register src1, Register src2);
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@ -1182,10 +1223,14 @@ private:
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void clwb(Address adr);
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void cmovl(Condition cc, Register dst, Register src);
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void ecmovl(Condition cc, Register dst, Register src1, Register src2);
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void cmovl(Condition cc, Register dst, Address src);
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void ecmovl(Condition cc, Register dst, Register src1, Address src2);
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void cmovq(Condition cc, Register dst, Register src);
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void ecmovq(Condition cc, Register dst, Register src1, Register src2);
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void cmovq(Condition cc, Register dst, Address src);
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void ecmovq(Condition cc, Register dst, Register src1, Address src2);
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void cmpb(Address dst, int imm8);
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@ -1488,25 +1533,41 @@ private:
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void hlt();
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void idivl(Register src);
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void eidivl(Register src, bool no_flags);
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void divl(Register src); // Unsigned division
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void edivl(Register src, bool no_flags); // Unsigned division
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#ifdef _LP64
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void idivq(Register src);
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void eidivq(Register src, bool no_flags);
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void divq(Register src); // Unsigned division
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void edivq(Register src, bool no_flags); // Unsigned division
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#endif
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void imull(Register src);
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void eimull(Register src, bool no_flags);
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void imull(Register dst, Register src);
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void eimull(Register dst, Register src1, Register src2, bool no_flags);
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void imull(Register dst, Register src, int value);
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void eimull(Register dst, Register src, int value, bool no_flags);
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void imull(Register dst, Address src, int value);
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void eimull(Register dst, Address src, int value, bool no_flags);
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void imull(Register dst, Address src);
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void eimull(Register dst, Register src1, Address src2, bool no_flags);
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#ifdef _LP64
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void imulq(Register dst, Register src);
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void eimulq(Register dst, Register src, bool no_flags);
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void eimulq(Register dst, Register src1, Register src2, bool no_flags);
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void imulq(Register dst, Register src, int value);
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void eimulq(Register dst, Register src, int value, bool no_flags);
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void imulq(Register dst, Address src, int value);
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void eimulq(Register dst, Address src, int value, bool no_flags);
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void imulq(Register dst, Address src);
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void eimulq(Register dst, Address src, bool no_flags);
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void eimulq(Register dst, Register src1, Address src2, bool no_flags);
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void imulq(Register dst);
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void eimulq(Register dst, bool no_flags);
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#endif
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// jcc is the generic conditional branch generator to run-
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@ -1565,11 +1626,15 @@ private:
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void size_prefix();
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void lzcntl(Register dst, Register src);
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void elzcntl(Register dst, Register src, bool no_flags);
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void lzcntl(Register dst, Address src);
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void elzcntl(Register dst, Address src, bool no_flags);
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#ifdef _LP64
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void lzcntq(Register dst, Register src);
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void elzcntq(Register dst, Register src, bool no_flags);
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void lzcntq(Register dst, Address src);
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void elzcntq(Register dst, Address src, bool no_flags);
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#endif
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enum Membar_mask_bits {
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@ -1785,11 +1850,15 @@ private:
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// Unsigned multiply with RAX destination register
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void mull(Address src);
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void emull(Address src, bool no_flags);
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void mull(Register src);
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void emull(Register src, bool no_flags);
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#ifdef _LP64
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void mulq(Address src);
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void emulq(Address src, bool no_flags);
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void mulq(Register src);
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void emulq(Register src, bool no_flags);
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void mulxq(Register dst1, Register dst2, Register src);
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#endif
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@ -1802,19 +1871,25 @@ private:
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void mulss(XMMRegister dst, XMMRegister src);
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void negl(Register dst);
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void enegl(Register dst, Register src, bool no_flags);
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void negl(Address dst);
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void enegl(Register dst, Address src, bool no_flags);
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#ifdef _LP64
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void negq(Register dst);
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void enegq(Register dst, Register src, bool no_flags);
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void negq(Address dst);
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void enegq(Register dst, Address src, bool no_flags);
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#endif
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void nop(uint i = 1);
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void notl(Register dst);
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void enotl(Register dst, Register src);
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#ifdef _LP64
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void notq(Register dst);
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void enotq(Register dst, Register src);
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void btsq(Address dst, int imm8);
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void btrq(Address dst, int imm8);
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@ -1822,21 +1897,37 @@ private:
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#endif
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void btq(Register dst, Register src);
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void orw(Register dst, Register src);
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void eorw(Register dst, Register src1, Register src2, bool no_flags);
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void orl(Address dst, int32_t imm32);
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void eorl(Register dst, Address src, int32_t imm32, bool no_flags);
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void orl(Register dst, int32_t imm32);
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void eorl(Register dst, Register src, int32_t imm32, bool no_flags);
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void orl(Register dst, Address src);
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void eorl(Register dst, Register src1, Address src2, bool no_flags);
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void orl(Register dst, Register src);
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void eorl(Register dst, Register src1, Register src2, bool no_flags);
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void orl(Address dst, Register src);
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void eorl(Register dst, Address src1, Register src2, bool no_flags);
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void orb(Address dst, int imm8);
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void eorb(Register dst, Address src, int imm8, bool no_flags);
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void orb(Address dst, Register src);
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void eorb(Register dst, Address src1, Register src2, bool no_flags);
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void orq(Address dst, int32_t imm32);
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void eorq(Register dst, Address src, int32_t imm32, bool no_flags);
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void orq(Address dst, Register src);
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void eorq(Register dst, Address src1, Register src2, bool no_flags);
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void orq(Register dst, int32_t imm32);
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void eorq(Register dst, Register src, int32_t imm32, bool no_flags);
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void orq_imm32(Register dst, int32_t imm32);
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void eorq_imm32(Register dst, Register src, int32_t imm32, bool no_flags);
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void orq(Register dst, Address src);
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void eorq(Register dst, Register src1, Address src2, bool no_flags);
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void orq(Register dst, Register src);
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void eorq(Register dst, Register src1, Register src2, bool no_flags);
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// Pack with signed saturation
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void packsswb(XMMRegister dst, XMMRegister src);
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@ -2022,7 +2113,9 @@ private:
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#endif
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void popcntl(Register dst, Address src);
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void epopcntl(Register dst, Address src, bool no_flags);
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void popcntl(Register dst, Register src);
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void epopcntl(Register dst, Register src, bool no_flags);
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void evpopcntb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
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void evpopcntw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
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@ -2031,7 +2124,9 @@ private:
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#ifdef _LP64
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void popcntq(Register dst, Address src);
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void epopcntq(Register dst, Address src, bool no_flags);
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void popcntq(Register dst, Register src);
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void epopcntq(Register dst, Register src, bool no_flags);
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#endif
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// Prefetches (SSE, SSE2, 3DNOW only)
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@ -2131,10 +2226,13 @@ private:
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void pushq(Address src);
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void rcll(Register dst, int imm8);
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void ercll(Register dst, Register src, int imm8);
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void rclq(Register dst, int imm8);
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void erclq(Register dst, Register src, int imm8);
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void rcrq(Register dst, int imm8);
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void ercrq(Register dst, Register src, int imm8);
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void rcpps(XMMRegister dst, XMMRegister src);
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@ -2145,18 +2243,26 @@ private:
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void ret(int imm16);
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void roll(Register dst);
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void eroll(Register dst, Register src, bool no_flags);
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void roll(Register dst, int imm8);
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void eroll(Register dst, Register src, int imm8, bool no_flags);
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void rorl(Register dst);
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void erorl(Register dst, Register src, bool no_flags);
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void rorl(Register dst, int imm8);
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void erorl(Register dst, Register src, int imm8, bool no_flags);
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#ifdef _LP64
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void rolq(Register dst);
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void erolq(Register dst, Register src, bool no_flags);
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void rolq(Register dst, int imm8);
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void erolq(Register dst, Register src, int imm8, bool no_flags);
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void rorq(Register dst);
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void erorq(Register dst, Register src, bool no_flags);
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void rorq(Register dst, int imm8);
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void erorq(Register dst, Register src, int imm8, bool no_flags);
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void rorxl(Register dst, Register src, int imm8);
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void rorxl(Register dst, Address src, int imm8);
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void rorxq(Register dst, Register src, int imm8);
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@ -2166,25 +2272,41 @@ private:
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void sahf();
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void sall(Register dst, int imm8);
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void esall(Register dst, Register src, int imm8, bool no_flags);
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void sall(Register dst);
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void esall(Register dst, Register src, bool no_flags);
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void sall(Address dst, int imm8);
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void esall(Register dst, Address src, int imm8, bool no_flags);
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void sall(Address dst);
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void esall(Register dst, Address src, bool no_flags);
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void sarl(Address dst, int imm8);
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void esarl(Register dst, Address src, int imm8, bool no_flags);
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void sarl(Address dst);
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void esarl(Register dst, Address src, bool no_flags);
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void sarl(Register dst, int imm8);
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void esarl(Register dst, Register src, int imm8, bool no_flags);
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void sarl(Register dst);
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void esarl(Register dst, Register src, bool no_flags);
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#ifdef _LP64
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void salq(Register dst, int imm8);
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void esalq(Register dst, Register src, int imm8, bool no_flags);
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void salq(Register dst);
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void esalq(Register dst, Register src, bool no_flags);
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void salq(Address dst, int imm8);
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void esalq(Register dst, Address src, int imm8, bool no_flags);
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void salq(Address dst);
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void esalq(Register dst, Address src, bool no_flags);
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void sarq(Address dst, int imm8);
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void esarq(Register dst, Address src, int imm8, bool no_flags);
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void sarq(Address dst);
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void esarq(Register dst, Address src, bool no_flags);
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void sarq(Register dst, int imm8);
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void esarq(Register dst, Register src, int imm8, bool no_flags);
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void sarq(Register dst);
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void esarq(Register dst, Register src, bool no_flags);
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#endif
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void sbbl(Address dst, int32_t imm32);
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@ -2216,29 +2338,47 @@ private:
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void sha256msg2(XMMRegister dst, XMMRegister src);
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void shldl(Register dst, Register src);
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void eshldl(Register dst, Register src1, Register src2, bool no_flags);
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void shldl(Register dst, Register src, int8_t imm8);
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void eshldl(Register dst, Register src1, Register src2, int8_t imm8, bool no_flags);
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void shrdl(Register dst, Register src);
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void eshrdl(Register dst, Register src1, Register src2, bool no_flags);
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void shrdl(Register dst, Register src, int8_t imm8);
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void eshrdl(Register dst, Register src1, Register src2, int8_t imm8, bool no_flags);
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#ifdef _LP64
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void shldq(Register dst, Register src, int8_t imm8);
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void eshldq(Register dst, Register src1, Register src2, int8_t imm8, bool no_flags);
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void shrdq(Register dst, Register src, int8_t imm8);
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void eshrdq(Register dst, Register src1, Register src2, int8_t imm8, bool no_flags);
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#endif
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void shll(Register dst, int imm8);
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||||
void eshll(Register dst, Register src, int imm8, bool no_flags);
|
||||
void shll(Register dst);
|
||||
void eshll(Register dst, Register src, bool no_flags);
|
||||
|
||||
void shlq(Register dst, int imm8);
|
||||
void eshlq(Register dst, Register src, int imm8, bool no_flags);
|
||||
void shlq(Register dst);
|
||||
void eshlq(Register dst, Register src, bool no_flags);
|
||||
|
||||
void shrl(Register dst, int imm8);
|
||||
void eshrl(Register dst, Register src, int imm8, bool no_flags);
|
||||
void shrl(Register dst);
|
||||
void eshrl(Register dst, Register src, bool no_flags);
|
||||
void shrl(Address dst);
|
||||
void eshrl(Register dst, Address src, bool no_flags);
|
||||
void shrl(Address dst, int imm8);
|
||||
void eshrl(Register dst, Address src, int imm8, bool no_flags);
|
||||
|
||||
void shrq(Register dst, int imm8);
|
||||
void eshrq(Register dst, Register src, int imm8, bool no_flags);
|
||||
void shrq(Register dst);
|
||||
void eshrq(Register dst, Register src, bool no_flags);
|
||||
void shrq(Address dst);
|
||||
void eshrq(Register dst, Address src, bool no_flags);
|
||||
void shrq(Address dst, int imm8);
|
||||
void eshrq(Register dst, Address src, int imm8, bool no_flags);
|
||||
|
||||
void smovl(); // QQQ generic?
|
||||
|
||||
@ -2258,20 +2398,32 @@ private:
|
||||
void stmxcsr( Address dst );
|
||||
|
||||
void subl(Address dst, int32_t imm32);
|
||||
void esubl(Register dst, Address src, int32_t imm32, bool no_flags);
|
||||
void subl(Address dst, Register src);
|
||||
void esubl(Register dst, Address src1, Register src2, bool no_flags);
|
||||
void subl(Register dst, int32_t imm32);
|
||||
void esubl(Register dst, Register src, int32_t imm32, bool no_flags);
|
||||
void subl(Register dst, Address src);
|
||||
void esubl(Register dst, Register src1, Address src2, bool no_flags);
|
||||
void subl(Register dst, Register src);
|
||||
void esubl(Register dst, Register src1, Register src2, bool no_flags);
|
||||
|
||||
void subq(Address dst, int32_t imm32);
|
||||
void esubq(Register dst, Address src, int32_t imm32, bool no_flags);
|
||||
void subq(Address dst, Register src);
|
||||
void esubq(Register dst, Address src1, Register src2, bool no_flags);
|
||||
void subq(Register dst, int32_t imm32);
|
||||
void esubq(Register dst, Register src, int32_t imm32, bool no_flags);
|
||||
void subq(Register dst, Address src);
|
||||
void esubq(Register dst, Register src1, Address src2, bool no_flags);
|
||||
void subq(Register dst, Register src);
|
||||
void esubq(Register dst, Register src1, Register src2, bool no_flags);
|
||||
|
||||
// Force generation of a 4 byte immediate value even if it fits into 8bit
|
||||
void subl_imm32(Register dst, int32_t imm32);
|
||||
void esubl_imm32(Register dst, Register src, int32_t imm32, bool no_flags);
|
||||
void subq_imm32(Register dst, int32_t imm32);
|
||||
void esubq_imm32(Register dst, Register src, int32_t imm32, bool no_flags);
|
||||
|
||||
// Subtract Scalar Double-Precision Floating-Point Values
|
||||
void subsd(XMMRegister dst, Address src);
|
||||
@ -2296,9 +2448,13 @@ private:
|
||||
|
||||
// BMI - count trailing zeros
|
||||
void tzcntl(Register dst, Register src);
|
||||
void etzcntl(Register dst, Register src, bool no_flags);
|
||||
void tzcntl(Register dst, Address src);
|
||||
void etzcntl(Register dst, Address src, bool no_flags);
|
||||
void tzcntq(Register dst, Register src);
|
||||
void etzcntq(Register dst, Register src, bool no_flags);
|
||||
void tzcntq(Register dst, Address src);
|
||||
void etzcntq(Register dst, Address src, bool no_flags);
|
||||
|
||||
// Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
|
||||
void ucomisd(XMMRegister dst, Address src);
|
||||
@ -2331,20 +2487,33 @@ private:
|
||||
void xgetbv();
|
||||
|
||||
void xorl(Register dst, int32_t imm32);
|
||||
void exorl(Register dst, Register src, int32_t imm32, bool no_flags);
|
||||
void xorl(Address dst, int32_t imm32);
|
||||
void exorl(Register dst, Address src, int32_t imm32, bool no_flags);
|
||||
void xorl(Register dst, Address src);
|
||||
void exorl(Register dst, Register src1, Address src2, bool no_flags);
|
||||
void xorl(Register dst, Register src);
|
||||
void exorl(Register dst, Register src1, Register src2, bool no_flags);
|
||||
void xorl(Address dst, Register src);
|
||||
void exorl(Register dst, Address src1, Register src2, bool no_flags);
|
||||
|
||||
void xorb(Address dst, Register src);
|
||||
void exorb(Register dst, Address src1, Register src2, bool no_flags);
|
||||
void xorb(Register dst, Address src);
|
||||
void exorb(Register dst, Register src1, Address src2, bool no_flags);
|
||||
void xorw(Register dst, Address src);
|
||||
void exorw(Register dst, Register src1, Address src2, bool no_flags);
|
||||
|
||||
void xorq(Register dst, Address src);
|
||||
void exorq(Register dst, Register src1, Address src2, bool no_flags);
|
||||
void xorq(Address dst, int32_t imm32);
|
||||
void exorq(Register dst, Address src, int32_t imm32, bool no_flags);
|
||||
void xorq(Register dst, Register src);
|
||||
void exorq(Register dst, Register src1, Register src2, bool no_flags);
|
||||
void xorq(Register dst, int32_t imm32);
|
||||
void exorq(Register dst, Register src, int32_t imm32, bool no_flags);
|
||||
void xorq(Address dst, Register src);
|
||||
void exorq(Register dst, Address src1, Register src2, bool no_flags);
|
||||
|
||||
// AVX 3-operands scalar instructions (encoded with VEX prefix)
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user