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8299844: RISC-V: Implement _onSpinWait intrinsic

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Reviewed-by: fjiang, fyang, luhenry
This commit is contained in:
Yadong Wang 2023-01-28 02:17:44 +00:00 committed by Fei Yang
parent 5dfc4ec7d9
commit af564e46b0
8 changed files with 133 additions and 13 deletions
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14
src/hotspot/cpu/riscv/assembler_riscv.hpp
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@ -1,7 +1,7 @@
/*
* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, 2023, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -682,13 +682,13 @@ public:
unsigned insn = 0;
guarantee(predecessor < 16, "predecessor is invalid");
guarantee(successor < 16, "successor is invalid");
patch((address)&insn, 6, 0, 0b001111);
patch((address)&insn, 11, 7, 0b00000);
patch((address)&insn, 6, 0, 0b001111); // opcode
patch((address)&insn, 11, 7, 0b00000); // rd
patch((address)&insn, 14, 12, 0b000);
patch((address)&insn, 19, 15, 0b00000);
patch((address)&insn, 23, 20, successor);
patch((address)&insn, 27, 24, predecessor);
patch((address)&insn, 31, 28, 0b0000);
patch((address)&insn, 19, 15, 0b00000); // rs1
patch((address)&insn, 23, 20, successor); // succ
patch((address)&insn, 27, 24, predecessor); // pred
patch((address)&insn, 31, 28, 0b0000); // fm
emit(insn);
}

4
src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp
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@ -1,7 +1,7 @@
/*
* Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, 2023, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -1924,7 +1924,7 @@ void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
void LIR_Assembler::on_spin_wait() {
Unimplemented();
__ pause();
}
void LIR_Assembler::get_thread(LIR_Opr result_reg) {

4
src/hotspot/cpu/riscv/globals_riscv.hpp
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@ -1,6 +1,6 @@
/*
* Copyright (c) 2000, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, 2023, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -108,6 +108,8 @@ define_pd_global(intx, InlineSmallCode, 1000);
product(bool, UseZicbom, false, EXPERIMENTAL, "Use Zicbom instructions") \
product(bool, UseZicbop, false, EXPERIMENTAL, "Use Zicbop instructions") \
product(bool, UseZicboz, false, EXPERIMENTAL, "Use Zicboz instructions") \
product(bool, UseZihintpause, false, EXPERIMENTAL, \
"Use Zihintpause instructions") \
product(bool, UseRVVForBigIntegerShiftIntrinsics, true, \
"Use RVV instructions for left/right shift of BigInteger")

4
src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
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@ -365,6 +365,10 @@ class MacroAssembler: public Assembler {
return ((predecessor & 0x3) << 2) | (successor & 0x3);
}
void pause() {
fence(w, 0);
}
// prints msg, dumps registers and stops execution
void stop(const char* msg);

19
src/hotspot/cpu/riscv/riscv.ad
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@ -1,7 +1,7 @@
//
// Copyright (c) 2003, 2023, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
// Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
// Copyright (c) 2020, 2023, Huawei Technologies Co., Ltd. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
@ -949,6 +949,7 @@ definitions %{
int_def FDIV_COST ( 2000, 20 * DEFAULT_COST); // fdiv
int_def FSQRT_COST ( 2500, 25 * DEFAULT_COST); // fsqrt
int_def VOLATILE_REF_COST ( 1000, 10 * DEFAULT_COST);
int_def CACHE_MISS_COST ( 2000, 20 * DEFAULT_COST); // typicall cache miss penalty
%}
@ -1815,6 +1816,8 @@ const bool Matcher::match_rule_supported(int opcode) {
}
switch (opcode) {
case Op_OnSpinWait:
return VM_Version::supports_on_spin_wait();
case Op_CacheWB: // fall through
case Op_CacheWBPreSync: // fall through
case Op_CacheWBPostSync:
@ -7872,6 +7875,20 @@ instruct membar_volatile() %{
ins_pipe(pipe_serial);
%}
instruct spin_wait() %{
predicate(UseZihintpause);
match(OnSpinWait);
ins_cost(CACHE_MISS_COST);
format %{ "spin_wait" %}
ins_encode %{
__ pause();
%}
ins_pipe(pipe_serial);
%}
// ============================================================================
// Cast Instructions (Java-level type cast)

5
src/hotspot/cpu/riscv/vm_version_riscv.cpp
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@ -1,6 +1,6 @@
/*
* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, 2023, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -77,6 +77,9 @@ void VM_Version::initialize() {
if (FLAG_IS_DEFAULT(UseZfhmin)) {
FLAG_SET_DEFAULT(UseZfhmin, true);
}
if (FLAG_IS_DEFAULT(UseZihintpause)) {
FLAG_SET_DEFAULT(UseZihintpause, true);
}
}
if (UseZic64b) {

4
src/hotspot/cpu/riscv/vm_version_riscv.hpp
View File

@ -1,7 +1,7 @@
/*
* Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, 2023, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -61,6 +61,8 @@ public:
constexpr static bool supports_stack_watermark_barrier() { return true; }
static bool supports_on_spin_wait() { return UseZihintpause; }
enum Feature_Flag {
#define CPU_FEATURE_FLAGS(decl) \
decl(I, "i", 8) \

92
test/hotspot/jtreg/compiler/onSpinWait/TestOnSpinWaitRISCV64.java Normal file
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@ -0,0 +1,92 @@
/*
* Copyright Amazon.com Inc. or its affiliates. All Rights Reserved.
* Copyright (c) 2023, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*/
/**
* @test TestOnSpinWaitRISCV64
* @summary Checks that java.lang.Thread.onSpinWait is intrinsified with instructions
* @library /test/lib
*
* @requires vm.flagless
* @requires os.arch=="riscv64"
*
* @run driver compiler.onSpinWait.TestOnSpinWaitRISCV64 c1
* @run driver compiler.onSpinWait.TestOnSpinWaitRISCV64 c2
*/
package compiler.onSpinWait;
import java.util.ArrayList;
import java.util.Iterator;
import java.util.ListIterator;
import jdk.test.lib.process.OutputAnalyzer;
import jdk.test.lib.process.ProcessTools;
public class TestOnSpinWaitRISCV64 {
public static void main(String[] args) throws Exception {
String compiler = args[0];
ArrayList<String> command = new ArrayList<String>();
command.add("-XX:+IgnoreUnrecognizedVMOptions");
command.add("-showversion");
command.add("-XX:+UnlockDiagnosticVMOptions");
command.add("-XX:+PrintCompilation");
command.add("-XX:+PrintInlining");
command.add("-XX:+UnlockExperimentalVMOptions");
command.add("-XX:+UseZihintpause");
if (compiler.equals("c2")) {
command.add("-XX:-TieredCompilation");
} else if (compiler.equals("c1")) {
command.add("-XX:+TieredCompilation");
command.add("-XX:TieredStopAtLevel=1");
} else {
throw new RuntimeException("Unknown compiler: " + compiler);
}
command.add("-Xbatch");
command.add(Launcher.class.getName());
ProcessBuilder pb = ProcessTools.createJavaProcessBuilder(command);
OutputAnalyzer analyzer = new OutputAnalyzer(pb.start());
analyzer.shouldHaveExitValue(0);
if (compiler.equals("c2")) {
analyzer.shouldContain("java.lang.Thread::onSpinWait (1 bytes) (intrinsic)");
} else {
analyzer.shouldContain("java.lang.Thread::onSpinWait (1 bytes) intrinsic");
}
}
static class Launcher {
public static void main(final String[] args) throws Exception {
int end = 20_000;
for (int i=0; i < end; i++) {
test();
}
}
static void test() {
java.lang.Thread.onSpinWait();
}
}
}