8131362: aarch64: C2 does not handle large stack offsets
Change spill code to allow large offsets Reviewed-by: kvn, aph
This commit is contained in:
Ed Nevill
parent
259aeb3399
commit
b73ef8ebc6
@ -2167,8 +2167,12 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo
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return 0; // Self copy, no move.
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}
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bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
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(dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
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int src_offset = ra_->reg2offset(src_lo);
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int dst_offset = ra_->reg2offset(dst_lo);
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if (bottom_type()->isa_vect() != NULL) {
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uint len = 4;
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uint ireg = ideal_reg();
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assert(ireg == Op_VecD || ireg == Op_VecX, "must be 64 bit or 128 bit vector");
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if (cbuf) {
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@ -2176,334 +2180,115 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo
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assert((src_lo_rc != rc_int && dst_lo_rc != rc_int), "sanity");
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if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
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// stack->stack
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int src_offset = ra_->reg2offset(src_lo);
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int dst_offset = ra_->reg2offset(dst_lo);
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assert((src_offset & 7) && (dst_offset & 7), "unaligned stack offset");
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len = 8;
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if (ireg == Op_VecD) {
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__ ldr(rscratch1, Address(sp, src_offset));
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__ str(rscratch1, Address(sp, dst_offset));
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__ unspill(rscratch1, true, src_offset);
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__ spill(rscratch1, true, dst_offset);
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} else {
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if (src_offset < 512) {
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__ ldp(rscratch1, rscratch2, Address(sp, src_offset));
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} else {
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__ ldr(rscratch1, Address(sp, src_offset));
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__ ldr(rscratch2, Address(sp, src_offset+4));
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len += 4;
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}
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if (dst_offset < 512) {
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__ stp(rscratch1, rscratch2, Address(sp, dst_offset));
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} else {
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__ str(rscratch1, Address(sp, dst_offset));
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__ str(rscratch2, Address(sp, dst_offset+4));
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len += 4;
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}
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__ spill_copy128(src_offset, dst_offset);
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}
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} else if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
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__ orr(as_FloatRegister(Matcher::_regEncode[dst_lo]),
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__ mov(as_FloatRegister(Matcher::_regEncode[dst_lo]),
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ireg == Op_VecD ? __ T8B : __ T16B,
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as_FloatRegister(Matcher::_regEncode[src_lo]),
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as_FloatRegister(Matcher::_regEncode[src_lo]));
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} else if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
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__ str(as_FloatRegister(Matcher::_regEncode[src_lo]),
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ireg == Op_VecD ? __ D : __ Q,
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Address(sp, ra_->reg2offset(dst_lo)));
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__ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
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ireg == Op_VecD ? __ D : __ Q,
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ra_->reg2offset(dst_lo));
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} else if (src_lo_rc == rc_stack && dst_lo_rc == rc_float) {
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__ ldr(as_FloatRegister(Matcher::_regEncode[dst_lo]),
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ireg == Op_VecD ? __ D : __ Q,
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Address(sp, ra_->reg2offset(src_lo)));
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__ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
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ireg == Op_VecD ? __ D : __ Q,
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ra_->reg2offset(src_lo));
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} else {
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ShouldNotReachHere();
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}
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} else if (st) {
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if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
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// stack->stack
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int src_offset = ra_->reg2offset(src_lo);
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int dst_offset = ra_->reg2offset(dst_lo);
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if (ireg == Op_VecD) {
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st->print("ldr rscratch1, [sp, #%d]", src_offset);
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st->print("str rscratch1, [sp, #%d]", dst_offset);
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}
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} else if (cbuf) {
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MacroAssembler _masm(cbuf);
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switch (src_lo_rc) {
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case rc_int:
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if (dst_lo_rc == rc_int) { // gpr --> gpr copy
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if (is64) {
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__ mov(as_Register(Matcher::_regEncode[dst_lo]),
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as_Register(Matcher::_regEncode[src_lo]));
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} else {
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if (src_offset < 512) {
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st->print("ldp rscratch1, rscratch2, [sp, #%d]", src_offset);
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} else {
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st->print("ldr rscratch1, [sp, #%d]", src_offset);
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st->print("\nldr rscratch2, [sp, #%d]", src_offset+4);
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}
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if (dst_offset < 512) {
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st->print("\nstp rscratch1, rscratch2, [sp, #%d]", dst_offset);
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} else {
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st->print("\nstr rscratch1, [sp, #%d]", dst_offset);
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st->print("\nstr rscratch2, [sp, #%d]", dst_offset+4);
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}
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MacroAssembler _masm(cbuf);
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__ movw(as_Register(Matcher::_regEncode[dst_lo]),
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as_Register(Matcher::_regEncode[src_lo]));
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}
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st->print("\t# vector spill, stack to stack");
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} else if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
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st->print("mov %s, %s\t# vector spill, reg to reg",
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Matcher::regName[dst_lo], Matcher::regName[src_lo]);
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} else if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
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st->print("str %s, [sp, #%d]\t# vector spill, reg to stack",
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Matcher::regName[src_lo], ra_->reg2offset(dst_lo));
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} else if (src_lo_rc == rc_stack && dst_lo_rc == rc_float) {
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st->print("ldr %s, [sp, #%d]\t# vector spill, stack to reg",
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Matcher::regName[dst_lo], ra_->reg2offset(src_lo));
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} else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
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if (is64) {
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__ fmovd(as_FloatRegister(Matcher::_regEncode[dst_lo]),
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as_Register(Matcher::_regEncode[src_lo]));
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} else {
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__ fmovs(as_FloatRegister(Matcher::_regEncode[dst_lo]),
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as_Register(Matcher::_regEncode[src_lo]));
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}
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} else { // gpr --> stack spill
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assert(dst_lo_rc == rc_stack, "spill to bad register class");
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__ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
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}
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}
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return len;
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}
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switch (src_lo_rc) {
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case rc_int:
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if (dst_lo_rc == rc_int) { // gpr --> gpr copy
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if (((src_lo & 1) == 0 && src_lo + 1 == src_hi) &&
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(dst_lo & 1) == 0 && dst_lo + 1 == dst_hi) {
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// 64 bit
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if (cbuf) {
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MacroAssembler _masm(cbuf);
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__ mov(as_Register(Matcher::_regEncode[dst_lo]),
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as_Register(Matcher::_regEncode[src_lo]));
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} else if (st) {
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st->print("mov %s, %s\t# shuffle",
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Matcher::regName[dst_lo],
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Matcher::regName[src_lo]);
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break;
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case rc_float:
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if (dst_lo_rc == rc_int) { // fpr --> gpr copy
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if (is64) {
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__ fmovd(as_Register(Matcher::_regEncode[dst_lo]),
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as_FloatRegister(Matcher::_regEncode[src_lo]));
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} else {
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__ fmovs(as_Register(Matcher::_regEncode[dst_lo]),
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as_FloatRegister(Matcher::_regEncode[src_lo]));
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}
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} else {
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// 32 bit
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if (cbuf) {
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MacroAssembler _masm(cbuf);
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__ movw(as_Register(Matcher::_regEncode[dst_lo]),
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as_Register(Matcher::_regEncode[src_lo]));
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} else if (st) {
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st->print("movw %s, %s\t# shuffle",
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Matcher::regName[dst_lo],
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Matcher::regName[src_lo]);
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} else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
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if (cbuf) {
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__ fmovd(as_FloatRegister(Matcher::_regEncode[dst_lo]),
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as_FloatRegister(Matcher::_regEncode[src_lo]));
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} else {
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__ fmovs(as_FloatRegister(Matcher::_regEncode[dst_lo]),
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as_FloatRegister(Matcher::_regEncode[src_lo]));
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}
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} else { // fpr --> stack spill
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assert(dst_lo_rc == rc_stack, "spill to bad register class");
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__ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
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is64 ? __ D : __ S, dst_offset);
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}
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} else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
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if (((src_lo & 1) == 0 && src_lo + 1 == src_hi) &&
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(dst_lo & 1) == 0 && dst_lo + 1 == dst_hi) {
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// 64 bit
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if (cbuf) {
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MacroAssembler _masm(cbuf);
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__ fmovd(as_FloatRegister(Matcher::_regEncode[dst_lo]),
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as_Register(Matcher::_regEncode[src_lo]));
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} else if (st) {
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st->print("fmovd %s, %s\t# shuffle",
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Matcher::regName[dst_lo],
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Matcher::regName[src_lo]);
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}
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} else {
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// 32 bit
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if (cbuf) {
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MacroAssembler _masm(cbuf);
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__ fmovs(as_FloatRegister(Matcher::_regEncode[dst_lo]),
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as_Register(Matcher::_regEncode[src_lo]));
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} else if (st) {
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st->print("fmovs %s, %s\t# shuffle",
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Matcher::regName[dst_lo],
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Matcher::regName[src_lo]);
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}
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break;
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case rc_stack:
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if (dst_lo_rc == rc_int) { // stack --> gpr load
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__ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
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} else if (dst_lo_rc == rc_float) { // stack --> fpr load
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__ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
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is64 ? __ D : __ S, src_offset);
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} else { // stack --> stack copy
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assert(dst_lo_rc == rc_stack, "spill to bad register class");
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__ unspill(rscratch1, is64, src_offset);
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__ spill(rscratch1, is64, dst_offset);
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}
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} else { // gpr --> stack spill
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assert(dst_lo_rc == rc_stack, "spill to bad register class");
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int dst_offset = ra_->reg2offset(dst_lo);
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if (((src_lo & 1) == 0 && src_lo + 1 == src_hi) &&
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(dst_lo & 1) == 0 && dst_lo + 1 == dst_hi) {
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// 64 bit
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if (cbuf) {
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MacroAssembler _masm(cbuf);
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__ str(as_Register(Matcher::_regEncode[src_lo]),
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Address(sp, dst_offset));
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} else if (st) {
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st->print("str %s, [sp, #%d]\t# spill",
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Matcher::regName[src_lo],
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dst_offset);
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}
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} else {
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// 32 bit
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if (cbuf) {
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MacroAssembler _masm(cbuf);
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__ strw(as_Register(Matcher::_regEncode[src_lo]),
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Address(sp, dst_offset));
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} else if (st) {
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st->print("strw %s, [sp, #%d]\t# spill",
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Matcher::regName[src_lo],
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dst_offset);
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}
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}
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}
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return 4;
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case rc_float:
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if (dst_lo_rc == rc_int) { // fpr --> gpr copy
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if (((src_lo & 1) == 0 && src_lo + 1 == src_hi) &&
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(dst_lo & 1) == 0 && dst_lo + 1 == dst_hi) {
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// 64 bit
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if (cbuf) {
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MacroAssembler _masm(cbuf);
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__ fmovd(as_Register(Matcher::_regEncode[dst_lo]),
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as_FloatRegister(Matcher::_regEncode[src_lo]));
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} else if (st) {
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st->print("fmovd %s, %s\t# shuffle",
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Matcher::regName[dst_lo],
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Matcher::regName[src_lo]);
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}
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} else {
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// 32 bit
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if (cbuf) {
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MacroAssembler _masm(cbuf);
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__ fmovs(as_Register(Matcher::_regEncode[dst_lo]),
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as_FloatRegister(Matcher::_regEncode[src_lo]));
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} else if (st) {
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st->print("fmovs %s, %s\t# shuffle",
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Matcher::regName[dst_lo],
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Matcher::regName[src_lo]);
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}
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}
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} else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
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if (((src_lo & 1) == 0 && src_lo + 1 == src_hi) &&
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(dst_lo & 1) == 0 && dst_lo + 1 == dst_hi) {
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// 64 bit
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if (cbuf) {
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MacroAssembler _masm(cbuf);
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__ fmovd(as_FloatRegister(Matcher::_regEncode[dst_lo]),
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as_FloatRegister(Matcher::_regEncode[src_lo]));
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} else if (st) {
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st->print("fmovd %s, %s\t# shuffle",
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Matcher::regName[dst_lo],
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Matcher::regName[src_lo]);
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}
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} else {
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// 32 bit
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if (cbuf) {
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MacroAssembler _masm(cbuf);
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__ fmovs(as_FloatRegister(Matcher::_regEncode[dst_lo]),
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as_FloatRegister(Matcher::_regEncode[src_lo]));
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} else if (st) {
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st->print("fmovs %s, %s\t# shuffle",
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Matcher::regName[dst_lo],
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Matcher::regName[src_lo]);
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}
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}
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} else { // fpr --> stack spill
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assert(dst_lo_rc == rc_stack, "spill to bad register class");
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int dst_offset = ra_->reg2offset(dst_lo);
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if (((src_lo & 1) == 0 && src_lo + 1 == src_hi) &&
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(dst_lo & 1) == 0 && dst_lo + 1 == dst_hi) {
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// 64 bit
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if (cbuf) {
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MacroAssembler _masm(cbuf);
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__ strd(as_FloatRegister(Matcher::_regEncode[src_lo]),
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Address(sp, dst_offset));
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} else if (st) {
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st->print("strd %s, [sp, #%d]\t# spill",
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Matcher::regName[src_lo],
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dst_offset);
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}
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} else {
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// 32 bit
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if (cbuf) {
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MacroAssembler _masm(cbuf);
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__ strs(as_FloatRegister(Matcher::_regEncode[src_lo]),
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Address(sp, dst_offset));
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} else if (st) {
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st->print("strs %s, [sp, #%d]\t# spill",
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Matcher::regName[src_lo],
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dst_offset);
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}
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}
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}
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return 4;
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case rc_stack:
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int src_offset = ra_->reg2offset(src_lo);
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if (dst_lo_rc == rc_int) { // stack --> gpr load
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if (((src_lo & 1) == 0 && src_lo + 1 == src_hi) &&
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(dst_lo & 1) == 0 && dst_lo + 1 == dst_hi) {
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// 64 bit
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if (cbuf) {
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MacroAssembler _masm(cbuf);
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__ ldr(as_Register(Matcher::_regEncode[dst_lo]),
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Address(sp, src_offset));
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} else if (st) {
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st->print("ldr %s, [sp, %d]\t# restore",
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Matcher::regName[dst_lo],
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src_offset);
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}
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} else {
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// 32 bit
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if (cbuf) {
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MacroAssembler _masm(cbuf);
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__ ldrw(as_Register(Matcher::_regEncode[dst_lo]),
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Address(sp, src_offset));
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} else if (st) {
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st->print("ldr %s, [sp, %d]\t# restore",
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Matcher::regName[dst_lo],
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src_offset);
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}
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}
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return 4;
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} else if (dst_lo_rc == rc_float) { // stack --> fpr load
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if (((src_lo & 1) == 0 && src_lo + 1 == src_hi) &&
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(dst_lo & 1) == 0 && dst_lo + 1 == dst_hi) {
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// 64 bit
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if (cbuf) {
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MacroAssembler _masm(cbuf);
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__ ldrd(as_FloatRegister(Matcher::_regEncode[dst_lo]),
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Address(sp, src_offset));
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} else if (st) {
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st->print("ldrd %s, [sp, %d]\t# restore",
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Matcher::regName[dst_lo],
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src_offset);
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}
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} else {
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// 32 bit
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if (cbuf) {
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MacroAssembler _masm(cbuf);
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__ ldrs(as_FloatRegister(Matcher::_regEncode[dst_lo]),
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Address(sp, src_offset));
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} else if (st) {
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st->print("ldrs %s, [sp, %d]\t# restore",
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Matcher::regName[dst_lo],
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src_offset);
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}
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}
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return 4;
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} else { // stack --> stack copy
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assert(dst_lo_rc == rc_stack, "spill to bad register class");
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int dst_offset = ra_->reg2offset(dst_lo);
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if (((src_lo & 1) == 0 && src_lo + 1 == src_hi) &&
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(dst_lo & 1) == 0 && dst_lo + 1 == dst_hi) {
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// 64 bit
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if (cbuf) {
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MacroAssembler _masm(cbuf);
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__ ldr(rscratch1, Address(sp, src_offset));
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__ str(rscratch1, Address(sp, dst_offset));
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} else if (st) {
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st->print("ldr rscratch1, [sp, %d]\t# mem-mem spill",
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src_offset);
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st->print("\n\t");
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st->print("str rscratch1, [sp, %d]",
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dst_offset);
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}
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} else {
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// 32 bit
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if (cbuf) {
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MacroAssembler _masm(cbuf);
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__ ldrw(rscratch1, Address(sp, src_offset));
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__ strw(rscratch1, Address(sp, dst_offset));
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} else if (st) {
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st->print("ldrw rscratch1, [sp, %d]\t# mem-mem spill",
|
||||
src_offset);
|
||||
st->print("\n\t");
|
||||
st->print("strw rscratch1, [sp, %d]",
|
||||
dst_offset);
|
||||
}
|
||||
}
|
||||
return 8;
|
||||
break;
|
||||
default:
|
||||
assert(false, "bad rc_class for spill");
|
||||
ShouldNotReachHere();
|
||||
}
|
||||
}
|
||||
|
||||
if (st) {
|
||||
st->print("spill ");
|
||||
if (src_lo_rc == rc_stack) {
|
||||
st->print("[sp, #%d] -> ", ra_->reg2offset(src_lo));
|
||||
} else {
|
||||
st->print("%s -> ", Matcher::regName[src_lo]);
|
||||
}
|
||||
if (dst_lo_rc == rc_stack) {
|
||||
st->print("[sp, #%d]", ra_->reg2offset(dst_lo));
|
||||
} else {
|
||||
st->print("%s", Matcher::regName[dst_lo]);
|
||||
}
|
||||
if (bottom_type()->isa_vect() != NULL) {
|
||||
st->print("\t# vector spill size = %d", ideal_reg()==Op_VecD ? 64:128);
|
||||
} else {
|
||||
st->print("\t# spill size = %d", is64 ? 64:32);
|
||||
}
|
||||
}
|
||||
|
||||
assert(false," bad rc_class for spill ");
|
||||
Unimplemented();
|
||||
return 0;
|
||||
|
||||
}
|
||||
@ -2522,7 +2307,7 @@ void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
|
||||
}
|
||||
|
||||
uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
|
||||
return implementation(NULL, ra_, true, NULL);
|
||||
return MachNode::size(ra_);
|
||||
}
|
||||
|
||||
//=============================================================================
|
||||
|
||||
@ -2306,6 +2306,28 @@ Address MacroAssembler::offsetted_address(Register r, Register r1,
|
||||
}
|
||||
}
|
||||
|
||||
Address MacroAssembler::spill_address(int size, int offset, Register tmp)
|
||||
{
|
||||
assert(offset >= 0, "spill to negative address?");
|
||||
// Offset reachable ?
|
||||
// Not aligned - 9 bits signed offset
|
||||
// Aligned - 12 bits unsigned offset shifted
|
||||
Register base = sp;
|
||||
if ((offset & (size-1)) && offset >= (1<<8)) {
|
||||
add(tmp, base, offset & ((1<<12)-1));
|
||||
base = tmp;
|
||||
offset &= -1<<12;
|
||||
}
|
||||
|
||||
if (offset >= (1<<12) * size) {
|
||||
add(tmp, base, offset & (((1<<12)-1)<<12));
|
||||
base = tmp;
|
||||
offset &= ~(((1<<12)-1)<<12);
|
||||
}
|
||||
|
||||
return Address(base, offset);
|
||||
}
|
||||
|
||||
/**
|
||||
* Multiply 64 bit by 64 bit first loop.
|
||||
*/
|
||||
|
||||
@ -468,6 +468,10 @@ public:
|
||||
|
||||
void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
|
||||
|
||||
void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
|
||||
orr(Vd, T, Vn, Vn);
|
||||
}
|
||||
|
||||
// macro instructions for accessing and updating floating point
|
||||
// status register
|
||||
//
|
||||
@ -1161,6 +1165,46 @@ private:
|
||||
// Uses rscratch2.
|
||||
Address offsetted_address(Register r, Register r1, Address::extend ext,
|
||||
int offset, int size);
|
||||
|
||||
private:
|
||||
// Returns an address on the stack which is reachable with a ldr/str of size
|
||||
// Uses rscratch2 if the address is not directly reachable
|
||||
Address spill_address(int size, int offset, Register tmp=rscratch2);
|
||||
|
||||
public:
|
||||
void spill(Register Rx, bool is64, int offset) {
|
||||
if (is64) {
|
||||
str(Rx, spill_address(8, offset));
|
||||
} else {
|
||||
strw(Rx, spill_address(4, offset));
|
||||
}
|
||||
}
|
||||
void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
|
||||
str(Vx, T, spill_address(1 << (int)T, offset));
|
||||
}
|
||||
void unspill(Register Rx, bool is64, int offset) {
|
||||
if (is64) {
|
||||
ldr(Rx, spill_address(8, offset));
|
||||
} else {
|
||||
ldrw(Rx, spill_address(4, offset));
|
||||
}
|
||||
}
|
||||
void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
|
||||
ldr(Vx, T, spill_address(1 << (int)T, offset));
|
||||
}
|
||||
void spill_copy128(int src_offset, int dst_offset,
|
||||
Register tmp1=rscratch1, Register tmp2=rscratch2) {
|
||||
if (src_offset < 512 && (src_offset & 7) == 0 &&
|
||||
dst_offset < 512 && (dst_offset & 7) == 0) {
|
||||
ldp(tmp1, tmp2, Address(sp, src_offset));
|
||||
stp(tmp1, tmp2, Address(sp, dst_offset));
|
||||
} else {
|
||||
unspill(tmp1, true, src_offset);
|
||||
spill(tmp1, true, dst_offset);
|
||||
unspill(tmp1, true, src_offset+8);
|
||||
spill(tmp1, true, dst_offset+8);
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
#ifdef ASSERT
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user