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8285923: [REDO] JDK-8285802 AArch64: Consistently handle offsets in MacroAssembler as 64-bit quantities

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Reviewed-by: ngasson, kvn
This commit is contained in:
Andrew Haley 2022-05-09 13:37:15 +00:00
parent f143386109
commit b849efdf15
3 changed files with 29 additions and 25 deletions
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22
src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp
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@ -2251,11 +2251,13 @@ void MacroAssembler::_assert_asm(Assembler::Condition cc, const char* msg) {
// If a constant does not fit in an immediate field, generate some
// number of MOV instructions and then perform the operation.
void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
add_sub_imm_insn insn1,
add_sub_reg_insn insn2) {
add_sub_reg_insn insn2,
bool is32) {
assert(Rd != zr, "Rd = zr and not setting flags?");
if (operand_valid_for_add_sub_immediate((int)imm)) {
bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
if (fits) {
(this->*insn1)(Rd, Rn, imm);
} else {
if (uabs(imm) < (1 << 24)) {
@ -2263,7 +2265,7 @@ void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned im
(this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
} else {
assert_different_registers(Rd, Rn);
mov(Rd, (uint64_t)imm);
mov(Rd, imm);
(this->*insn2)(Rd, Rn, Rd, LSL, 0);
}
}
@ -2271,15 +2273,17 @@ void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned im
// Separate vsn which sets the flags. Optimisations are more restricted
// because we must set the flags correctly.
void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
add_sub_imm_insn insn1,
add_sub_reg_insn insn2) {
if (operand_valid_for_add_sub_immediate((int)imm)) {
void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
add_sub_imm_insn insn1,
add_sub_reg_insn insn2,
bool is32) {
bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
if (fits) {
(this->*insn1)(Rd, Rn, imm);
} else {
assert_different_registers(Rd, Rn);
assert(Rd != zr, "overflow in immediate operand");
mov(Rd, (uint64_t)imm);
mov(Rd, imm);
(this->*insn2)(Rd, Rn, Rd, LSL, 0);
}
}

30
src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp
View File

@ -212,7 +212,7 @@ class MacroAssembler: public Assembler {
inline void movw(Register Rd, Register Rn) {
if (Rd == sp || Rn == sp) {
addw(Rd, Rn, 0U);
Assembler::addw(Rd, Rn, 0U);
} else {
orrw(Rd, zr, Rn);
}
@ -221,7 +221,7 @@ class MacroAssembler: public Assembler {
assert(Rd != r31_sp && Rn != r31_sp, "should be");
if (Rd == Rn) {
} else if (Rd == sp || Rn == sp) {
add(Rd, Rn, 0U);
Assembler::add(Rd, Rn, 0U);
} else {
orr(Rd, zr, Rn);
}
@ -1169,17 +1169,17 @@ public:
// If a constant does not fit in an immediate field, generate some
// number of MOV instructions and then perform the operation
void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
add_sub_imm_insn insn1,
add_sub_reg_insn insn2);
add_sub_reg_insn insn2, bool is32);
// Separate vsn which sets the flags
void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
add_sub_imm_insn insn1,
add_sub_reg_insn insn2);
void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
add_sub_imm_insn insn1,
add_sub_reg_insn insn2, bool is32);
#define WRAP(INSN) \
void INSN(Register Rd, Register Rn, unsigned imm) { \
wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
#define WRAP(INSN, is32) \
void INSN(Register Rd, Register Rn, uint64_t imm) { \
wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
} \
\
void INSN(Register Rd, Register Rn, Register Rm, \
@ -1196,12 +1196,12 @@ public:
Assembler::INSN(Rd, Rn, Rm, option, amount); \
}
WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
#undef WRAP
#define WRAP(INSN) \
void INSN(Register Rd, Register Rn, unsigned imm) { \
wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
#define WRAP(INSN, is32) \
void INSN(Register Rd, Register Rn, uint64_t imm) { \
wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
} \
\
void INSN(Register Rd, Register Rn, Register Rm, \
@ -1218,7 +1218,7 @@ public:
Assembler::INSN(Rd, Rn, Rm, option, amount); \
}
WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
void add(Register Rd, Register Rn, RegisterOrConstant increment);
void addw(Register Rd, Register Rn, RegisterOrConstant increment);

2
src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp
View File

@ -6806,7 +6806,7 @@ class StubGenerator: public StubCodeGenerator {
assert(is_even(framesize/2), "sp not 16-byte aligned");
// lr and fp are already in place
__ sub(sp, rfp, ((unsigned)framesize-4) << LogBytesPerInt); // prolog
__ sub(sp, rfp, ((uint64_t)framesize-4) << LogBytesPerInt); // prolog
int frame_complete = __ pc() - start;