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8253284: Zero OrderAccess barrier mappings are incorrect

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Reviewed-by: dholmes, aph, andrew
This commit is contained in:
Aleksey Shipilev 2020-09-22 08:33:42 +00:00
parent 284bbf02dd
commit b9729cb432
2 changed files with 26 additions and 26 deletions
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24
src/hotspot/os_cpu/bsd_zero/orderAccess_bsd_zero.hpp
View File

@ -28,7 +28,7 @@
// Included in orderAccess.hpp header file.
#ifdef ARM
#if defined(ARM) // ----------------------------------------------------
/*
* ARM Kernel helper for memory barrier.
@ -39,14 +39,10 @@
typedef void (__kernel_dmb_t) (void);
#define __kernel_dmb (*(__kernel_dmb_t *) 0xffff0fa0)
#define FULL_MEM_BARRIER __kernel_dmb()
#define LIGHT_MEM_BARRIER __kernel_dmb()
#define FULL_MEM_BARRIER __kernel_dmb()
#else // ARM
#define FULL_MEM_BARRIER __sync_synchronize()
#ifdef PPC
#elif defined(PPC) // ----------------------------------------------------
#ifdef __NO_LWSYNC__
#define LIGHT_MEM_BARRIER __asm __volatile ("sync":::"memory")
@ -54,13 +50,21 @@ typedef void (__kernel_dmb_t) (void);
#define LIGHT_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
#endif
#else // PPC
#define FULL_MEM_BARRIER __sync_synchronize()
#elif defined(X86) // ----------------------------------------------------
#define LIGHT_MEM_BARRIER __asm __volatile ("":::"memory")
#define FULL_MEM_BARRIER __sync_synchronize()
#endif // PPC
#else // ----------------------------------------------------
#endif // ARM
// Default to strongest barriers for correctness.
#define LIGHT_MEM_BARRIER __sync_synchronize()
#define FULL_MEM_BARRIER __sync_synchronize()
#endif // ----------------------------------------------------
// Note: What is meant by LIGHT_MEM_BARRIER is a barrier which is sufficient
// to provide TSO semantics, i.e. StoreStore | LoadLoad | LoadStore.

28
src/hotspot/os_cpu/linux_zero/orderAccess_linux_zero.hpp
View File

@ -28,7 +28,7 @@
// Included in orderAccess.hpp header file.
#ifdef ARM
#if defined(ARM) // ----------------------------------------------------
/*
* ARM Kernel helper for memory barrier.
@ -39,14 +39,10 @@
typedef void (__kernel_dmb_t) (void);
#define __kernel_dmb (*(__kernel_dmb_t *) 0xffff0fa0)
#define FULL_MEM_BARRIER __kernel_dmb()
#define LIGHT_MEM_BARRIER __kernel_dmb()
#define FULL_MEM_BARRIER __kernel_dmb()
#else // ARM
#define FULL_MEM_BARRIER __sync_synchronize()
#ifdef PPC
#elif defined(PPC) // ----------------------------------------------------
#ifdef __NO_LWSYNC__
#define LIGHT_MEM_BARRIER __asm __volatile ("sync":::"memory")
@ -54,21 +50,21 @@ typedef void (__kernel_dmb_t) (void);
#define LIGHT_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
#endif
#else // PPC
#define FULL_MEM_BARRIER __sync_synchronize()
#ifdef ALPHA
#define LIGHT_MEM_BARRIER __sync_synchronize()
#else // ALPHA
#elif defined(X86) // ----------------------------------------------------
#define LIGHT_MEM_BARRIER __asm __volatile ("":::"memory")
#define FULL_MEM_BARRIER __sync_synchronize()
#endif // ALPHA
#else // ----------------------------------------------------
#endif // PPC
// Default to strongest barriers for correctness.
#endif // ARM
#define LIGHT_MEM_BARRIER __sync_synchronize()
#define FULL_MEM_BARRIER __sync_synchronize()
#endif // ----------------------------------------------------
// Note: What is meant by LIGHT_MEM_BARRIER is a barrier which is sufficient
// to provide TSO semantics, i.e. StoreStore | LoadLoad | LoadStore.