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8305524: AArch64: Fix arraycopy issue on SVE caused by matching rule vmask_gen_sub

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Reviewed-by: aph, xgong
This commit is contained in:
Pengfei Li 2023-04-12 03:15:39 +00:00
parent 82e8b0332b
commit b9bdbe9ab3
4 changed files with 62 additions and 10 deletions
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8
src/hotspot/cpu/aarch64/aarch64_vector.ad
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@ -5726,7 +5726,7 @@ instruct vmask_gen_I(pReg pd, iRegIorL2I src, rFlagsReg cr) %{
format %{ "vmask_gen_I $pd, $src\t# KILL cr" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
__ sve_whilelow($pd$$PRegister, __ elemType_to_regVariant(bt), zr, $src$$Register);
__ sve_whileltw($pd$$PRegister, __ elemType_to_regVariant(bt), zr, $src$$Register);
%}
ins_pipe(pipe_class_default);
%}
@ -5738,7 +5738,7 @@ instruct vmask_gen_L(pReg pd, iRegL src, rFlagsReg cr) %{
format %{ "vmask_gen_L $pd, $src\t# KILL cr" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
__ sve_whilelo($pd$$PRegister, __ elemType_to_regVariant(bt), zr, $src$$Register);
__ sve_whilelt($pd$$PRegister, __ elemType_to_regVariant(bt), zr, $src$$Register);
%}
ins_pipe(pipe_slow);
%}
@ -5762,7 +5762,7 @@ instruct vmask_gen_sub(pReg pd, iRegL src1, iRegL src2, rFlagsReg cr) %{
format %{ "vmask_gen_sub $pd, $src2, $src1\t# KILL cr" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
__ sve_whilelo($pd$$PRegister, __ elemType_to_regVariant(bt), $src2$$Register, $src1$$Register);
__ sve_whilelt($pd$$PRegister, __ elemType_to_regVariant(bt), $src2$$Register, $src1$$Register);
%}
ins_pipe(pipe_slow);
%}
@ -6521,7 +6521,7 @@ instruct mcompress(pReg dst, pReg pg, rFlagsReg cr) %{
BasicType bt = Matcher::vector_element_basic_type(this);
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
__ sve_cntp(rscratch1, size, ptrue, $pg$$PRegister);
__ sve_whilelo(as_PRegister($dst$$reg), size, zr, rscratch1);
__ sve_whilelt(as_PRegister($dst$$reg), size, zr, rscratch1);
%}
ins_pipe(pipe_slow);
%}

8
src/hotspot/cpu/aarch64/aarch64_vector_ad.m4
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@ -4090,7 +4090,7 @@ instruct vmask_gen_I(pReg pd, iRegIorL2I src, rFlagsReg cr) %{
format %{ "vmask_gen_I $pd, $src\t# KILL cr" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
__ sve_whilelow($pd$$PRegister, __ elemType_to_regVariant(bt), zr, $src$$Register);
__ sve_whileltw($pd$$PRegister, __ elemType_to_regVariant(bt), zr, $src$$Register);
%}
ins_pipe(pipe_class_default);
%}
@ -4102,7 +4102,7 @@ instruct vmask_gen_L(pReg pd, iRegL src, rFlagsReg cr) %{
format %{ "vmask_gen_L $pd, $src\t# KILL cr" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
__ sve_whilelo($pd$$PRegister, __ elemType_to_regVariant(bt), zr, $src$$Register);
__ sve_whilelt($pd$$PRegister, __ elemType_to_regVariant(bt), zr, $src$$Register);
%}
ins_pipe(pipe_slow);
%}
@ -4126,7 +4126,7 @@ instruct vmask_gen_sub(pReg pd, iRegL src1, iRegL src2, rFlagsReg cr) %{
format %{ "vmask_gen_sub $pd, $src2, $src1\t# KILL cr" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
__ sve_whilelo($pd$$PRegister, __ elemType_to_regVariant(bt), $src2$$Register, $src1$$Register);
__ sve_whilelt($pd$$PRegister, __ elemType_to_regVariant(bt), $src2$$Register, $src1$$Register);
%}
ins_pipe(pipe_slow);
%}
@ -4852,7 +4852,7 @@ instruct mcompress(pReg dst, pReg pg, rFlagsReg cr) %{
BasicType bt = Matcher::vector_element_basic_type(this);
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
__ sve_cntp(rscratch1, size, ptrue, $pg$$PRegister);
__ sve_whilelo(as_PRegister($dst$$reg), size, zr, rscratch1);
__ sve_whilelt(as_PRegister($dst$$reg), size, zr, rscratch1);
%}
ins_pipe(pipe_slow);
%}

4
src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp
View File

@ -1763,9 +1763,9 @@ void C2_MacroAssembler::sve_gen_mask_imm(PRegister dst, BasicType bt, uint32_t l
} else if (lane_cnt == max_vector_length - (max_vector_length % 3)) {
sve_ptrue(dst, size, /* MUL3 */ 0b11110);
} else {
// Encode to "whilelow" for the remaining cases.
// Encode to "whileltw" for the remaining cases.
mov(rscratch1, lane_cnt);
sve_whilelow(dst, size, zr, rscratch1);
sve_whileltw(dst, size, zr, rscratch1);
}
}

52
test/hotspot/jtreg/compiler/arraycopy/TestArrayCopyMaskedWithSub.java Normal file
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@ -0,0 +1,52 @@
/*
* Copyright (c) 2023, Arm Limited. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*/
/*
* @test
* @bug 8305524
* @run main/othervm -Xbatch compiler.arraycopy.TestArrayCopyMaskedWithSub
*/
package compiler.arraycopy;
public class TestArrayCopyMaskedWithSub {
private static char[] src = {'A', 'A', 'A', 'A', 'A'};
private static char[] dst = {'B', 'B', 'B', 'B', 'B'};
private static void copy(int nlen) {
System.arraycopy(src, 0, dst, 0, -nlen);
}
public static void main(String[] args) {
for (int i = 0; i < 25000; i++) {
copy(0);
}
copy(-5);
for (char c : dst) {
if (c != 'A') {
throw new RuntimeException("Wrong value!");
}
}
System.out.println("PASS");
}
}