8324123: aarch64: fix prfm literal encoding in assembler
Reviewed-by: aph, dlong
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parent
b5995a76f7
commit
bde87895c8
src/hotspot/cpu/aarch64
@ -187,6 +187,26 @@ void Address::lea(MacroAssembler *as, Register r) const {
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zrf(Rd, 0);
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}
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// This encoding is similar (but not quite identical) to the encoding used
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// by literal ld/st. see JDK-8324123.
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// PRFM does not support writeback or pre/post index.
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void Assembler::prfm(const Address &adr, prfop pfop) {
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Address::mode mode = adr.getMode();
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// PRFM does not support pre/post index
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guarantee((mode != Address::pre) && (mode != Address::post), "prfm does not support pre/post indexing");
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if (mode == Address::literal) {
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starti;
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f(0b11, 31, 30), f(0b011, 29, 27), f(0b000, 26, 24);
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f(pfop, 4, 0);
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int64_t offset = (adr.target() - pc()) >> 2;
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sf(offset, 23, 5);
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} else {
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assert((mode == Address::base_plus_offset)
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|| (mode == Address::base_plus_offset_reg), "must be base_plus_offset/base_plus_offset_reg");
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ld_st2(as_Register(pfop), adr, 0b11, 0b10);
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}
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}
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// An "all-purpose" add/subtract immediate, per ARM documentation:
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// A "programmer-friendly" assembler may accept a negative immediate
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// between -(2^24 -1) and -1 inclusive, causing it to convert a
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@ -797,6 +797,8 @@ public:
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void adrp(Register Rd, const Address &dest, uint64_t &offset) = delete;
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void prfm(const Address &adr, prfop pfop = PLDL1KEEP);
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#undef INSN
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void add_sub_immediate(Instruction_aarch64 ¤t_insn, Register Rd, Register Rn,
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@ -1574,17 +1576,6 @@ public:
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#undef INSN
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#define INSN(NAME, size, op) \
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void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \
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ld_st2(as_Register(pfop), adr, size, op); \
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}
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INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with
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// writeback modes, but the assembler
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// doesn't enfore that.
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#undef INSN
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#define INSN(NAME, size, op) \
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void NAME(FloatRegister Rt, const Address &adr) { \
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ld_st2(as_Register(Rt), adr, size, op, 1); \
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