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8327058: RISC-V: make Zcb experimental

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Reviewed-by: fyang, gli
This commit is contained in:
Hamlin Li 2024-03-01 13:33:01 +00:00
parent b972997af7
commit c02e7f4bb5
3 changed files with 3 additions and 2 deletions

2
src/hotspot/cpu/riscv/assembler_riscv.hpp

@ -2656,7 +2656,7 @@ public:
}
bool do_compress_zcb(Register reg1 = noreg, Register reg2 = noreg) const {
return do_compress() && VM_Version::ext_Zcb.enabled() &&
return do_compress() && UseZcb &&
(reg1 == noreg || reg1->is_compressed_valid()) && (reg2 == noreg || reg2->is_compressed_valid());
}

1
src/hotspot/cpu/riscv/globals_riscv.hpp

@ -107,6 +107,7 @@ define_pd_global(intx, InlineSmallCode, 1000);
product(bool, UseZbs, false, "Use Zbs instructions") \
product(bool, UseZfh, false, "Use Zfh instructions") \
product(bool, UseZacas, false, EXPERIMENTAL, "Use Zacas instructions") \
product(bool, UseZcb, false, EXPERIMENTAL, "Use Zcb instructions") \
product(bool, UseZic64b, false, EXPERIMENTAL, "Use Zic64b instructions") \
product(bool, UseZicbom, false, EXPERIMENTAL, "Use Zicbom instructions") \
product(bool, UseZicbop, false, EXPERIMENTAL, "Use Zicbop instructions") \

2
src/hotspot/cpu/riscv/vm_version_riscv.hpp

@ -144,7 +144,7 @@ class VM_Version : public Abstract_VM_Version {
decl(ext_Zbb , "Zbb" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZbb)) \
decl(ext_Zbc , "Zbc" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
decl(ext_Zbs , "Zbs" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZbs)) \
decl(ext_Zcb , "Zcb" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
decl(ext_Zcb , "Zcb" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZcb)) \
decl(ext_Zfh , "Zfh" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZfh)) \
decl(ext_Zicsr , "Zicsr" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
decl(ext_Zifencei , "Zifencei" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \