8341068: [s390x] intrinsics for divideUnsigned and remainderUnsigned methods in java.lang.Integer and java.lang.Long
Reviewed-by: lucy, aph
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parent
37a3398b58
commit
c125178065
src/hotspot/cpu/s390
@ -795,8 +795,8 @@ class Assembler : public AbstractAssembler {
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#define DSGF_ZOPC (unsigned long)(227L << 40 | 29L)
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#define DSG_ZOPC (unsigned long)(227L << 40 | 13L)
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// RR, unsigned
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#define DLR_ZOPC (unsigned int)(185 << 24 | 151 << 16)
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#define DLGR_ZOPC (unsigned int)(185 << 24 | 135 << 16)
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#define DLR_ZOPC (unsigned int)(0xb997 << 16)
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#define DLGR_ZOPC (unsigned int)(0xb987 << 16)
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// RM, unsigned
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#define DL_ZOPC (unsigned long)(227L << 40 | 151L)
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#define DLG_ZOPC (unsigned long)(227L << 40 | 135L)
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@ -2257,6 +2257,8 @@ class Assembler : public AbstractAssembler {
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inline void z_mghi( Register r1, int64_t i2); // mult r1 = r1 * i2_imm16; int64
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// Division instructions
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inline void z_dlr( Register r1, Register r2); // div r1 = r1 / r2 ; int64/int32 needs reg pair!
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inline void z_dlgr( Register r1, Register r2); // div r1 = r1 / r2 ; int128/int64 needs reg pair!
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inline void z_dsgr( Register r1, Register r2); // div r1 = r1 / r2 ; int64/int32 needs reg pair!
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inline void z_dsgfr(Register r1, Register r2); // div r1 = r1 / r2 ; int64/int32 needs reg pair!
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@ -624,6 +624,8 @@ inline void Assembler::z_mghi( Register r1, int64_t i2) { emit_32( MGHI_ZOPC |
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//------------------
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// DIVIDE
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//------------------
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inline void Assembler::z_dlr( Register r1, Register r2) { emit_32( DLR_ZOPC | regt(r1, 24, 32) | reg(r2, 28, 32)); }
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inline void Assembler::z_dlgr( Register r1, Register r2) { emit_32( DLGR_ZOPC | regt(r1, 24, 32) | reg(r2, 28, 32)); }
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inline void Assembler::z_dsgr( Register r1, Register r2) { emit_32( DSGR_ZOPC | regt(r1, 24, 32) | reg(r2, 28, 32)); }
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inline void Assembler::z_dsgfr(Register r1, Register r2) { emit_32( DSGFR_ZOPC | regt(r1, 24, 32) | reg(r2, 28, 32)); }
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@ -6249,6 +6249,29 @@ instruct divI_reg_imm16(roddRegI dst, iRegI src1, immI16 src2, revenRegI tmp, fl
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ins_pipe(pipe_class_dummy);
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%}
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// Unsigned Integer Register Division
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// NOTE: z_dlr requires even-odd pair. remainder will be in even register(r4) & quotient will be stored in odd register(r5)
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// for dividend, upper 32bits will be in r4 and lower 32bits will be in r5 register.
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instruct udivI_reg_reg(roddRegI r5_rodd_dst, iRegI src2, revenRegI r4_reven_tmp, flagsReg cr) %{
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match(Set r5_rodd_dst (UDivI r5_rodd_dst src2));
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effect(TEMP r4_reven_tmp, KILL cr);
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// TODO: size(4);
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format %{ "UDIV $r5_rodd_dst,$r5_rodd_dst,$src2" %}
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ins_encode %{
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Register b = $src2$$Register;
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Register r4_reven_tmp = $r4_reven_tmp$$Register;
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Register r5_rodd_dst = $r5_rodd_dst$$Register;
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assert_different_registers(r4_reven_tmp, r5_rodd_dst, b);
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assert(r4_reven_tmp->successor() == r5_rodd_dst, "even-odd pair required for the instruction");
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__ block_comment("unsigned_div_int {");
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__ z_lhi(r4_reven_tmp, 0); // make upper 32bits 0
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__ z_dlr(r4_reven_tmp, b);
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__ block_comment("} unsigned_div_int");
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%}
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ins_pipe(pipe_class_dummy);
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%}
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// Long DIVMOD with Register, both quotient and mod results
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instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flagsReg cr) %{
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match(DivModL dst1src1 src2);
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@ -6305,6 +6328,28 @@ instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{
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ins_pipe(pipe_class_dummy);
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%}
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// Register Unsigned Long Division
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// NOTE: z_dlgr requires even-odd pair. remainder will be in even register(r4) & quotient will be stored in odd register(r5)
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// for dividend, upper 64bits will be in r4 and lower 64bits will be in r5 register.
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instruct udivL_reg_reg(roddRegL r5_rodd_dst, iRegL src, revenRegL r4_reven_tmp, flagsReg cr) %{
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match(Set r5_rodd_dst (UDivL r5_rodd_dst src));
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effect(TEMP r4_reven_tmp, KILL cr);
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ins_cost(DEFAULT_COST);
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// TODO: size(4);
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format %{ "UDIVG $r5_rodd_dst,$r5_rodd_dst,$src" %}
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ins_encode %{
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Register b = $src$$Register;
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Register r5_rodd_dst = $r5_rodd_dst$$Register;
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Register r4_reven_tmp = $r4_reven_tmp$$Register;
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assert_different_registers(r5_rodd_dst, r4_reven_tmp, b);
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__ block_comment("unsigned_div_long {");
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__ z_lghi(r4_reven_tmp, 0); // make upper 64bits 0
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__ z_dlgr(r4_reven_tmp, b);
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__ block_comment("} unsigned_div_long");
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%}
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ins_pipe(pipe_class_dummy);
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%}
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// Immediate Long Division
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instruct divL_reg_imm16(roddRegL dst, iRegL src1, immL16 src2, revenRegL tmp, flagsReg cr) %{
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match(Set dst (DivL src1 src2));
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@ -6370,6 +6415,31 @@ instruct modI_reg_reg(revenRegI dst, iRegI src1, noOdd_iRegI src2, roddRegI tmp,
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ins_pipe(pipe_class_dummy);
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%}
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// Register Unsigned Integer Remainder
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// NOTE: z_dlr requires even-odd pair. remainder will be in even register(r4) & quotient will be stored in odd register(r5)
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// for dividend, upper 32bits will be in r4 and lower 32bits will be in r5 register.
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instruct umodI_reg_reg(revenRegI r4_reven_dst, iRegI src2, roddRegI r5_rodd_tmp, flagsReg cr) %{
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match(Set r4_reven_dst (UModI r4_reven_dst src2));
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effect(TEMP r5_rodd_tmp, KILL cr);
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ins_cost(DEFAULT_COST);
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// TODO: s390 port size(VARIABLE_SIZE);
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format %{ "UMOD $r4_reven_dst,$r4_reven_dst,$src2" %}
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ins_encode %{
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Register b = $src2$$Register;
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Register r4_reven_dst = $r4_reven_dst$$Register;
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Register r5_rodd_tmp = $r5_rodd_tmp$$Register;
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assert_different_registers(r4_reven_dst, r5_rodd_tmp, b);
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assert(r4_reven_dst->successor() == r5_rodd_tmp, "must be an even-odd pair");
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__ block_comment("unsigned_mod_integer {");
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__ z_lr(r5_rodd_tmp, r4_reven_dst); // load lower 32bits in odd register
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__ z_lhi(r4_reven_dst, 0); // make upper 32bits 0
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__ z_dlr(r4_reven_dst, b);
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__ block_comment("} unsigned_mod_integer");
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%}
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ins_pipe(pipe_class_dummy);
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%}
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// Immediate Remainder
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instruct modI_reg_imm16(revenRegI dst, iRegI src1, immI16 src2, roddRegI tmp, flagsReg cr) %{
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match(Set dst (ModI src1 src2));
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@ -6433,6 +6503,31 @@ instruct modL_reg_reg(revenRegL dst, roddRegL src1, iRegL src2, flagsReg cr) %{
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ins_pipe(pipe_class_dummy);
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%}
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// Register Unsigned Long Remainder
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// NOTE: z_dlgr requires even-odd pair. remainder will be in even register(r4) & quotient will be stored in odd register(r5)
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// for dividend, upper 64bits will be in r4 and lower 64bits will be in r5 register.
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instruct umodL_reg_reg(revenRegL r4_reven_dst, roddRegL r5_rodd_tmp, iRegL src2, flagsReg cr) %{
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match(Set r4_reven_dst (UModL r4_reven_dst src2));
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effect(TEMP r5_rodd_tmp, KILL cr);
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ins_cost(DEFAULT_COST);
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// TODO: s390 port size(VARIABLE_SIZE);
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format %{ "UMODG $r4_reven_dst,$r4_reven_dst,$src2" %}
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ins_encode %{
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Register b = $src2$$Register;
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Register r4_reven_dst = $r4_reven_dst$$Register;
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Register r5_rodd_tmp = $r5_rodd_tmp$$Register;
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assert_different_registers(r4_reven_dst, r5_rodd_tmp, b);
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assert(r4_reven_dst->successor() == r5_rodd_tmp, "instruction requires an even-odd pair" );
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__ block_comment("unsigned_mod_long {");
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__ z_lgr(r5_rodd_tmp, r4_reven_dst); // load lower 64bits in even register
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__ z_lghi(r4_reven_dst, 0); // make upper 64bits 0
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__ z_dlgr(r4_reven_dst, b);
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__ block_comment("} unsigned_mod_long");
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%}
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ins_pipe(pipe_class_dummy);
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%}
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// Register Long Remainder
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instruct modL_reg_imm16(revenRegL dst, iRegL src1, immL16 src2, roddRegL tmp, flagsReg cr) %{
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match(Set dst (ModL src1 src2));
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