8277619: AArch64: Incorrect parameter type in Advanced SIMD Copy assembler functions
Reviewed-by: aph, pli
This commit is contained in:
parent
46f99aca94
commit
c442587f1e
src/hotspot/cpu/aarch64
test/hotspot/gtest/aarch64
@ -8565,10 +8565,10 @@ instruct popCountI(iRegINoSp dst, iRegIorL2I src, vRegF tmp) %{
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"mov $dst, $tmp\t# vector (1D)" %}
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ins_encode %{
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__ movw($src$$Register, $src$$Register); // ensure top 32 bits 0
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__ mov($tmp$$FloatRegister, __ T1D, 0, $src$$Register);
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__ mov($tmp$$FloatRegister, __ D, 0, $src$$Register);
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__ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
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__ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
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__ mov($dst$$Register, $tmp$$FloatRegister, __ T1D, 0);
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__ mov($dst$$Register, $tmp$$FloatRegister, __ D, 0);
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%}
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ins_pipe(pipe_class_default);
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@ -8590,7 +8590,7 @@ instruct popCountI_mem(iRegINoSp dst, memory4 mem, vRegF tmp) %{
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as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
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__ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
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__ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
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__ mov($dst$$Register, $tmp$$FloatRegister, __ T1D, 0);
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__ mov($dst$$Register, $tmp$$FloatRegister, __ D, 0);
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%}
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ins_pipe(pipe_class_default);
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@ -8608,10 +8608,10 @@ instruct popCountL(iRegINoSp dst, iRegL src, vRegD tmp) %{
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"addv $tmp, $tmp\t# vector (8B)\n\t"
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"mov $dst, $tmp\t# vector (1D)" %}
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ins_encode %{
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__ mov($tmp$$FloatRegister, __ T1D, 0, $src$$Register);
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__ mov($tmp$$FloatRegister, __ D, 0, $src$$Register);
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__ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
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__ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
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__ mov($dst$$Register, $tmp$$FloatRegister, __ T1D, 0);
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__ mov($dst$$Register, $tmp$$FloatRegister, __ D, 0);
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%}
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ins_pipe(pipe_class_default);
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@ -8633,7 +8633,7 @@ instruct popCountL_mem(iRegINoSp dst, memory8 mem, vRegD tmp) %{
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as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 8);
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__ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
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__ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
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__ mov($dst$$Register, $tmp$$FloatRegister, __ T1D, 0);
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__ mov($dst$$Register, $tmp$$FloatRegister, __ D, 0);
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%}
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ins_pipe(pipe_class_default);
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@ -511,7 +511,7 @@ instruct vcvt2Dto2I(vecD dst, vecX src)
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"fcvtzdw rscratch1, $src\n\t"
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"fcvtzdw rscratch2, $dst\n\t"
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"fmovs $dst, rscratch1\n\t"
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"mov $dst, T2S, 1, rscratch2\t#convert 2D to 2I vector"
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"mov $dst, S, 1, rscratch2\t#convert 2D to 2I vector"
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%}
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ins_encode %{
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__ ins(as_FloatRegister($dst$$reg), __ D, as_FloatRegister($src$$reg), 0, 1);
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@ -520,7 +520,7 @@ instruct vcvt2Dto2I(vecD dst, vecX src)
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__ fcvtzdw(rscratch1, as_FloatRegister($src$$reg));
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__ fcvtzdw(rscratch2, as_FloatRegister($dst$$reg));
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__ fmovs(as_FloatRegister($dst$$reg), rscratch1);
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__ mov(as_FloatRegister($dst$$reg), __ T2S, 1, rscratch2);
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__ mov(as_FloatRegister($dst$$reg), __ S, 1, rscratch2);
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%}
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ins_pipe(pipe_slow);
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%}
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@ -1703,13 +1703,13 @@ instruct insert8B(vecD dst, vecD src, iRegIorL2I val, immI idx)
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match(Set dst (VectorInsert (Binary src val) idx));
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ins_cost(INSN_COST);
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format %{ "orr $dst, T8B, $src, $src\n\t"
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"mov $dst, T8B, $idx, $val\t# insert into vector(8B)" %}
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"mov $dst, B, $idx, $val\t# insert into vector(8B)" %}
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ins_encode %{
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if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
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__ orr(as_FloatRegister($dst$$reg), __ T8B,
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as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
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}
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__ mov(as_FloatRegister($dst$$reg), __ T8B, $idx$$constant, $val$$Register);
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__ mov(as_FloatRegister($dst$$reg), __ B, $idx$$constant, $val$$Register);
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%}
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ins_pipe(pipe_slow);
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%}
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@ -1720,13 +1720,13 @@ instruct insert16B(vecX dst, vecX src, iRegIorL2I val, immI idx)
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match(Set dst (VectorInsert (Binary src val) idx));
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ins_cost(INSN_COST);
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format %{ "orr $dst, T16B, $src, $src\n\t"
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"mov $dst, T16B, $idx, $val\t# insert into vector(16B)" %}
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"mov $dst, B, $idx, $val\t# insert into vector(16B)" %}
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ins_encode %{
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if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
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__ orr(as_FloatRegister($dst$$reg), __ T16B,
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as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
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}
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__ mov(as_FloatRegister($dst$$reg), __ T16B, $idx$$constant, $val$$Register);
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__ mov(as_FloatRegister($dst$$reg), __ B, $idx$$constant, $val$$Register);
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%}
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ins_pipe(pipe_slow);
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%}
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@ -1737,13 +1737,13 @@ instruct insert4S(vecD dst, vecD src, iRegIorL2I val, immI idx)
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match(Set dst (VectorInsert (Binary src val) idx));
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ins_cost(INSN_COST);
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format %{ "orr $dst, T8B, $src, $src\n\t"
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"mov $dst, T4H, $idx, $val\t# insert into vector(4S)" %}
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"mov $dst, H, $idx, $val\t# insert into vector(4S)" %}
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ins_encode %{
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if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
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__ orr(as_FloatRegister($dst$$reg), __ T8B,
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as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
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}
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__ mov(as_FloatRegister($dst$$reg), __ T4H, $idx$$constant, $val$$Register);
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__ mov(as_FloatRegister($dst$$reg), __ H, $idx$$constant, $val$$Register);
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%}
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ins_pipe(pipe_slow);
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%}
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@ -1754,13 +1754,13 @@ instruct insert8S(vecX dst, vecX src, iRegIorL2I val, immI idx)
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match(Set dst (VectorInsert (Binary src val) idx));
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ins_cost(INSN_COST);
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format %{ "orr $dst, T16B, $src, $src\n\t"
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"mov $dst, T8H, $idx, $val\t# insert into vector(8S)" %}
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"mov $dst, H, $idx, $val\t# insert into vector(8S)" %}
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ins_encode %{
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if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
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__ orr(as_FloatRegister($dst$$reg), __ T16B,
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as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
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}
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__ mov(as_FloatRegister($dst$$reg), __ T8H, $idx$$constant, $val$$Register);
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__ mov(as_FloatRegister($dst$$reg), __ H, $idx$$constant, $val$$Register);
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%}
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ins_pipe(pipe_slow);
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%}
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@ -1771,13 +1771,13 @@ instruct insert2I(vecD dst, vecD src, iRegIorL2I val, immI idx)
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match(Set dst (VectorInsert (Binary src val) idx));
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ins_cost(INSN_COST);
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format %{ "orr $dst, T8B, $src, $src\n\t"
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"mov $dst, T2S, $idx, $val\t# insert into vector(2I)" %}
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"mov $dst, S, $idx, $val\t# insert into vector(2I)" %}
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ins_encode %{
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if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
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__ orr(as_FloatRegister($dst$$reg), __ T8B,
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as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
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}
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__ mov(as_FloatRegister($dst$$reg), __ T2S, $idx$$constant, $val$$Register);
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__ mov(as_FloatRegister($dst$$reg), __ S, $idx$$constant, $val$$Register);
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%}
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ins_pipe(pipe_slow);
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%}
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@ -1788,13 +1788,13 @@ instruct insert4I(vecX dst, vecX src, iRegIorL2I val, immI idx)
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match(Set dst (VectorInsert (Binary src val) idx));
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ins_cost(INSN_COST);
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format %{ "orr $dst, T16B, $src, $src\n\t"
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"mov $dst, T4S, $idx, $val\t# insert into vector(4I)" %}
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"mov $dst, S, $idx, $val\t# insert into vector(4I)" %}
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ins_encode %{
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if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
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__ orr(as_FloatRegister($dst$$reg), __ T16B,
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as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
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}
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__ mov(as_FloatRegister($dst$$reg), __ T4S, $idx$$constant, $val$$Register);
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__ mov(as_FloatRegister($dst$$reg), __ S, $idx$$constant, $val$$Register);
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%}
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ins_pipe(pipe_slow);
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%}
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@ -1805,13 +1805,13 @@ instruct insert2L(vecX dst, vecX src, iRegL val, immI idx)
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match(Set dst (VectorInsert (Binary src val) idx));
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ins_cost(INSN_COST);
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format %{ "orr $dst, T16B, $src, $src\n\t"
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"mov $dst, T2D, $idx, $val\t# insert into vector(2L)" %}
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"mov $dst, D, $idx, $val\t# insert into vector(2L)" %}
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ins_encode %{
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if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
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__ orr(as_FloatRegister($dst$$reg), __ T16B,
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as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
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}
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__ mov(as_FloatRegister($dst$$reg), __ T2D, $idx$$constant, $val$$Register);
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__ mov(as_FloatRegister($dst$$reg), __ D, $idx$$constant, $val$$Register);
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%}
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ins_pipe(pipe_slow);
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%}
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@ -2044,11 +2044,11 @@ instruct vmul2L(vecX dst, vecX src1, vecX src2, iRegLNoSp tmp1, iRegLNoSp tmp2)
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__ umov($tmp1$$Register, as_FloatRegister($src1$$reg), __ D, 0);
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__ umov($tmp2$$Register, as_FloatRegister($src2$$reg), __ D, 0);
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__ mul(as_Register($tmp2$$reg), as_Register($tmp2$$reg), as_Register($tmp1$$reg));
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__ mov(as_FloatRegister($dst$$reg), __ T2D, 0, $tmp2$$Register);
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__ mov(as_FloatRegister($dst$$reg), __ D, 0, $tmp2$$Register);
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__ umov($tmp1$$Register, as_FloatRegister($src1$$reg), __ D, 1);
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__ umov($tmp2$$Register, as_FloatRegister($src2$$reg), __ D, 1);
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__ mul(as_Register($tmp2$$reg), as_Register($tmp2$$reg), as_Register($tmp1$$reg));
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__ mov(as_FloatRegister($dst$$reg), __ T2D, 1, $tmp2$$Register);
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__ mov(as_FloatRegister($dst$$reg), __ D, 1, $tmp2$$Register);
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%}
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ins_pipe(pipe_slow);
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%}
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@ -296,7 +296,7 @@ instruct vcvt2Dto2I(vecD dst, vecX src)
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"fcvtzdw rscratch1, $src\n\t"
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"fcvtzdw rscratch2, $dst\n\t"
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"fmovs $dst, rscratch1\n\t"
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"mov $dst, T2S, 1, rscratch2\t#convert 2D to 2I vector"
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"mov $dst, S, 1, rscratch2\t#convert 2D to 2I vector"
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%}
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ins_encode %{
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__ ins(as_FloatRegister($dst$$reg), __ D, as_FloatRegister($src$$reg), 0, 1);
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@ -305,7 +305,7 @@ instruct vcvt2Dto2I(vecD dst, vecX src)
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__ fcvtzdw(rscratch1, as_FloatRegister($src$$reg));
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__ fcvtzdw(rscratch2, as_FloatRegister($dst$$reg));
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__ fmovs(as_FloatRegister($dst$$reg), rscratch1);
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__ mov(as_FloatRegister($dst$$reg), __ T2S, 1, rscratch2);
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__ mov(as_FloatRegister($dst$$reg), __ S, 1, rscratch2);
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%}
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ins_pipe(pipe_slow);
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%}
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@ -868,13 +868,13 @@ instruct insert$1$2`'(vec$3 dst, vec$3 src, iReg$4`'ORL2I($4) val, immI idx)
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match(Set dst (VectorInsert (Binary src val) idx));
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ins_cost(INSN_COST);
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format %{ "orr $dst, T$5, $src, $src\n\t"
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"mov $dst, T$1`'iTYPE2SIMD($2), $idx, $val\t# insert into vector($1$2)" %}
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"mov $dst, iTYPE2SIMD($2), $idx, $val\t# insert into vector($1$2)" %}
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ins_encode %{
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if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
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__ orr(as_FloatRegister($dst$$reg), __ T$5,
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as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
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}
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__ mov(as_FloatRegister($dst$$reg), __ T$1`'iTYPE2SIMD($2), $idx$$constant, $val$$Register);
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__ mov(as_FloatRegister($dst$$reg), __ iTYPE2SIMD($2), $idx$$constant, $val$$Register);
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%}
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ins_pipe(pipe_slow);
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%}')dnl
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@ -1003,11 +1003,11 @@ instruct vmul2L(vecX dst, vecX src1, vecX src2, iRegLNoSp tmp1, iRegLNoSp tmp2)
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__ umov($tmp1$$Register, as_FloatRegister($src1$$reg), __ D, 0);
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__ umov($tmp2$$Register, as_FloatRegister($src2$$reg), __ D, 0);
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__ mul(as_Register($tmp2$$reg), as_Register($tmp2$$reg), as_Register($tmp1$$reg));
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__ mov(as_FloatRegister($dst$$reg), __ T2D, 0, $tmp2$$Register);
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__ mov(as_FloatRegister($dst$$reg), __ D, 0, $tmp2$$Register);
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__ umov($tmp1$$Register, as_FloatRegister($src1$$reg), __ D, 1);
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__ umov($tmp2$$Register, as_FloatRegister($src2$$reg), __ D, 1);
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__ mul(as_Register($tmp2$$reg), as_Register($tmp2$$reg), as_Register($tmp1$$reg));
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__ mov(as_FloatRegister($dst$$reg), __ T2D, 1, $tmp2$$Register);
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__ mov(as_FloatRegister($dst$$reg), __ D, 1, $tmp2$$Register);
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%}
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ins_pipe(pipe_slow);
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%}
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@ -2756,20 +2756,18 @@ public:
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// Move from general purpose register
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// mov Vd.T[index], Rn
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void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) {
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void mov(FloatRegister Vd, SIMD_RegVariant T, int index, Register Xn) {
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guarantee(T != Q, "invalid register variant");
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starti;
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f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
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f(0b01001110000, 31, 21), f(((1 << T) | (index << (T + 1))), 20, 16);
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f(0b000111, 15, 10), zrf(Xn, 5), rf(Vd, 0);
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}
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// Move to general purpose register
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// mov Rd, Vn.T[index]
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void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) {
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guarantee(T >= T2S && T < T1Q, "only D and S arrangements are supported");
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starti;
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f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21);
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f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
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f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0);
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void mov(Register Xd, FloatRegister Vn, SIMD_RegVariant T, int index) {
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guarantee(T == S || T == D, "invalid register variant");
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umov(Xd, Vn, T, index);
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}
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private:
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@ -3367,7 +3367,7 @@ void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
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ld1r(v5, T2D, post(tmp, 8));
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ld1r(v6, T2D, post(tmp, 8));
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ld1r(v7, T2D, post(tmp, 8));
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mov(v16, T4S, 0, crc);
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mov(v16, S, 0, crc);
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eor(v0, T16B, v0, v16);
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sub(len, len, 64);
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@ -3471,16 +3471,16 @@ void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
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br(Assembler::GE, L_fold);
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mov(crc, 0);
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mov(tmp, v0, T1D, 0);
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mov(tmp, v0, D, 0);
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update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
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update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
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mov(tmp, v0, T1D, 1);
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mov(tmp, v0, D, 1);
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update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
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update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
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mov(tmp, v1, T1D, 0);
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mov(tmp, v1, D, 0);
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update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
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update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
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mov(tmp, v1, T1D, 1);
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mov(tmp, v1, D, 1);
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update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
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update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
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@ -1571,10 +1571,10 @@ generate(SpecialCases, [["ccmn", "__ ccmn(zr, zr, 3u, Assembler::LE);",
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["stxpw", "__ stxpw(r6, zr, zr, sp);", "stxp\tw6, wzr, wzr, [sp]"],
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["dup", "__ dup(v0, __ T16B, zr);", "dup\tv0.16b, wzr"],
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["dup", "__ dup(v0, __ S, v1);", "dup\ts0, v1.s[0]"],
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["mov", "__ mov(v1, __ T1D, 0, zr);", "mov\tv1.d[0], xzr"],
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["mov", "__ mov(v1, __ T2S, 1, zr);", "mov\tv1.s[1], wzr"],
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["mov", "__ mov(v1, __ T4H, 2, zr);", "mov\tv1.h[2], wzr"],
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["mov", "__ mov(v1, __ T8B, 3, zr);", "mov\tv1.b[3], wzr"],
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["mov", "__ mov(v1, __ D, 0, zr);", "mov\tv1.d[0], xzr"],
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["mov", "__ mov(v1, __ S, 1, zr);", "mov\tv1.s[1], wzr"],
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["mov", "__ mov(v1, __ H, 2, zr);", "mov\tv1.h[2], wzr"],
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["mov", "__ mov(v1, __ B, 3, zr);", "mov\tv1.b[3], wzr"],
|
||||
["smov", "__ smov(r0, v1, __ S, 0);", "smov\tx0, v1.s[0]"],
|
||||
["smov", "__ smov(r0, v1, __ H, 1);", "smov\tx0, v1.h[1]"],
|
||||
["smov", "__ smov(r0, v1, __ B, 2);", "smov\tx0, v1.b[2]"],
|
||||
|
@ -713,10 +713,10 @@
|
||||
__ stxpw(r6, zr, zr, sp); // stxp w6, wzr, wzr, [sp]
|
||||
__ dup(v0, __ T16B, zr); // dup v0.16b, wzr
|
||||
__ dup(v0, __ S, v1); // dup s0, v1.s[0]
|
||||
__ mov(v1, __ T1D, 0, zr); // mov v1.d[0], xzr
|
||||
__ mov(v1, __ T2S, 1, zr); // mov v1.s[1], wzr
|
||||
__ mov(v1, __ T4H, 2, zr); // mov v1.h[2], wzr
|
||||
__ mov(v1, __ T8B, 3, zr); // mov v1.b[3], wzr
|
||||
__ mov(v1, __ D, 0, zr); // mov v1.d[0], xzr
|
||||
__ mov(v1, __ S, 1, zr); // mov v1.s[1], wzr
|
||||
__ mov(v1, __ H, 2, zr); // mov v1.h[2], wzr
|
||||
__ mov(v1, __ B, 3, zr); // mov v1.b[3], wzr
|
||||
__ smov(r0, v1, __ S, 0); // smov x0, v1.s[0]
|
||||
__ smov(r0, v1, __ H, 1); // smov x0, v1.h[1]
|
||||
__ smov(r0, v1, __ B, 2); // smov x0, v1.b[2]
|
||||
|
Loading…
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Reference in New Issue
Block a user