8171244: PPC64: Make interpreter's math entries consistent with C1 and C2 and support FMA
Reviewed-by: kvn, goetz
This commit is contained in:
Martin Doerr
parent
d652c70de6
commit
c44e860576
@ -51,19 +51,25 @@ int AbstractInterpreter::BasicType_as_index(BasicType type) {
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return i;
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}
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// Support abs and sqrt like in compiler.
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// For others we can use a normal (native) entry.
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bool AbstractInterpreter::math_entry_available(AbstractInterpreter::MethodKind kind) {
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if (!InlineIntrinsics) return false;
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return ((kind==Interpreter::java_lang_math_sqrt && VM_Version::has_fsqrt()) ||
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(kind==Interpreter::java_lang_math_abs));
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}
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// These should never be compiled since the interpreter will prefer
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// the compiled version to the intrinsic version.
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bool AbstractInterpreter::can_be_compiled(methodHandle m) {
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return !math_entry_available(method_kind(m));
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switch (method_kind(m)) {
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case Interpreter::java_lang_math_sin : // fall thru
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case Interpreter::java_lang_math_cos : // fall thru
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case Interpreter::java_lang_math_tan : // fall thru
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case Interpreter::java_lang_math_abs : // fall thru
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case Interpreter::java_lang_math_log : // fall thru
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case Interpreter::java_lang_math_log10 : // fall thru
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case Interpreter::java_lang_math_sqrt : // fall thru
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case Interpreter::java_lang_math_pow : // fall thru
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case Interpreter::java_lang_math_exp : // fall thru
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case Interpreter::java_lang_math_fmaD : // fall thru
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case Interpreter::java_lang_math_fmaF :
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return false;
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default:
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return true;
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}
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}
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// How much stack a method activation needs in stack slots.
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@ -460,16 +460,15 @@ class Assembler : public AbstractAssembler {
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FCTIWZ_OPCODE = (63u << OPCODE_SHIFT | 15u << 1),
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FRSP_OPCODE = (63u << OPCODE_SHIFT | 12u << 1),
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// WARNING: using fmadd results in a non-compliant vm. Some floating
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// point tck tests will fail.
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FMADD_OPCODE = (59u << OPCODE_SHIFT | 29u << 1),
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DMADD_OPCODE = (63u << OPCODE_SHIFT | 29u << 1),
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FMSUB_OPCODE = (59u << OPCODE_SHIFT | 28u << 1),
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DMSUB_OPCODE = (63u << OPCODE_SHIFT | 28u << 1),
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FNMADD_OPCODE = (59u << OPCODE_SHIFT | 31u << 1),
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DNMADD_OPCODE = (63u << OPCODE_SHIFT | 31u << 1),
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FNMSUB_OPCODE = (59u << OPCODE_SHIFT | 30u << 1),
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DNMSUB_OPCODE = (63u << OPCODE_SHIFT | 30u << 1),
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// Fused multiply-accumulate instructions.
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FMADD_OPCODE = (63u << OPCODE_SHIFT | 29u << 1),
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FMADDS_OPCODE = (59u << OPCODE_SHIFT | 29u << 1),
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FMSUB_OPCODE = (63u << OPCODE_SHIFT | 28u << 1),
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FMSUBS_OPCODE = (59u << OPCODE_SHIFT | 28u << 1),
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FNMADD_OPCODE = (63u << OPCODE_SHIFT | 31u << 1),
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FNMADDS_OPCODE = (59u << OPCODE_SHIFT | 31u << 1),
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FNMSUB_OPCODE = (63u << OPCODE_SHIFT | 30u << 1),
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FNMSUBS_OPCODE = (59u << OPCODE_SHIFT | 30u << 1),
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LFD_OPCODE = (50u << OPCODE_SHIFT | 00u << 1),
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LFDU_OPCODE = (51u << OPCODE_SHIFT | 00u << 1),
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@ -1939,6 +1938,26 @@ class Assembler : public AbstractAssembler {
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inline void fdivs( FloatRegister d, FloatRegister a, FloatRegister b);
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inline void fdivs_(FloatRegister d, FloatRegister a, FloatRegister b);
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// Fused multiply-accumulate instructions.
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// WARNING: Use only when rounding between the 2 parts is not desired.
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// Some floating point tck tests will fail if used incorrectly.
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inline void fmadd( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
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inline void fmadd_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
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inline void fmadds( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
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inline void fmadds_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
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inline void fmsub( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
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inline void fmsub_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
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inline void fmsubs( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
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inline void fmsubs_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
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inline void fnmadd( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
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inline void fnmadd_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
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inline void fnmadds( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
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inline void fnmadds_(FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
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inline void fnmsub( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
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inline void fnmsub_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
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inline void fnmsubs( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
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inline void fnmsubs_(FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
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// PPC 1, section 4.6.6 Floating-Point Rounding and Conversion Instructions
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inline void frsp( FloatRegister d, FloatRegister b);
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inline void fctid( FloatRegister d, FloatRegister b);
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@ -700,6 +700,26 @@ inline void Assembler::fdiv_( FloatRegister d, FloatRegister a, FloatRegister b)
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inline void Assembler::fdivs( FloatRegister d, FloatRegister a, FloatRegister b) { emit_int32( FDIVS_OPCODE | frt(d) | fra(a) | frb(b) | rc(0)); }
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inline void Assembler::fdivs_(FloatRegister d, FloatRegister a, FloatRegister b) { emit_int32( FDIVS_OPCODE | frt(d) | fra(a) | frb(b) | rc(1)); }
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// Fused multiply-accumulate instructions.
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// WARNING: Use only when rounding between the 2 parts is not desired.
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// Some floating point tck tests will fail if used incorrectly.
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inline void Assembler::fmadd( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FMADD_OPCODE | frt(d) | fra(a) | frb(b) | frc(c) | rc(0)); }
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inline void Assembler::fmadd_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FMADD_OPCODE | frt(d) | fra(a) | frb(b) | frc(c) | rc(1)); }
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inline void Assembler::fmadds( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FMADDS_OPCODE | frt(d) | fra(a) | frb(b) | frc(c) | rc(0)); }
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inline void Assembler::fmadds_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FMADDS_OPCODE | frt(d) | fra(a) | frb(b) | frc(c) | rc(1)); }
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inline void Assembler::fmsub( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FMSUB_OPCODE | frt(d) | fra(a) | frb(b) | frc(c) | rc(0)); }
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inline void Assembler::fmsub_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FMSUB_OPCODE | frt(d) | fra(a) | frb(b) | frc(c) | rc(1)); }
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inline void Assembler::fmsubs( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FMSUBS_OPCODE | frt(d) | fra(a) | frb(b) | frc(c) | rc(0)); }
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inline void Assembler::fmsubs_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FMSUBS_OPCODE | frt(d) | fra(a) | frb(b) | frc(c) | rc(1)); }
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inline void Assembler::fnmadd( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FNMADD_OPCODE | frt(d) | fra(a) | frb(b) | frc(c) | rc(0)); }
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inline void Assembler::fnmadd_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FNMADD_OPCODE | frt(d) | fra(a) | frb(b) | frc(c) | rc(1)); }
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inline void Assembler::fnmadds( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FNMADDS_OPCODE | frt(d) | fra(a) | frb(b) | frc(c) | rc(0)); }
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inline void Assembler::fnmadds_(FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FNMADDS_OPCODE | frt(d) | fra(a) | frb(b) | frc(c) | rc(1)); }
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inline void Assembler::fnmsub( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FNMSUB_OPCODE | frt(d) | fra(a) | frb(b) | frc(c) | rc(0)); }
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inline void Assembler::fnmsub_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FNMSUB_OPCODE | frt(d) | fra(a) | frb(b) | frc(c) | rc(1)); }
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inline void Assembler::fnmsubs( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FNMSUBS_OPCODE | frt(d) | fra(a) | frb(b) | frc(c) | rc(0)); }
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inline void Assembler::fnmsubs_(FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b) { emit_int32( FNMSUBS_OPCODE | frt(d) | fra(a) | frb(b) | frc(c) | rc(1)); }
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// PPC 1, section 4.6.6 Floating-Point Rounding and Conversion Instructions
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inline void Assembler::frsp( FloatRegister d, FloatRegister b) { emit_int32( FRSP_OPCODE | frt(d) | frb(b) | rc(0)); }
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inline void Assembler::fctid( FloatRegister d, FloatRegister b) { emit_int32( FCTID_OPCODE | frt(d) | frb(b) | rc(0)); }
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@ -292,28 +292,28 @@ void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
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}
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void LIR_Assembler::emit_op3(LIR_Op3* op) {
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const bool is_int = op->result_opr()->is_single_cpu();
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Register Rdividend = is_int ? op->in_opr1()->as_register() : op->in_opr1()->as_register_lo();
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void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
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const bool is_int = result->is_single_cpu();
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Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
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Register Rdivisor = noreg;
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Register Rscratch = op->in_opr3()->as_register();
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Register Rresult = is_int ? op->result_opr()->as_register() : op->result_opr()->as_register_lo();
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Register Rscratch = temp->as_register();
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Register Rresult = is_int ? result->as_register() : result->as_register_lo();
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long divisor = -1;
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if (op->in_opr2()->is_register()) {
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Rdivisor = is_int ? op->in_opr2()->as_register() : op->in_opr2()->as_register_lo();
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if (right->is_register()) {
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Rdivisor = is_int ? right->as_register() : right->as_register_lo();
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} else {
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divisor = is_int ? op->in_opr2()->as_constant_ptr()->as_jint()
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: op->in_opr2()->as_constant_ptr()->as_jlong();
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divisor = is_int ? right->as_constant_ptr()->as_jint()
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: right->as_constant_ptr()->as_jlong();
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}
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assert(Rdividend != Rscratch, "");
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assert(Rdivisor != Rscratch, "");
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assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
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assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
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if (Rdivisor == noreg) {
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if (divisor == 1) { // stupid, but can happen
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if (op->code() == lir_idiv) {
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if (code == lir_idiv) {
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__ mr_if_needed(Rresult, Rdividend);
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} else {
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__ li(Rresult, 0);
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@ -340,7 +340,7 @@ void LIR_Assembler::emit_op3(LIR_Op3* op) {
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}
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__ add(Rscratch, Rdividend, Rscratch);
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if (op->code() == lir_idiv) {
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if (code == lir_idiv) {
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if (is_int) {
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__ srawi(Rresult, Rscratch, log2);
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} else {
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@ -352,7 +352,7 @@ void LIR_Assembler::emit_op3(LIR_Op3* op) {
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}
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} else if (divisor == -1) {
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if (op->code() == lir_idiv) {
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if (code == lir_idiv) {
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__ neg(Rresult, Rdividend);
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} else {
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__ li(Rresult, 0);
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@ -360,7 +360,7 @@ void LIR_Assembler::emit_op3(LIR_Op3* op) {
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} else {
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__ load_const_optimized(Rscratch, divisor);
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if (op->code() == lir_idiv) {
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if (code == lir_idiv) {
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if (is_int) {
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__ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
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} else {
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@ -389,7 +389,7 @@ void LIR_Assembler::emit_op3(LIR_Op3* op) {
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__ cmpdi(CCR0, Rdivisor, -1);
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}
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__ bne(CCR0, regular);
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if (op->code() == lir_idiv) {
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if (code == lir_idiv) {
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__ neg(Rresult, Rdividend);
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__ b(done);
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__ bind(regular);
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@ -415,6 +415,26 @@ void LIR_Assembler::emit_op3(LIR_Op3* op) {
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}
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void LIR_Assembler::emit_op3(LIR_Op3* op) {
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switch (op->code()) {
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case lir_idiv:
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case lir_irem:
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arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
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op->result_opr(), op->info());
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break;
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case lir_fmad:
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__ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
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op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
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break;
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case lir_fmaf:
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__ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
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op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
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break;
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default: ShouldNotReachHere(); break;
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}
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}
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void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
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#ifdef ASSERT
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assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
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@ -1435,7 +1435,26 @@ void LIRGenerator::do_update_CRC32(Intrinsic* x) {
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}
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void LIRGenerator::do_FmaIntrinsic(Intrinsic* x) {
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fatal("FMA intrinsic is not implemented on this platform");
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assert(x->number_of_arguments() == 3, "wrong type");
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assert(UseFMA, "Needs FMA instructions support.");
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LIRItem value(x->argument_at(0), this);
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LIRItem value1(x->argument_at(1), this);
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LIRItem value2(x->argument_at(2), this);
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value.load_item();
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value1.load_item();
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value2.load_item();
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LIR_Opr calc_input = value.result();
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LIR_Opr calc_input1 = value1.result();
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LIR_Opr calc_input2 = value2.result();
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LIR_Opr calc_result = rlock_result(x);
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switch (x->id()) {
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case vmIntrinsics::_fmaD: __ fmad(calc_input, calc_input1, calc_input2, calc_result); break;
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case vmIntrinsics::_fmaF: __ fmaf(calc_input, calc_input1, calc_input2, calc_result); break;
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default: ShouldNotReachHere();
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}
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}
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void LIRGenerator::do_vectorizedMismatch(Intrinsic* x) {
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@ -9569,6 +9569,117 @@ instruct roundFloat_nop(regF dst) %{
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ins_pipe(pipe_class_default);
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%}
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// Multiply-Accumulate
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// src1 * src2 + src3
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instruct maddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
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match(Set dst (FmaF src3 (Binary src1 src2)));
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format %{ "FMADDS $dst, $src1, $src2, $src3" %}
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size(4);
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ins_encode %{
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// TODO: PPC port $archOpcode(ppc64Opcode_fmadds);
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__ fmadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
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%}
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ins_pipe(pipe_class_default);
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%}
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// src1 * src2 + src3
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instruct maddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
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match(Set dst (FmaD src3 (Binary src1 src2)));
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format %{ "FMADD $dst, $src1, $src2, $src3" %}
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size(4);
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ins_encode %{
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// TODO: PPC port $archOpcode(ppc64Opcode_fmadd);
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__ fmadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
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%}
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ins_pipe(pipe_class_default);
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%}
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// -src1 * src2 + src3 = -(src1*src2-src3)
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instruct mnsubF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
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match(Set dst (FmaF src3 (Binary (NegF src1) src2)));
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match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
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format %{ "FNMSUBS $dst, $src1, $src2, $src3" %}
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size(4);
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ins_encode %{
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// TODO: PPC port $archOpcode(ppc64Opcode_fnmsubs);
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__ fnmsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
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%}
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ins_pipe(pipe_class_default);
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%}
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// -src1 * src2 + src3 = -(src1*src2-src3)
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instruct mnsubD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
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match(Set dst (FmaD src3 (Binary (NegD src1) src2)));
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match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
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format %{ "FNMSUB $dst, $src1, $src2, $src3" %}
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size(4);
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ins_encode %{
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// TODO: PPC port $archOpcode(ppc64Opcode_fnmsub);
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__ fnmsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
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%}
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ins_pipe(pipe_class_default);
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%}
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// -src1 * src2 - src3 = -(src1*src2+src3)
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instruct mnaddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
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match(Set dst (FmaF (NegF src3) (Binary (NegF src1) src2)));
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match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
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format %{ "FNMADDS $dst, $src1, $src2, $src3" %}
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size(4);
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ins_encode %{
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// TODO: PPC port $archOpcode(ppc64Opcode_fnmadds);
|
||||
__ fnmadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
// -src1 * src2 - src3 = -(src1*src2+src3)
|
||||
instruct mnaddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
|
||||
match(Set dst (FmaD (NegD src3) (Binary (NegD src1) src2)));
|
||||
match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
|
||||
|
||||
format %{ "FNMADD $dst, $src1, $src2, $src3" %}
|
||||
size(4);
|
||||
ins_encode %{
|
||||
// TODO: PPC port $archOpcode(ppc64Opcode_fnmadd);
|
||||
__ fnmadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
// src1 * src2 - src3
|
||||
instruct msubF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
|
||||
match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
|
||||
|
||||
format %{ "FMSUBS $dst, $src1, $src2, $src3" %}
|
||||
size(4);
|
||||
ins_encode %{
|
||||
// TODO: PPC port $archOpcode(ppc64Opcode_fmsubs);
|
||||
__ fmsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
// src1 * src2 - src3
|
||||
instruct msubD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
|
||||
match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
|
||||
|
||||
format %{ "FMSUB $dst, $src1, $src2, $src3" %}
|
||||
size(4);
|
||||
ins_encode %{
|
||||
// TODO: PPC port $archOpcode(ppc64Opcode_fmsub);
|
||||
__ fmsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
|
||||
//----------Logical Instructions-----------------------------------------------
|
||||
|
||||
// And Instructions
|
||||
|
||||
@ -1134,14 +1134,57 @@ void TemplateInterpreterGenerator::generate_fixed_frame(bool native_call, Regist
|
||||
// End of helpers
|
||||
|
||||
address TemplateInterpreterGenerator::generate_math_entry(AbstractInterpreter::MethodKind kind) {
|
||||
if (!Interpreter::math_entry_available(kind)) {
|
||||
NOT_PRODUCT(__ should_not_reach_here();)
|
||||
return NULL;
|
||||
|
||||
// Decide what to do: Use same platform specific instructions and runtime calls as compilers.
|
||||
bool use_instruction = false;
|
||||
address runtime_entry = NULL;
|
||||
int num_args = 1;
|
||||
bool double_precision = true;
|
||||
|
||||
// PPC64 specific:
|
||||
switch (kind) {
|
||||
case Interpreter::java_lang_math_sqrt: use_instruction = VM_Version::has_fsqrt(); break;
|
||||
case Interpreter::java_lang_math_abs: use_instruction = true; break;
|
||||
case Interpreter::java_lang_math_fmaF:
|
||||
case Interpreter::java_lang_math_fmaD: use_instruction = UseFMA; break;
|
||||
default: break; // Fall back to runtime call.
|
||||
}
|
||||
|
||||
switch (kind) {
|
||||
case Interpreter::java_lang_math_sin : runtime_entry = CAST_FROM_FN_PTR(address, SharedRuntime::dsin); break;
|
||||
case Interpreter::java_lang_math_cos : runtime_entry = CAST_FROM_FN_PTR(address, SharedRuntime::dcos); break;
|
||||
case Interpreter::java_lang_math_tan : runtime_entry = CAST_FROM_FN_PTR(address, SharedRuntime::dtan); break;
|
||||
case Interpreter::java_lang_math_abs : /* run interpreted */ break;
|
||||
case Interpreter::java_lang_math_sqrt : runtime_entry = CAST_FROM_FN_PTR(address, SharedRuntime::dsqrt); break;
|
||||
case Interpreter::java_lang_math_log : runtime_entry = CAST_FROM_FN_PTR(address, SharedRuntime::dlog); break;
|
||||
case Interpreter::java_lang_math_log10: runtime_entry = CAST_FROM_FN_PTR(address, SharedRuntime::dlog10); break;
|
||||
case Interpreter::java_lang_math_pow : runtime_entry = CAST_FROM_FN_PTR(address, SharedRuntime::dpow); num_args = 2; break;
|
||||
case Interpreter::java_lang_math_exp : runtime_entry = CAST_FROM_FN_PTR(address, SharedRuntime::dexp); break;
|
||||
case Interpreter::java_lang_math_fmaF : /* run interpreted */ num_args = 3; double_precision = false; break;
|
||||
case Interpreter::java_lang_math_fmaD : /* run interpreted */ num_args = 3; break;
|
||||
default: ShouldNotReachHere();
|
||||
}
|
||||
|
||||
// Use normal entry if neither instruction nor runtime call is used.
|
||||
if (!use_instruction && runtime_entry == NULL) return NULL;
|
||||
|
||||
address entry = __ pc();
|
||||
|
||||
__ lfd(F1_RET, Interpreter::stackElementSize, R15_esp);
|
||||
// Load arguments
|
||||
assert(num_args <= 13, "passed in registers");
|
||||
if (double_precision) {
|
||||
int offset = (2 * num_args - 1) * Interpreter::stackElementSize;
|
||||
for (int i = 0; i < num_args; ++i) {
|
||||
__ lfd(as_FloatRegister(F1_ARG1->encoding() + i), offset, R15_esp);
|
||||
offset -= 2 * Interpreter::stackElementSize;
|
||||
}
|
||||
} else {
|
||||
int offset = num_args * Interpreter::stackElementSize;
|
||||
for (int i = 0; i < num_args; ++i) {
|
||||
__ lfs(as_FloatRegister(F1_ARG1->encoding() + i), offset, R15_esp);
|
||||
offset -= Interpreter::stackElementSize;
|
||||
}
|
||||
}
|
||||
|
||||
// Pop c2i arguments (if any) off when we return.
|
||||
#ifdef ASSERT
|
||||
@ -1152,15 +1195,30 @@ address TemplateInterpreterGenerator::generate_math_entry(AbstractInterpreter::M
|
||||
#endif // ASSERT
|
||||
__ mr(R1_SP, R21_sender_SP); // Cut the stack back to where the caller started.
|
||||
|
||||
if (kind == Interpreter::java_lang_math_sqrt) {
|
||||
__ fsqrt(F1_RET, F1_RET);
|
||||
} else if (kind == Interpreter::java_lang_math_abs) {
|
||||
__ fabs(F1_RET, F1_RET);
|
||||
if (use_instruction) {
|
||||
switch (kind) {
|
||||
case Interpreter::java_lang_math_sqrt: __ fsqrt(F1_RET, F1); break;
|
||||
case Interpreter::java_lang_math_abs: __ fabs(F1_RET, F1); break;
|
||||
case Interpreter::java_lang_math_fmaF: __ fmadds(F1_RET, F1, F2, F3); break;
|
||||
case Interpreter::java_lang_math_fmaD: __ fmadd(F1_RET, F1, F2, F3); break;
|
||||
default: ShouldNotReachHere();
|
||||
}
|
||||
} else {
|
||||
ShouldNotReachHere();
|
||||
// Comment: Can use tail call if the unextended frame is always C ABI compliant:
|
||||
//__ load_const_optimized(R12_scratch2, runtime_entry, R0);
|
||||
//__ call_c_and_return_to_caller(R12_scratch2);
|
||||
|
||||
// Push a new C frame and save LR.
|
||||
__ save_LR_CR(R0);
|
||||
__ push_frame_reg_args(0, R11_scratch1);
|
||||
|
||||
__ call_VM_leaf(runtime_entry);
|
||||
|
||||
// Pop the C frame and restore LR.
|
||||
__ pop_frame();
|
||||
__ restore_LR_CR(R0);
|
||||
}
|
||||
|
||||
// And we're done.
|
||||
__ blr();
|
||||
|
||||
__ flush();
|
||||
|
||||
@ -230,9 +230,8 @@ void VM_Version::initialize() {
|
||||
FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
|
||||
}
|
||||
|
||||
if (UseFMA) {
|
||||
warning("FMA instructions are not available on this CPU");
|
||||
FLAG_SET_DEFAULT(UseFMA, false);
|
||||
if (FLAG_IS_DEFAULT(UseFMA)) {
|
||||
FLAG_SET_DEFAULT(UseFMA, true);
|
||||
}
|
||||
|
||||
if (UseSHA) {
|
||||
|
||||
@ -299,10 +299,6 @@ class AbstractInterpreter: AllStatic {
|
||||
}
|
||||
|
||||
static void initialize_method_handle_entries();
|
||||
|
||||
// PPC-only: Support abs and sqrt like in compiler.
|
||||
// For others we can use a normal (native) entry.
|
||||
static bool math_entry_available(MethodKind kind);
|
||||
};
|
||||
|
||||
//------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Loading…
Reference in New Issue
Block a user