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This commit is contained in:
Lana Steuck 2015-03-19 16:13:07 -07:00
commit c88afadada
89 changed files with 1989 additions and 5842 deletions
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4
hotspot/agent/src/os/linux/libproc.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -30,7 +30,7 @@
#include <stdint.h>
#include "proc_service.h"
#if defined(arm) || defined(ppc)
#ifdef ALT_SASRCDIR
#include "libproc_md.h"
#endif

47
hotspot/agent/src/share/classes/sun/jvm/hotspot/HotSpotTypeDataBase.java
View File

@ -51,6 +51,9 @@ public class HotSpotTypeDataBase extends BasicTypeDataBase {
private static final int C_INT32_SIZE = 4;
private static final int C_INT64_SIZE = 8;
private static int pointerSize = UNINITIALIZED_SIZE;
// Counter to ensure read loops terminate:
private static final int MAX_DUPLICATE_DEFINITIONS = 100;
private int duplicateDefCount = 0;
private static final boolean DEBUG;
static {
@ -166,6 +169,10 @@ public class HotSpotTypeDataBase extends BasicTypeDataBase {
typeEntrySizeOffset = getLongValueFromProcess("gHotSpotVMTypeEntrySizeOffset");
typeEntryArrayStride = getLongValueFromProcess("gHotSpotVMTypeEntryArrayStride");
if (typeEntryArrayStride == 0L) {
throw new RuntimeException("zero stride: cannot read types.");
}
// Start iterating down it until we find an entry with no name
Address typeNameAddr = null;
do {
@ -192,7 +199,11 @@ public class HotSpotTypeDataBase extends BasicTypeDataBase {
}
entryAddr = entryAddr.addOffsetTo(typeEntryArrayStride);
} while (typeNameAddr != null);
} while (typeNameAddr != null && duplicateDefCount < MAX_DUPLICATE_DEFINITIONS);
if (duplicateDefCount >= MAX_DUPLICATE_DEFINITIONS) {
throw new RuntimeException("too many duplicate definitions");
}
}
private void initializePrimitiveTypes() {
@ -395,6 +406,10 @@ public class HotSpotTypeDataBase extends BasicTypeDataBase {
structEntryAddressOffset = getLongValueFromProcess("gHotSpotVMStructEntryAddressOffset");
structEntryArrayStride = getLongValueFromProcess("gHotSpotVMStructEntryArrayStride");
if (structEntryArrayStride == 0L) {
throw new RuntimeException("zero stride: cannot read types.");
}
// Fetch the address of the VMStructEntry*
Address entryAddr = lookupInProcess("gHotSpotVMStructs");
// Dereference this once to get the pointer to the first VMStructEntry
@ -472,6 +487,11 @@ public class HotSpotTypeDataBase extends BasicTypeDataBase {
intConstantEntryValueOffset = getLongValueFromProcess("gHotSpotVMIntConstantEntryValueOffset");
intConstantEntryArrayStride = getLongValueFromProcess("gHotSpotVMIntConstantEntryArrayStride");
if (intConstantEntryArrayStride == 0L) {
throw new RuntimeException("zero stride: cannot read types.");
}
// Fetch the address of the VMIntConstantEntry*
Address entryAddr = lookupInProcess("gHotSpotVMIntConstants");
// Dereference this once to get the pointer to the first VMIntConstantEntry
@ -501,12 +521,17 @@ public class HotSpotTypeDataBase extends BasicTypeDataBase {
} else {
System.err.println("Warning: the int constant \"" + name + "\" (declared in the remote VM in VMStructs::localHotSpotVMIntConstants) " +
"had its value declared as " + value + " twice. Continuing.");
duplicateDefCount++;
}
}
}
entryAddr = entryAddr.addOffsetTo(intConstantEntryArrayStride);
} while (nameAddr != null);
} while (nameAddr != null && duplicateDefCount < MAX_DUPLICATE_DEFINITIONS);
if (duplicateDefCount >= MAX_DUPLICATE_DEFINITIONS) {
throw new RuntimeException("too many duplicate definitions");
}
}
private void readVMLongConstants() {
@ -519,6 +544,10 @@ public class HotSpotTypeDataBase extends BasicTypeDataBase {
longConstantEntryValueOffset = getLongValueFromProcess("gHotSpotVMLongConstantEntryValueOffset");
longConstantEntryArrayStride = getLongValueFromProcess("gHotSpotVMLongConstantEntryArrayStride");
if (longConstantEntryArrayStride == 0L) {
throw new RuntimeException("zero stride: cannot read types.");
}
// Fetch the address of the VMLongConstantEntry*
Address entryAddr = lookupInProcess("gHotSpotVMLongConstants");
// Dereference this once to get the pointer to the first VMLongConstantEntry
@ -548,12 +577,17 @@ public class HotSpotTypeDataBase extends BasicTypeDataBase {
} else {
System.err.println("Warning: the long constant \"" + name + "\" (declared in the remote VM in VMStructs::localHotSpotVMLongConstants) " +
"had its value declared as " + value + " twice. Continuing.");
duplicateDefCount++;
}
}
}
entryAddr = entryAddr.addOffsetTo(longConstantEntryArrayStride);
} while (nameAddr != null);
} while (nameAddr != null && duplicateDefCount < MAX_DUPLICATE_DEFINITIONS);
if (duplicateDefCount >= MAX_DUPLICATE_DEFINITIONS) {
throw new RuntimeException("too many duplicate definitions.");
}
}
private BasicType lookupOrFail(String typeName) {
@ -740,9 +774,10 @@ public class HotSpotTypeDataBase extends BasicTypeDataBase {
}
if (!typeNameIsPointerType(typeName)) {
System.err.println("Warning: the type \"" + typeName + "\" (declared in the remote VM in VMStructs::localHotSpotVMTypes) " +
"had its size declared as " + size + " twice. Continuing.");
}
System.err.println("Warning: the type \"" + typeName + "\" (declared in the remote VM in VMStructs::localHotSpotVMTypes) " +
"had its size declared as " + size + " twice. Continuing.");
duplicateDefCount++;
}
}
}

13
hotspot/make/aix/makefiles/rules.make
View File

@ -126,10 +126,17 @@ QUIETLY$(MAKE_VERBOSE) = @
RUN.JAR$(MAKE_VERBOSE) += >/dev/null
# Settings for javac
BOOT_SOURCE_LANGUAGE_VERSION = 6
BOOT_TARGET_CLASS_VERSION = 6
JAVAC_FLAGS = -g -encoding ascii
BOOTSTRAP_JAVAC_FLAGS = $(JAVAC_FLAGS) -source $(BOOT_SOURCE_LANGUAGE_VERSION) -target $(BOOT_TARGET_CLASS_VERSION)
# Prefer BOOT_JDK_SOURCETARGET if it's set (typically by the top build system)
# Fall back to the values here if it's not set (hotspot only builds)
ifeq ($(BOOT_JDK_SOURCETARGET),)
BOOTSTRAP_SOURCETARGET := -source 8 -target 8
else
BOOTSTRAP_SOURCETARGET := $(BOOT_JDK_SOURCETARGET)
endif
BOOTSTRAP_JAVAC_FLAGS = $(JAVAC_FLAGS) $(BOOTSTRAP_SOURCETARGET)
# With parallel makes, print a message at the end of compilation.
ifeq ($(findstring j,$(MFLAGS)),j)

13
hotspot/make/bsd/makefiles/rules.make
View File

@ -126,10 +126,17 @@ QUIETLY$(MAKE_VERBOSE) = @
RUN.JAR$(MAKE_VERBOSE) += >/dev/null
# Settings for javac
BOOT_SOURCE_LANGUAGE_VERSION = 6
BOOT_TARGET_CLASS_VERSION = 6
JAVAC_FLAGS = -g -encoding ascii
BOOTSTRAP_JAVAC_FLAGS = $(JAVAC_FLAGS) -source $(BOOT_SOURCE_LANGUAGE_VERSION) -target $(BOOT_TARGET_CLASS_VERSION)
# Prefer BOOT_JDK_SOURCETARGET if it's set (typically by the top build system)
# Fall back to the values here if it's not set (hotspot only builds)
ifeq ($(BOOT_JDK_SOURCETARGET),)
BOOTSTRAP_SOURCETARGET := -source 8 -target 8
else
BOOTSTRAP_SOURCETARGET := $(BOOT_JDK_SOURCETARGET)
endif
BOOTSTRAP_JAVAC_FLAGS = $(JAVAC_FLAGS) $(BOOTSTRAP_SOURCETARGET)
# With parallel makes, print a message at the end of compilation.
ifeq ($(findstring j,$(MFLAGS)),j)

13
hotspot/make/defs.make
View File

@ -1,5 +1,5 @@
#
# Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved.
# Copyright (c) 2006, 2015, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
@ -286,7 +286,7 @@ ifneq ($(OSNAME),windows)
# Use uname output for SRCARCH, but deal with platform differences. If ARCH
# is not explicitly listed below, it is treated as x86.
SRCARCH = $(ARCH/$(filter sparc sparc64 ia64 amd64 x86_64 arm ppc ppc64 aarch64 zero,$(ARCH)))
SRCARCH ?= $(ARCH/$(filter sparc sparc64 ia64 amd64 x86_64 ppc ppc64 aarch64 zero,$(ARCH)))
ARCH/ = x86
ARCH/sparc = sparc
ARCH/sparc64= sparc
@ -295,12 +295,11 @@ ifneq ($(OSNAME),windows)
ARCH/x86_64 = x86
ARCH/ppc64 = ppc
ARCH/ppc = ppc
ARCH/arm = arm
ARCH/aarch64= aarch64
ARCH/zero = zero
# BUILDARCH is usually the same as SRCARCH, except for sparcv9
BUILDARCH = $(SRCARCH)
BUILDARCH ?= $(SRCARCH)
ifeq ($(BUILDARCH), x86)
ifdef LP64
BUILDARCH = amd64
@ -320,7 +319,7 @@ ifneq ($(OSNAME),windows)
endif
# LIBARCH is 1:1 mapping from BUILDARCH
LIBARCH = $(LIBARCH/$(BUILDARCH))
LIBARCH ?= $(LIBARCH/$(BUILDARCH))
LIBARCH/i486 = i386
LIBARCH/amd64 = amd64
LIBARCH/sparc = sparc
@ -328,8 +327,6 @@ ifneq ($(OSNAME),windows)
LIBARCH/ia64 = ia64
LIBARCH/ppc64 = ppc64
LIBARCH/aarch64 = aarch64
LIBARCH/ppc = ppc
LIBARCH/arm = arm
LIBARCH/zero = $(ZERO_LIBARCH)
LP64_ARCH = sparcv9 amd64 ia64 ppc64 aarch64 zero
@ -347,6 +344,8 @@ MAKE_ARGS += JRE_RELEASE_VERSION=$(JRE_RELEASE_VERSION)
# includes this make/defs.make file.
MAKE_ARGS += HOTSPOT_BUILD_VERSION=$(HOTSPOT_BUILD_VERSION)
MAKE_ARGS += BOOT_JDK_SOURCETARGET="$(BOOT_JDK_SOURCETARGET)"
# Various export sub directories
EXPORT_INCLUDE_DIR = $(EXPORT_PATH)/include
EXPORT_DOCS_DIR = $(EXPORT_PATH)/docs

31
hotspot/make/linux/makefiles/arm.make
View File

@ -1,31 +0,0 @@
#
# Copyright (c) 2008, 2013, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License version 2 only, as
# published by the Free Software Foundation.
#
# This code is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# version 2 for more details (a copy is included in the LICENSE file that
# accompanied this code).
#
# You should have received a copy of the GNU General Public License version
# 2 along with this work; if not, write to the Free Software Foundation,
# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
#
# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
# or visit www.oracle.com if you need additional information or have any
# questions.
#
#
Obj_Files += linux_arm.o
ifneq ($(EXT_LIBS_PATH),)
LIBS += $(EXT_LIBS_PATH)/sflt_glibc.a
endif
CFLAGS += -DVM_LITTLE_ENDIAN

6
hotspot/make/linux/makefiles/buildtree.make
View File

@ -1,5 +1,5 @@
#
# Copyright (c) 2005, 2014, Oracle and/or its affiliates. All rights reserved.
# Copyright (c) 2005, 2015, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
@ -70,6 +70,8 @@ else
PLATFORM_FILE = $(GAMMADIR)/make/$(OS_FAMILY)/platform_$(BUILDARCH).suncc
else
PLATFORM_FILE = $(GAMMADIR)/make/$(OS_FAMILY)/platform_$(BUILDARCH)
ALT_PLATFORM_FILE = $(HS_ALT_MAKE)/$(OS_FAMILY)/platform_$(BUILDARCH)
PLATFORM_FILE := $(if $(wildcard $(ALT_PLATFORM_FILE)),$(ALT_PLATFORM_FILE),$(PLATFORM_FILE))
endif
endif
@ -203,7 +205,7 @@ flags.make: $(BUILDTREE_MAKE) ../shared_dirs.lst
$(QUIETLY) ( \
$(BUILDTREE_COMMENT); \
echo; \
echo "Platform_file = $(PLATFORM_FILE)" | sed 's|$(GAMMADIR)|$$(GAMMADIR)|'; \
echo "Platform_file = $(PLATFORM_FILE)" | sed -e 's|$(HS_ALT_MAKE)|$$(HS_ALT_MAKE)|' -e 's|$(GAMMADIR)|$$(GAMMADIR)|'; \
sed -n '/=/s/^ */Platform_/p' < $(PLATFORM_FILE); \
echo; \
echo "GAMMADIR = $(GAMMADIR)"; \

14
hotspot/make/linux/makefiles/defs.make
View File

@ -1,5 +1,5 @@
#
# Copyright (c) 2006, 2014, Oracle and/or its affiliates. All rights reserved.
# Copyright (c) 2006, 2015, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
@ -105,14 +105,6 @@ ifneq (,$(findstring $(ARCH), amd64 x86_64 i686 i586))
HS_ARCH = x86
endif
# ARM
ifeq ($(ARCH), arm)
ARCH_DATA_MODEL = 32
PLATFORM = linux-arm
VM_PLATFORM = linux_arm
HS_ARCH = arm
endif
# PPC
# Notice: after 8046471 ARCH will be 'ppc' for top-level ppc64 builds but
# 'ppc64' for HotSpot-only ppc64 builds. Need to detect both variants here!
@ -121,10 +113,6 @@ ifneq (,$(findstring $(ARCH), ppc ppc64))
MAKE_ARGS += LP64=1
PLATFORM = linux-ppc64
VM_PLATFORM = linux_ppc64
else
ARCH_DATA_MODEL = 32
PLATFORM = linux-ppc
VM_PLATFORM = linux_ppc
endif
HS_ARCH = ppc

12
hotspot/make/linux/makefiles/gcc.make
View File

@ -1,5 +1,5 @@
#
# Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved.
# Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
@ -176,11 +176,7 @@ ARCHFLAG/aarch64 =
ARCHFLAG/ia64 =
ARCHFLAG/sparc = -m32 -mcpu=v9
ARCHFLAG/sparcv9 = -m64 -mcpu=v9
ARCHFLAG/arm = -fsigned-char
ARCHFLAG/zero = $(ZERO_ARCHFLAG)
ifndef E500V2
ARCHFLAG/ppc = -mcpu=powerpc
endif
ARCHFLAG/ppc64 = -m64
CFLAGS += $(ARCHFLAG)
@ -188,10 +184,6 @@ AOUT_FLAGS += $(ARCHFLAG)
LFLAGS += $(ARCHFLAG)
ASFLAGS += $(ARCHFLAG)
ifdef E500V2
CFLAGS += -DE500V2
endif
# Use C++ Interpreter
ifdef CC_INTERP
CFLAGS += -DCC_INTERP
@ -391,3 +383,5 @@ endif
ifndef USE_SUNCC
CFLAGS += -fno-omit-frame-pointer
endif
-include $(HS_ALT_MAKE)/linux/makefiles/gcc.make

33
hotspot/make/linux/makefiles/ppc.make
View File

@ -1,33 +0,0 @@
#
# Copyright (c) 2004, 2012, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License version 2 only, as
# published by the Free Software Foundation.
#
# This code is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# version 2 for more details (a copy is included in the LICENSE file that
# accompanied this code).
#
# You should have received a copy of the GNU General Public License version
# 2 along with this work; if not, write to the Free Software Foundation,
# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
#
# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
# or visit www.oracle.com if you need additional information or have any
# questions.
#
#
# The copied fdlibm routines in sharedRuntimeTrig.o must not be optimized
OPT_CFLAGS/sharedRuntimeTrig.o = $(OPT_CFLAGS/NOOPT)
# Must also specify if CPU is big endian
CFLAGS += -DVM_BIG_ENDIAN
ifdef E500V2
ASFLAGS += -Wa,-mspe -Wa,--defsym -Wa,E500V2=1
endif

13
hotspot/make/linux/makefiles/rules.make
View File

@ -126,10 +126,17 @@ QUIETLY$(MAKE_VERBOSE) = @
RUN.JAR$(MAKE_VERBOSE) += >/dev/null
# Settings for javac
BOOT_SOURCE_LANGUAGE_VERSION = 6
BOOT_TARGET_CLASS_VERSION = 6
JAVAC_FLAGS = -g -encoding ascii
BOOTSTRAP_JAVAC_FLAGS = $(JAVAC_FLAGS) -source $(BOOT_SOURCE_LANGUAGE_VERSION) -target $(BOOT_TARGET_CLASS_VERSION)
# Prefer BOOT_JDK_SOURCETARGET if it's set (typically by the top build system)
# Fall back to the values here if it's not set (hotspot only builds)
ifeq ($(BOOT_JDK_SOURCETARGET),)
BOOTSTRAP_SOURCETARGET := -source 8 -target 8
else
BOOTSTRAP_SOURCETARGET := $(BOOT_JDK_SOURCETARGET)
endif
BOOTSTRAP_JAVAC_FLAGS = $(JAVAC_FLAGS) $(BOOTSTRAP_SOURCETARGET)
# With parallel makes, print a message at the end of compilation.
ifeq ($(findstring j,$(MFLAGS)),j)

8
hotspot/make/linux/makefiles/saproc.make
View File

@ -1,5 +1,5 @@
#
# Copyright (c) 2005, 2014, Oracle and/or its affiliates. All rights reserved.
# Copyright (c) 2005, 2015, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
@ -69,19 +69,21 @@ endif
endif
ifneq ($(ALT_SASRCDIR),)
ALT_SAINCDIR=-I$(ALT_SASRCDIR)
ALT_SAINCDIR=-I$(ALT_SASRCDIR) -DALT_SASRCDIR
else
ALT_SAINCDIR=
endif
SA_LFLAGS = $(MAPFLAG:FILENAME=$(SAMAPFILE)) $(LDFLAGS_HASH_STYLE)
SAARCH ?= $(BUILDARCH)
$(LIBSAPROC): $(SASRCFILES) $(SAMAPFILE)
$(QUIETLY) if [ "$(BOOT_JAVA_HOME)" = "" ]; then \
echo "ALT_BOOTDIR, BOOTDIR or JAVA_HOME needs to be defined to build SA"; \
exit 1; \
fi
@echo $(LOG_INFO) Making SA debugger back-end...
$(QUIETLY) $(CC) -D$(BUILDARCH) -D_GNU_SOURCE \
$(QUIETLY) $(CC) -D$(SAARCH) -D_GNU_SOURCE \
-D_FILE_OFFSET_BITS=64 \
$(SYMFLAG) $(ARCHFLAG) $(SHARED_FLAG) $(PICFLAG) \
-I$(SASRCDIR) \

5
hotspot/make/linux/makefiles/vm.make
View File

@ -45,8 +45,9 @@ DEP_DIR = $(GENERATED)/dependencies
ifeq ($(findstring true, $(JVM_VARIANT_ZERO) $(JVM_VARIANT_ZEROSHARK)), true)
include $(MAKEFILES_DIR)/zeroshark.make
else
include $(MAKEFILES_DIR)/$(BUILDARCH).make
-include $(HS_ALT_MAKE)/$(Platform_os_family)/makefiles/$(BUILDARCH).make
BUILDARCH_MAKE = $(MAKEFILES_DIR)/$(BUILDARCH).make
ALT_BUILDARCH_MAKE = $(HS_ALT_MAKE)/$(Platform_os_family)/makefiles/$(BUILDARCH).make
include $(if $(wildcard $(ALT_BUILDARCH_MAKE)),$(ALT_BUILDARCH_MAKE),$(BUILDARCH_MAKE))
endif
# set VPATH so make knows where to look for source files

17
hotspot/make/linux/platform_arm
View File

@ -1,17 +0,0 @@
os_family = linux
arch = arm
arch_model = arm
os_arch = linux_arm
os_arch_model = linux_arm
lib_arch = arm
compiler = gcc
gnu_dis_arch = arm
sysdefs = -DLINUX -D_GNU_SOURCE -DARM

17
hotspot/make/linux/platform_ppc
View File

@ -1,17 +0,0 @@
os_family = linux
arch = ppc
arch_model = ppc_32
os_arch = linux_ppc
os_arch_model = linux_ppc_32
lib_arch = ppc
compiler = gcc
gnu_dis_arch = ppc
sysdefs = -DLINUX -D_GNU_SOURCE -DPPC32

13
hotspot/make/solaris/makefiles/rules.make
View File

@ -118,10 +118,17 @@ QUIETLY$(MAKE_VERBOSE) = @
RUN.JAR$(MAKE_VERBOSE) += >/dev/null
# Settings for javac
BOOT_SOURCE_LANGUAGE_VERSION = 6
BOOT_TARGET_CLASS_VERSION = 6
JAVAC_FLAGS = -g -encoding ascii
BOOTSTRAP_JAVAC_FLAGS = $(JAVAC_FLAGS) -source $(BOOT_SOURCE_LANGUAGE_VERSION) -target $(BOOT_TARGET_CLASS_VERSION)
# Prefer BOOT_JDK_SOURCETARGET if it's set (typically by the top build system)
# Fall back to the values here if it's not set (hotspot only builds)
ifeq ($(BOOT_JDK_SOURCETARGET),)
BOOTSTRAP_SOURCETARGET := -source 8 -target 8
else
BOOTSTRAP_SOURCETARGET := $(BOOT_JDK_SOURCETARGET)
endif
BOOTSTRAP_JAVAC_FLAGS = $(JAVAC_FLAGS) $(BOOTSTRAP_SOURCETARGET)
# With parallel makes, print a message at the end of compilation.
ifeq ($(findstring j,$(MFLAGS)),j)

13
hotspot/make/windows/makefiles/rules.make
View File

@ -44,10 +44,17 @@ BOOT_JAVA_HOME=
!endif
# Settings for javac
BOOT_SOURCE_LANGUAGE_VERSION=6
BOOT_TARGET_CLASS_VERSION=6
JAVAC_FLAGS=-g -encoding ascii
BOOTSTRAP_JAVAC_FLAGS=$(JAVAC_FLAGS) -source $(BOOT_SOURCE_LANGUAGE_VERSION) -target $(BOOT_TARGET_CLASS_VERSION)
# Prefer BOOT_JDK_SOURCETARGET if it's set (typically by the top build system)
# Fall back to the values here if it's not set (hotspot only builds)
!ifndef BOOT_JDK_SOURCETARGET
BOOTSTRAP_SOURCETARGET=-source 8 -target 8
!else
BOOTSTRAP_SOURCETARGET=$(BOOT_JDK_SOURCETARGET)
!endif
BOOTSTRAP_JAVAC_FLAGS=$(JAVAC_FLAGS) $(BOOTSTRAP_SOURCETARGET)
# VS2012 and VS2013 loads VS10 projects just fine (and will
# upgrade them automatically to VS2012 format).

1
hotspot/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp
View File

@ -2776,7 +2776,6 @@ void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
__ stop("unexpected profiling mismatch");
__ bind(ok);
__ pop(tmp);
}
#endif
// first time here. Set profile type.

2
hotspot/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp
View File

@ -872,7 +872,7 @@ public:
// stack grows down, caller passes positive offset
assert(offset > 0, "must bang with negative offset");
mov(rscratch2, -offset);
ldr(zr, Address(sp, rscratch2));
str(zr, Address(sp, rscratch2));
}
// Writes to stack successive pages until offset reached to check for

2
hotspot/src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp
View File

@ -858,7 +858,7 @@ void InterpreterGenerator::bang_stack_shadow_pages(bool native_call) {
const int page_size = os::vm_page_size();
for (int pages = start_page; pages <= StackShadowPages ; pages++) {
__ sub(rscratch2, sp, pages*page_size);
__ ldr(zr, Address(rscratch2));
__ str(zr, Address(rscratch2));
}
}
}

2
hotspot/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp
View File

@ -3947,12 +3947,10 @@ void LIR_Assembler::membar() {
void LIR_Assembler::membar_acquire() {
// No x86 machines currently require load fences
// __ load_fence();
}
void LIR_Assembler::membar_release() {
// No x86 machines currently require store fences
// __ store_fence();
}
void LIR_Assembler::membar_loadload() {

1434
hotspot/src/cpu/x86/vm/templateTable_x86_64.cpp → hotspot/src/cpu/x86/vm/templateTable_x86.cpp
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File diff suppressed because it is too large Load Diff

3668
hotspot/src/cpu/x86/vm/templateTable_x86_32.cpp
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File diff suppressed because it is too large Load Diff

28
hotspot/src/os/linux/vm/os_linux.cpp
View File

@ -227,31 +227,7 @@ bool os::have_special_privileges() {
#endif
// Cpu architecture string
#if defined(ZERO)
static char cpu_arch[] = ZERO_LIBARCH;
#elif defined(IA64)
static char cpu_arch[] = "ia64";
#elif defined(IA32)
static char cpu_arch[] = "i386";
#elif defined(AMD64)
static char cpu_arch[] = "amd64";
#elif defined(ARM)
static char cpu_arch[] = "arm";
#elif defined(PPC32)
static char cpu_arch[] = "ppc";
#elif defined(PPC64)
static char cpu_arch[] = "ppc64";
#elif defined(SPARC)
#ifdef _LP64
static char cpu_arch[] = "sparcv9";
#else
static char cpu_arch[] = "sparc";
#endif
#elif defined(AARCH64)
static char cpu_arch[] = "aarch64";
#else
#error Add appropriate cpu_arch setting
#endif
static char cpu_arch[] = HOTSPOT_LIB_ARCH;
// pid_t gettid()
@ -3296,7 +3272,7 @@ size_t os::Linux::find_large_page_size() {
#ifndef ZERO
large_page_size = IA32_ONLY(4 * M) AMD64_ONLY(2 * M) IA64_ONLY(256 * M) SPARC_ONLY(4 * M)
ARM_ONLY(2 * M) PPC_ONLY(4 * M) AARCH64_ONLY(2 * M);
ARM32_ONLY(2 * M) PPC_ONLY(4 * M) AARCH64_ONLY(2 * M);
#endif // ZERO
FILE *fp = fopen("/proc/meminfo", "r");

4
hotspot/src/os/solaris/vm/jvm_solaris.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1998, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -41,7 +41,9 @@
* JNI conversion, which should be sorted out later.
*/
#define __USE_LEGACY_PROTOTYPES__
#include <dirent.h> /* For DIR */
#undef __USE_LEGACY_PROTOTYPES__
#include <sys/param.h> /* For MAXPATHLEN */
#include <sys/socket.h> /* For socklen_t */
#include <unistd.h> /* For F_OK, R_OK, W_OK */

87
hotspot/src/os_cpu/aix_ppc/vm/orderAccess_aix_ppc.inline.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2014, SAP AG. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -28,6 +28,9 @@
#include "runtime/orderAccess.hpp"
// Compiler version last used for testing: xlc 12
// Please update this information when this file changes
// Implementation of class OrderAccess.
//
@ -61,86 +64,30 @@
#define inlasm_lwsync() __asm__ __volatile__ ("lwsync" : : : "memory");
#define inlasm_eieio() __asm__ __volatile__ ("eieio" : : : "memory");
#define inlasm_isync() __asm__ __volatile__ ("isync" : : : "memory");
#define inlasm_release() inlasm_lwsync();
#define inlasm_acquire() inlasm_lwsync();
// Use twi-isync for load_acquire (faster than lwsync).
// ATTENTION: seems like xlC 10.1 has problems with this inline assembler macro (VerifyMethodHandles found "bad vminfo in AMH.conv"):
// #define inlasm_acquire_reg(X) __asm__ __volatile__ ("twi 0,%0,0\n isync\n" : : "r" (X) : "memory");
#define inlasm_acquire_reg(X) inlasm_lwsync();
#define inlasm_fence() inlasm_sync();
inline void OrderAccess::loadload() { inlasm_lwsync(); }
inline void OrderAccess::storestore() { inlasm_lwsync(); }
inline void OrderAccess::loadstore() { inlasm_lwsync(); }
inline void OrderAccess::storeload() { inlasm_fence(); }
inline void OrderAccess::loadload() { inlasm_lwsync(); }
inline void OrderAccess::storestore() { inlasm_lwsync(); }
inline void OrderAccess::loadstore() { inlasm_lwsync(); }
inline void OrderAccess::storeload() { inlasm_sync(); }
inline void OrderAccess::acquire() { inlasm_acquire(); }
inline void OrderAccess::release() { inlasm_release(); }
inline void OrderAccess::fence() { inlasm_fence(); }
inline void OrderAccess::acquire() { inlasm_lwsync(); }
inline void OrderAccess::release() { inlasm_lwsync(); }
inline void OrderAccess::fence() { inlasm_sync(); }
inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { register jbyte t = *p; inlasm_acquire_reg(t); return t; }
inline jshort OrderAccess::load_acquire(volatile jshort* p) { register jshort t = *p; inlasm_acquire_reg(t); return t; }
inline jint OrderAccess::load_acquire(volatile jint* p) { register jint t = *p; inlasm_acquire_reg(t); return t; }
inline jlong OrderAccess::load_acquire(volatile jlong* p) { register jlong t = *p; inlasm_acquire_reg(t); return t; }
inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { register jubyte t = *p; inlasm_acquire_reg(t); return t; }
inline jushort OrderAccess::load_acquire(volatile jushort* p) { register jushort t = *p; inlasm_acquire_reg(t); return t; }
inline juint OrderAccess::load_acquire(volatile juint* p) { register juint t = *p; inlasm_acquire_reg(t); return t; }
inline julong OrderAccess::load_acquire(volatile julong* p) { return (julong)load_acquire((volatile jlong*)p); }
inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { register jfloat t = *p; inlasm_acquire(); return t; }
inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { register jdouble t = *p; inlasm_acquire(); return t; }
inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { return (intptr_t)load_acquire((volatile jlong*)p); }
inline void* OrderAccess::load_ptr_acquire(volatile void* p) { return (void*) load_acquire((volatile jlong*)p); }
inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { return (void*) load_acquire((volatile jlong*)p); }
inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store(volatile jshort* p, jshort v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store(volatile jint* p, jint v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store(volatile jlong* p, jlong v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store(volatile jushort* p, jushort v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store(volatile juint* p, juint v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store(volatile julong* p, julong v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { inlasm_release(); *(void* volatile *)p = v; }
inline void OrderAccess::store_fence(jbyte* p, jbyte v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_fence(jshort* p, jshort v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_fence(jint* p, jint v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_fence(jlong* p, jlong v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_fence(jubyte* p, jubyte v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_fence(jushort* p, jushort v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_fence(juint* p, juint v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_fence(julong* p, julong v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_fence(jdouble* p, jdouble v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_ptr_fence(void** p, void* v) { *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_fence(volatile jint* p, jint v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) { inlasm_release(); *(void* volatile *)p = v; inlasm_fence(); }
template<> inline jbyte OrderAccess::specialized_load_acquire<jbyte> (volatile jbyte* p) { register jbyte t = load(p); inlasm_acquire_reg(t); return t; }
template<> inline jshort OrderAccess::specialized_load_acquire<jshort>(volatile jshort* p) { register jshort t = load(p); inlasm_acquire_reg(t); return t; }
template<> inline jint OrderAccess::specialized_load_acquire<jint> (volatile jint* p) { register jint t = load(p); inlasm_acquire_reg(t); return t; }
template<> inline jlong OrderAccess::specialized_load_acquire<jlong> (volatile jlong* p) { register jlong t = load(p); inlasm_acquire_reg(t); return t; }
#undef inlasm_sync
#undef inlasm_lwsync
#undef inlasm_eieio
#undef inlasm_isync
#undef inlasm_release
#undef inlasm_acquire
#undef inlasm_fence
#define VM_HAS_GENERALIZED_ORDER_ACCESS 1
#endif // OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP

182
hotspot/src/os_cpu/bsd_x86/vm/orderAccess_bsd_x86.inline.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -29,27 +29,27 @@
#include "runtime/orderAccess.hpp"
#include "runtime/os.hpp"
// Compiler version last used for testing: clang 5.1
// Please update this information when this file changes
// A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions
static inline void compiler_barrier() {
__asm__ volatile ("" : : : "memory");
}
// x86 is TSO and hence only needs a fence for storeload
// However, a compiler barrier is still needed to prevent reordering
// between volatile and non-volatile memory accesses.
// Implementation of class OrderAccess.
inline void OrderAccess::loadload() { acquire(); }
inline void OrderAccess::storestore() { release(); }
inline void OrderAccess::loadstore() { acquire(); }
inline void OrderAccess::storeload() { fence(); }
inline void OrderAccess::loadload() { compiler_barrier(); }
inline void OrderAccess::storestore() { compiler_barrier(); }
inline void OrderAccess::loadstore() { compiler_barrier(); }
inline void OrderAccess::storeload() { fence(); }
inline void OrderAccess::acquire() {
volatile intptr_t local_dummy;
#ifdef AMD64
__asm__ volatile ("movq 0(%%rsp), %0" : "=r" (local_dummy) : : "memory");
#else
__asm__ volatile ("movl 0(%%esp),%0" : "=r" (local_dummy) : : "memory");
#endif // AMD64
}
inline void OrderAccess::release() {
// Avoid hitting the same cache-line from
// different threads.
volatile jint local_dummy = 0;
}
inline void OrderAccess::acquire() { compiler_barrier(); }
inline void OrderAccess::release() { compiler_barrier(); }
inline void OrderAccess::fence() {
if (os::is_MP()) {
@ -60,156 +60,50 @@ inline void OrderAccess::fence() {
__asm__ volatile ("lock; addl $0,0(%%esp)" : : : "cc", "memory");
#endif
}
compiler_barrier();
}
inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { return *p; }
inline jshort OrderAccess::load_acquire(volatile jshort* p) { return *p; }
inline jint OrderAccess::load_acquire(volatile jint* p) { return *p; }
inline jlong OrderAccess::load_acquire(volatile jlong* p) { return Atomic::load(p); }
inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { return *p; }
inline jushort OrderAccess::load_acquire(volatile jushort* p) { return *p; }
inline juint OrderAccess::load_acquire(volatile juint* p) { return *p; }
inline julong OrderAccess::load_acquire(volatile julong* p) { return Atomic::load((volatile jlong*)p); }
inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { return *p; }
inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { return jdouble_cast(Atomic::load((volatile jlong*)p)); }
inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { return *p; }
inline void* OrderAccess::load_ptr_acquire(volatile void* p) { return *(void* volatile *)p; }
inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { return *(void* const volatile *)p; }
inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { *p = v; }
inline void OrderAccess::release_store(volatile jshort* p, jshort v) { *p = v; }
inline void OrderAccess::release_store(volatile jint* p, jint v) { *p = v; }
inline void OrderAccess::release_store(volatile jlong* p, jlong v) { Atomic::store(v, p); }
inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { *p = v; }
inline void OrderAccess::release_store(volatile jushort* p, jushort v) { *p = v; }
inline void OrderAccess::release_store(volatile juint* p, juint v) { *p = v; }
inline void OrderAccess::release_store(volatile julong* p, julong v) { Atomic::store((jlong)v, (volatile jlong*)p); }
inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { *p = v; }
inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { release_store((volatile jlong*)p, jlong_cast(v)); }
inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { *p = v; }
inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { *(void* volatile *)p = v; }
inline void OrderAccess::store_fence(jbyte* p, jbyte v) {
template<>
inline void OrderAccess::specialized_release_store_fence<jbyte> (volatile jbyte* p, jbyte v) {
__asm__ volatile ( "xchgb (%2),%0"
: "=q" (v)
: "0" (v), "r" (p)
: "memory");
}
inline void OrderAccess::store_fence(jshort* p, jshort v) {
template<>
inline void OrderAccess::specialized_release_store_fence<jshort>(volatile jshort* p, jshort v) {
__asm__ volatile ( "xchgw (%2),%0"
: "=r" (v)
: "0" (v), "r" (p)
: "memory");
}
inline void OrderAccess::store_fence(jint* p, jint v) {
template<>
inline void OrderAccess::specialized_release_store_fence<jint> (volatile jint* p, jint v) {
__asm__ volatile ( "xchgl (%2),%0"
: "=r" (v)
: "0" (v), "r" (p)
: "memory");
}
inline void OrderAccess::store_fence(jlong* p, jlong v) {
#ifdef AMD64
__asm__ __volatile__ ("xchgq (%2), %0"
: "=r" (v)
: "0" (v), "r" (p)
: "memory");
#else
*p = v; fence();
#endif // AMD64
}
// AMD64 copied the bodies for the the signed version. 32bit did this. As long as the
// compiler does the inlining this is simpler.
inline void OrderAccess::store_fence(jubyte* p, jubyte v) { store_fence((jbyte*)p, (jbyte)v); }
inline void OrderAccess::store_fence(jushort* p, jushort v) { store_fence((jshort*)p, (jshort)v); }
inline void OrderAccess::store_fence(juint* p, juint v) { store_fence((jint*)p, (jint)v); }
inline void OrderAccess::store_fence(julong* p, julong v) { store_fence((jlong*)p, (jlong)v); }
inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jdouble* p, jdouble v) { *p = v; fence(); }
inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) {
#ifdef AMD64
__asm__ __volatile__ ("xchgq (%2), %0"
: "=r" (v)
: "0" (v), "r" (p)
: "memory");
#else
store_fence((jint*)p, (jint)v);
#endif // AMD64
}
inline void OrderAccess::store_ptr_fence(void** p, void* v) {
#ifdef AMD64
__asm__ __volatile__ ("xchgq (%2), %0"
: "=r" (v)
: "0" (v), "r" (p)
: "memory");
#else
store_fence((jint*)p, (jint)v);
#endif // AMD64
}
// Must duplicate definitions instead of calling store_fence because we don't want to cast away volatile.
inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) {
__asm__ volatile ( "xchgb (%2),%0"
: "=q" (v)
: "0" (v), "r" (p)
: "memory");
}
inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) {
__asm__ volatile ( "xchgw (%2),%0"
template<>
inline void OrderAccess::specialized_release_store_fence<jlong> (volatile jlong* p, jlong v) {
__asm__ volatile ( "xchgq (%2), %0"
: "=r" (v)
: "0" (v), "r" (p)
: "memory");
}
inline void OrderAccess::release_store_fence(volatile jint* p, jint v) {
__asm__ volatile ( "xchgl (%2),%0"
: "=r" (v)
: "0" (v), "r" (p)
: "memory");
}
inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) {
#ifdef AMD64
__asm__ __volatile__ ( "xchgq (%2), %0"
: "=r" (v)
: "0" (v), "r" (p)
: "memory");
#else
release_store(p, v); fence();
#endif // AMD64
template<>
inline void OrderAccess::specialized_release_store_fence<jfloat> (volatile jfloat* p, jfloat v) {
release_store_fence((volatile jint*)p, jint_cast(v));
}
template<>
inline void OrderAccess::specialized_release_store_fence<jdouble>(volatile jdouble* p, jdouble v) {
release_store_fence((volatile jlong*)p, jlong_cast(v));
}
inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { release_store_fence((volatile jbyte*)p, (jbyte)v); }
inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { release_store_fence((volatile jshort*)p, (jshort)v); }
inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { release_store_fence((volatile jint*)p, (jint)v); }
inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { release_store_fence((volatile jlong*)p, (jlong)v); }
inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { release_store_fence((volatile jlong*)p, jlong_cast(v)); }
inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) {
#ifdef AMD64
__asm__ __volatile__ ( "xchgq (%2), %0"
: "=r" (v)
: "0" (v), "r" (p)
: "memory");
#else
release_store_fence((volatile jint*)p, (jint)v);
#endif // AMD64
}
inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) {
#ifdef AMD64
__asm__ __volatile__ ( "xchgq (%2), %0"
: "=r" (v)
: "0" (v), "r" (p)
: "memory");
#else
release_store_fence((volatile jint*)p, (jint)v);
#endif // AMD64
}
#define VM_HAS_GENERALIZED_ORDER_ACCESS 1
#endif // OS_CPU_BSD_X86_VM_ORDERACCESS_BSD_X86_INLINE_HPP

126
hotspot/src/os_cpu/bsd_zero/vm/orderAccess_bsd_zero.inline.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
* Copyright 2007, 2008, 2009 Red Hat, Inc.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -40,8 +40,7 @@ typedef void (__kernel_dmb_t) (void);
#define __kernel_dmb (*(__kernel_dmb_t *) 0xffff0fa0)
#define FULL_MEM_BARRIER __kernel_dmb()
#define READ_MEM_BARRIER __kernel_dmb()
#define WRITE_MEM_BARRIER __kernel_dmb()
#define LIGHT_MEM_BARRIER __kernel_dmb()
#else // ARM
@ -50,126 +49,31 @@ typedef void (__kernel_dmb_t) (void);
#ifdef PPC
#ifdef __NO_LWSYNC__
#define READ_MEM_BARRIER __asm __volatile ("sync":::"memory")
#define WRITE_MEM_BARRIER __asm __volatile ("sync":::"memory")
#define LIGHT_MEM_BARRIER __asm __volatile ("sync":::"memory")
#else
#define READ_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
#define WRITE_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
#define LIGHT_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
#endif
#else // PPC
#define READ_MEM_BARRIER __asm __volatile ("":::"memory")
#define WRITE_MEM_BARRIER __asm __volatile ("":::"memory")
#define LIGHT_MEM_BARRIER __asm __volatile ("":::"memory")
#endif // PPC
#endif // ARM
// Note: What is meant by LIGHT_MEM_BARRIER is a barrier which is sufficient
// to provide TSO semantics, i.e. StoreStore | LoadLoad | LoadStore.
inline void OrderAccess::loadload() { acquire(); }
inline void OrderAccess::storestore() { release(); }
inline void OrderAccess::loadstore() { acquire(); }
inline void OrderAccess::storeload() { fence(); }
inline void OrderAccess::loadload() { LIGHT_MEM_BARRIER; }
inline void OrderAccess::storestore() { LIGHT_MEM_BARRIER; }
inline void OrderAccess::loadstore() { LIGHT_MEM_BARRIER; }
inline void OrderAccess::storeload() { FULL_MEM_BARRIER; }
inline void OrderAccess::acquire() {
READ_MEM_BARRIER;
}
inline void OrderAccess::acquire() { LIGHT_MEM_BARRIER; }
inline void OrderAccess::release() { LIGHT_MEM_BARRIER; }
inline void OrderAccess::fence() { FULL_MEM_BARRIER; }
inline void OrderAccess::release() {
WRITE_MEM_BARRIER;
}
inline void OrderAccess::fence() {
FULL_MEM_BARRIER;
}
inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { jbyte data = *p; acquire(); return data; }
inline jshort OrderAccess::load_acquire(volatile jshort* p) { jshort data = *p; acquire(); return data; }
inline jint OrderAccess::load_acquire(volatile jint* p) { jint data = *p; acquire(); return data; }
inline jlong OrderAccess::load_acquire(volatile jlong* p) {
jlong tmp;
os::atomic_copy64(p, &tmp);
acquire();
return tmp;
}
inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { jubyte data = *p; acquire(); return data; }
inline jushort OrderAccess::load_acquire(volatile jushort* p) { jushort data = *p; acquire(); return data; }
inline juint OrderAccess::load_acquire(volatile juint* p) { juint data = *p; acquire(); return data; }
inline julong OrderAccess::load_acquire(volatile julong* p) {
julong tmp;
os::atomic_copy64(p, &tmp);
acquire();
return tmp;
}
inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { jfloat data = *p; acquire(); return data; }
inline jdouble OrderAccess::load_acquire(volatile jdouble* p) {
jdouble tmp;
os::atomic_copy64(p, &tmp);
acquire();
return tmp;
}
inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) {
intptr_t data = *p;
acquire();
return data;
}
inline void* OrderAccess::load_ptr_acquire(volatile void* p) {
void *data = *(void* volatile *)p;
acquire();
return data;
}
inline void* OrderAccess::load_ptr_acquire(const volatile void* p) {
void *data = *(void* const volatile *)p;
acquire();
return data;
}
inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { release(); *p = v; }
inline void OrderAccess::release_store(volatile jshort* p, jshort v) { release(); *p = v; }
inline void OrderAccess::release_store(volatile jint* p, jint v) { release(); *p = v; }
inline void OrderAccess::release_store(volatile jlong* p, jlong v)
{ release(); os::atomic_copy64(&v, p); }
inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { release(); *p = v; }
inline void OrderAccess::release_store(volatile jushort* p, jushort v) { release(); *p = v; }
inline void OrderAccess::release_store(volatile juint* p, juint v) { release(); *p = v; }
inline void OrderAccess::release_store(volatile julong* p, julong v)
{ release(); os::atomic_copy64(&v, p); }
inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { release(); *p = v; }
inline void OrderAccess::release_store(volatile jdouble* p, jdouble v)
{ release(); os::atomic_copy64(&v, p); }
inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { release(); *p = v; }
inline void OrderAccess::release_store_ptr(volatile void* p, void* v)
{ release(); *(void* volatile *)p = v; }
inline void OrderAccess::store_fence(jbyte* p, jbyte v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jshort* p, jshort v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jint* p, jint v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jlong* p, jlong v) { os::atomic_copy64(&v, p); fence(); }
inline void OrderAccess::store_fence(jubyte* p, jubyte v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jushort* p, jushort v) { *p = v; fence(); }
inline void OrderAccess::store_fence(juint* p, juint v) { *p = v; fence(); }
inline void OrderAccess::store_fence(julong* p, julong v) { os::atomic_copy64(&v, p); fence(); }
inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jdouble* p, jdouble v) { os::atomic_copy64(&v, p); fence(); }
inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) { *p = v; fence(); }
inline void OrderAccess::store_ptr_fence(void** p, void* v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile jint* p, jint v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) { release_store_ptr(p, v); fence(); }
inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) { release_store_ptr(p, v); fence(); }
#define VM_HAS_GENERALIZED_ORDER_ACCESS 1
#endif // OS_CPU_BSD_ZERO_VM_ORDERACCESS_BSD_ZERO_INLINE_HPP

88
hotspot/src/os_cpu/linux_ppc/vm/orderAccess_linux_ppc.inline.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2014, SAP AG. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -32,6 +32,9 @@
#error "OrderAccess currently only implemented for PPC64"
#endif
// Compiler version last used for testing: gcc 4.1.2
// Please update this information when this file changes
// Implementation of class OrderAccess.
//
@ -65,84 +68,29 @@
#define inlasm_lwsync() __asm__ __volatile__ ("lwsync" : : : "memory");
#define inlasm_eieio() __asm__ __volatile__ ("eieio" : : : "memory");
#define inlasm_isync() __asm__ __volatile__ ("isync" : : : "memory");
#define inlasm_release() inlasm_lwsync();
#define inlasm_acquire() inlasm_lwsync();
// Use twi-isync for load_acquire (faster than lwsync).
#define inlasm_acquire_reg(X) __asm__ __volatile__ ("twi 0,%0,0\n isync\n" : : "r" (X) : "memory");
#define inlasm_fence() inlasm_sync();
inline void OrderAccess::loadload() { inlasm_lwsync(); }
inline void OrderAccess::storestore() { inlasm_lwsync(); }
inline void OrderAccess::loadstore() { inlasm_lwsync(); }
inline void OrderAccess::storeload() { inlasm_fence(); }
inline void OrderAccess::loadload() { inlasm_lwsync(); }
inline void OrderAccess::storestore() { inlasm_lwsync(); }
inline void OrderAccess::loadstore() { inlasm_lwsync(); }
inline void OrderAccess::storeload() { inlasm_sync(); }
inline void OrderAccess::acquire() { inlasm_acquire(); }
inline void OrderAccess::release() { inlasm_release(); }
inline void OrderAccess::fence() { inlasm_fence(); }
inline void OrderAccess::acquire() { inlasm_lwsync(); }
inline void OrderAccess::release() { inlasm_lwsync(); }
inline void OrderAccess::fence() { inlasm_sync(); }
inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { register jbyte t = *p; inlasm_acquire_reg(t); return t; }
inline jshort OrderAccess::load_acquire(volatile jshort* p) { register jshort t = *p; inlasm_acquire_reg(t); return t; }
inline jint OrderAccess::load_acquire(volatile jint* p) { register jint t = *p; inlasm_acquire_reg(t); return t; }
inline jlong OrderAccess::load_acquire(volatile jlong* p) { register jlong t = *p; inlasm_acquire_reg(t); return t; }
inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { register jubyte t = *p; inlasm_acquire_reg(t); return t; }
inline jushort OrderAccess::load_acquire(volatile jushort* p) { register jushort t = *p; inlasm_acquire_reg(t); return t; }
inline juint OrderAccess::load_acquire(volatile juint* p) { register juint t = *p; inlasm_acquire_reg(t); return t; }
inline julong OrderAccess::load_acquire(volatile julong* p) { return (julong)load_acquire((volatile jlong*)p); }
inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { register jfloat t = *p; inlasm_acquire(); return t; }
inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { register jdouble t = *p; inlasm_acquire(); return t; }
inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { return (intptr_t)load_acquire((volatile jlong*)p); }
inline void* OrderAccess::load_ptr_acquire(volatile void* p) { return (void*) load_acquire((volatile jlong*)p); }
inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { return (void*) load_acquire((volatile jlong*)p); }
inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store(volatile jshort* p, jshort v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store(volatile jint* p, jint v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store(volatile jlong* p, jlong v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store(volatile jushort* p, jushort v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store(volatile juint* p, juint v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store(volatile julong* p, julong v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { inlasm_release(); *p = v; }
inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { inlasm_release(); *(void* volatile *)p = v; }
inline void OrderAccess::store_fence(jbyte* p, jbyte v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_fence(jshort* p, jshort v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_fence(jint* p, jint v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_fence(jlong* p, jlong v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_fence(jubyte* p, jubyte v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_fence(jushort* p, jushort v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_fence(juint* p, juint v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_fence(julong* p, julong v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_fence(jdouble* p, jdouble v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) { *p = v; inlasm_fence(); }
inline void OrderAccess::store_ptr_fence(void** p, void* v) { *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_fence(volatile jint* p, jint v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) { inlasm_release(); *p = v; inlasm_fence(); }
inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) { inlasm_release(); *(void* volatile *)p = v; inlasm_fence(); }
template<> inline jbyte OrderAccess::specialized_load_acquire<jbyte> (volatile jbyte* p) { register jbyte t = load(p); inlasm_acquire_reg(t); return t; }
template<> inline jshort OrderAccess::specialized_load_acquire<jshort>(volatile jshort* p) { register jshort t = load(p); inlasm_acquire_reg(t); return t; }
template<> inline jint OrderAccess::specialized_load_acquire<jint> (volatile jint* p) { register jint t = load(p); inlasm_acquire_reg(t); return t; }
template<> inline jlong OrderAccess::specialized_load_acquire<jlong> (volatile jlong* p) { register jlong t = load(p); inlasm_acquire_reg(t); return t; }
#undef inlasm_sync
#undef inlasm_lwsync
#undef inlasm_eieio
#undef inlasm_isync
#undef inlasm_release
#undef inlasm_acquire
#undef inlasm_fence
#undef inlasm_acquire_reg
#define VM_HAS_GENERALIZED_ORDER_ACCESS 1
#endif // OS_CPU_LINUX_PPC_VM_ORDERACCESS_LINUX_PPC_INLINE_HPP

84
hotspot/src/os_cpu/linux_sparc/vm/orderAccess_linux_sparc.inline.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -29,81 +29,25 @@
// Implementation of class OrderAccess.
// A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions
static inline void compiler_barrier() {
__asm__ volatile ("" : : : "memory");
}
// Assume TSO.
inline void OrderAccess::loadload() { acquire(); }
inline void OrderAccess::storestore() { release(); }
inline void OrderAccess::loadstore() { acquire(); }
inline void OrderAccess::storeload() { fence(); }
inline void OrderAccess::loadload() { compiler_barrier(); }
inline void OrderAccess::storestore() { compiler_barrier(); }
inline void OrderAccess::loadstore() { compiler_barrier(); }
inline void OrderAccess::storeload() { fence(); }
inline void OrderAccess::acquire() {
__asm__ volatile ("nop" : : :);
}
inline void OrderAccess::release() {
jint* local_dummy = (jint*)&local_dummy;
__asm__ volatile("stw %%g0, [%0]" : : "r" (local_dummy) : "memory");
}
inline void OrderAccess::acquire() { compiler_barrier(); }
inline void OrderAccess::release() { compiler_barrier(); }
inline void OrderAccess::fence() {
__asm__ volatile ("membar #StoreLoad" : : :);
__asm__ volatile ("membar #StoreLoad" : : : "memory");
}
inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { return *p; }
inline jshort OrderAccess::load_acquire(volatile jshort* p) { return *p; }
inline jint OrderAccess::load_acquire(volatile jint* p) { return *p; }
inline jlong OrderAccess::load_acquire(volatile jlong* p) { return *p; }
inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { return *p; }
inline jushort OrderAccess::load_acquire(volatile jushort* p) { return *p; }
inline juint OrderAccess::load_acquire(volatile juint* p) { return *p; }
inline julong OrderAccess::load_acquire(volatile julong* p) { return *p; }
inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { return *p; }
inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { return *p; }
inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { return *p; }
inline void* OrderAccess::load_ptr_acquire(volatile void* p) { return *(void* volatile *)p; }
inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { return *(void* const volatile *)p; }
inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { *p = v; }
inline void OrderAccess::release_store(volatile jshort* p, jshort v) { *p = v; }
inline void OrderAccess::release_store(volatile jint* p, jint v) { *p = v; }
inline void OrderAccess::release_store(volatile jlong* p, jlong v) { *p = v; }
inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { *p = v; }
inline void OrderAccess::release_store(volatile jushort* p, jushort v) { *p = v; }
inline void OrderAccess::release_store(volatile juint* p, juint v) { *p = v; }
inline void OrderAccess::release_store(volatile julong* p, julong v) { *p = v; }
inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { *p = v; }
inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { *p = v; }
inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { *p = v; }
inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { *(void* volatile *)p = v; }
inline void OrderAccess::store_fence(jbyte* p, jbyte v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jshort* p, jshort v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jint* p, jint v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jlong* p, jlong v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jubyte* p, jubyte v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jushort* p, jushort v) { *p = v; fence(); }
inline void OrderAccess::store_fence(juint* p, juint v) { *p = v; fence(); }
inline void OrderAccess::store_fence(julong* p, julong v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jdouble* p, jdouble v) { *p = v; fence(); }
inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) { *p = v; fence(); }
inline void OrderAccess::store_ptr_fence(void** p, void* v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jint* p, jint v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { *p = v; fence(); }
inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) { *p = v; fence(); }
inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) { *(void* volatile *)p = v; fence(); }
#define VM_HAS_GENERALIZED_ORDER_ACCESS 1
#endif // OS_CPU_LINUX_SPARC_VM_ORDERACCESS_LINUX_SPARC_INLINE_HPP

171
hotspot/src/os_cpu/linux_x86/vm/orderAccess_linux_x86.inline.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -29,6 +29,9 @@
#include "runtime/orderAccess.hpp"
#include "runtime/os.hpp"
// Compiler version last used for testing: gcc 4.8.2
// Please update this information when this file changes
// Implementation of class OrderAccess.
// A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions
@ -36,23 +39,13 @@ static inline void compiler_barrier() {
__asm__ volatile ("" : : : "memory");
}
inline void OrderAccess::loadload() { acquire(); }
inline void OrderAccess::storestore() { release(); }
inline void OrderAccess::loadstore() { acquire(); }
inline void OrderAccess::storeload() { fence(); }
inline void OrderAccess::loadload() { compiler_barrier(); }
inline void OrderAccess::storestore() { compiler_barrier(); }
inline void OrderAccess::loadstore() { compiler_barrier(); }
inline void OrderAccess::storeload() { fence(); }
inline void OrderAccess::acquire() {
volatile intptr_t local_dummy;
#ifdef AMD64
__asm__ volatile ("movq 0(%%rsp), %0" : "=r" (local_dummy) : : "memory");
#else
__asm__ volatile ("movl 0(%%esp),%0" : "=r" (local_dummy) : : "memory");
#endif // AMD64
}
inline void OrderAccess::release() {
compiler_barrier();
}
inline void OrderAccess::acquire() { compiler_barrier(); }
inline void OrderAccess::release() { compiler_barrier(); }
inline void OrderAccess::fence() {
if (os::is_MP()) {
@ -63,156 +56,50 @@ inline void OrderAccess::fence() {
__asm__ volatile ("lock; addl $0,0(%%esp)" : : : "cc", "memory");
#endif
}
compiler_barrier();
}
inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { jbyte v = *p; compiler_barrier(); return v; }
inline jshort OrderAccess::load_acquire(volatile jshort* p) { jshort v = *p; compiler_barrier(); return v; }
inline jint OrderAccess::load_acquire(volatile jint* p) { jint v = *p; compiler_barrier(); return v; }
inline jlong OrderAccess::load_acquire(volatile jlong* p) { jlong v = Atomic::load(p); compiler_barrier(); return v; }
inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { jubyte v = *p; compiler_barrier(); return v; }
inline jushort OrderAccess::load_acquire(volatile jushort* p) { jushort v = *p; compiler_barrier(); return v; }
inline juint OrderAccess::load_acquire(volatile juint* p) { juint v = *p; compiler_barrier(); return v; }
inline julong OrderAccess::load_acquire(volatile julong* p) { julong v = Atomic::load((volatile jlong*)p); compiler_barrier(); return v; }
inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { jfloat v = *p; compiler_barrier(); return v; }
inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { jdouble v = jdouble_cast(Atomic::load((volatile jlong*)p)); compiler_barrier(); return v; }
inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { intptr_t v = *p; compiler_barrier(); return v; }
inline void* OrderAccess::load_ptr_acquire(volatile void* p) { void* v = *(void* volatile *)p; compiler_barrier(); return v; }
inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { void* v = *(void* const volatile *)p; compiler_barrier(); return v; }
inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { compiler_barrier(); *p = v; }
inline void OrderAccess::release_store(volatile jshort* p, jshort v) { compiler_barrier(); *p = v; }
inline void OrderAccess::release_store(volatile jint* p, jint v) { compiler_barrier(); *p = v; }
inline void OrderAccess::release_store(volatile jlong* p, jlong v) { compiler_barrier(); Atomic::store(v, p); }
inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { compiler_barrier(); *p = v; }
inline void OrderAccess::release_store(volatile jushort* p, jushort v) { compiler_barrier(); *p = v; }
inline void OrderAccess::release_store(volatile juint* p, juint v) { compiler_barrier(); *p = v; }
inline void OrderAccess::release_store(volatile julong* p, julong v) { compiler_barrier(); Atomic::store((jlong)v, (volatile jlong*)p); }
inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { compiler_barrier(); *p = v; }
inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { release_store((volatile jlong *)p, jlong_cast(v)); }
inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { compiler_barrier(); *p = v; }
inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { compiler_barrier(); *(void* volatile *)p = v; }
inline void OrderAccess::store_fence(jbyte* p, jbyte v) {
template<>
inline void OrderAccess::specialized_release_store_fence<jbyte> (volatile jbyte* p, jbyte v) {
__asm__ volatile ( "xchgb (%2),%0"
: "=q" (v)
: "0" (v), "r" (p)
: "memory");
}
inline void OrderAccess::store_fence(jshort* p, jshort v) {
template<>
inline void OrderAccess::specialized_release_store_fence<jshort>(volatile jshort* p, jshort v) {
__asm__ volatile ( "xchgw (%2),%0"
: "=r" (v)
: "0" (v), "r" (p)
: "memory");
}
inline void OrderAccess::store_fence(jint* p, jint v) {
template<>
inline void OrderAccess::specialized_release_store_fence<jint> (volatile jint* p, jint v) {
__asm__ volatile ( "xchgl (%2),%0"
: "=r" (v)
: "0" (v), "r" (p)
: "memory");
}
inline void OrderAccess::store_fence(jlong* p, jlong v) {
#ifdef AMD64
__asm__ __volatile__ ("xchgq (%2), %0"
: "=r" (v)
: "0" (v), "r" (p)
: "memory");
#else
*p = v; fence();
#endif // AMD64
}
// AMD64 copied the bodies for the the signed version. 32bit did this. As long as the
// compiler does the inlining this is simpler.
inline void OrderAccess::store_fence(jubyte* p, jubyte v) { store_fence((jbyte*)p, (jbyte)v); }
inline void OrderAccess::store_fence(jushort* p, jushort v) { store_fence((jshort*)p, (jshort)v); }
inline void OrderAccess::store_fence(juint* p, juint v) { store_fence((jint*)p, (jint)v); }
inline void OrderAccess::store_fence(julong* p, julong v) { store_fence((jlong*)p, (jlong)v); }
inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jdouble* p, jdouble v) { store_fence((jlong*)p, jlong_cast(v)); }
inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) {
#ifdef AMD64
__asm__ __volatile__ ("xchgq (%2), %0"
: "=r" (v)
: "0" (v), "r" (p)
: "memory");
#else
store_fence((jint*)p, (jint)v);
#endif // AMD64
}
inline void OrderAccess::store_ptr_fence(void** p, void* v) {
#ifdef AMD64
__asm__ __volatile__ ("xchgq (%2), %0"
: "=r" (v)
: "0" (v), "r" (p)
: "memory");
#else
store_fence((jint*)p, (jint)v);
#endif // AMD64
}
// Must duplicate definitions instead of calling store_fence because we don't want to cast away volatile.
inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) {
__asm__ volatile ( "xchgb (%2),%0"
: "=q" (v)
: "0" (v), "r" (p)
: "memory");
}
inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) {
__asm__ volatile ( "xchgw (%2),%0"
template<>
inline void OrderAccess::specialized_release_store_fence<jlong> (volatile jlong* p, jlong v) {
__asm__ volatile ( "xchgq (%2), %0"
: "=r" (v)
: "0" (v), "r" (p)
: "memory");
}
inline void OrderAccess::release_store_fence(volatile jint* p, jint v) {
__asm__ volatile ( "xchgl (%2),%0"
: "=r" (v)
: "0" (v), "r" (p)
: "memory");
}
inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) {
#ifdef AMD64
__asm__ __volatile__ ( "xchgq (%2), %0"
: "=r" (v)
: "0" (v), "r" (p)
: "memory");
#else
release_store(p, v); fence();
#endif // AMD64
template<>
inline void OrderAccess::specialized_release_store_fence<jfloat> (volatile jfloat* p, jfloat v) {
release_store_fence((volatile jint*)p, jint_cast(v));
}
template<>
inline void OrderAccess::specialized_release_store_fence<jdouble>(volatile jdouble* p, jdouble v) {
release_store_fence((volatile jlong*)p, jlong_cast(v));
}
inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { release_store_fence((volatile jbyte*)p, (jbyte)v); }
inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { release_store_fence((volatile jshort*)p, (jshort)v); }
inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { release_store_fence((volatile jint*)p, (jint)v); }
inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { release_store_fence((volatile jlong*)p, (jlong)v); }
inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { release_store_fence((volatile jlong*)p, jlong_cast(v)); }
inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) {
#ifdef AMD64
__asm__ __volatile__ ( "xchgq (%2), %0"
: "=r" (v)
: "0" (v), "r" (p)
: "memory");
#else
release_store_fence((volatile jint*)p, (jint)v);
#endif // AMD64
}
inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) {
#ifdef AMD64
__asm__ __volatile__ ( "xchgq (%2), %0"
: "=r" (v)
: "0" (v), "r" (p)
: "memory");
#else
release_store_fence((volatile jint*)p, (jint)v);
#endif // AMD64
}
#define VM_HAS_GENERALIZED_ORDER_ACCESS 1
#endif // OS_CPU_LINUX_X86_VM_ORDERACCESS_LINUX_X86_INLINE_HPP

124
hotspot/src/os_cpu/linux_zero/vm/orderAccess_linux_zero.inline.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
* Copyright 2007, 2008, 2009 Red Hat, Inc.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -40,8 +40,7 @@ typedef void (__kernel_dmb_t) (void);
#define __kernel_dmb (*(__kernel_dmb_t *) 0xffff0fa0)
#define FULL_MEM_BARRIER __kernel_dmb()
#define READ_MEM_BARRIER __kernel_dmb()
#define WRITE_MEM_BARRIER __kernel_dmb()
#define LIGHT_MEM_BARRIER __kernel_dmb()
#else // ARM
@ -49,126 +48,33 @@ typedef void (__kernel_dmb_t) (void);
#ifdef PPC
#define READ_MEM_BARRIER __asm __volatile ("isync":::"memory")
#ifdef __NO_LWSYNC__
#define WRITE_MEM_BARRIER __asm __volatile ("sync":::"memory")
#define LIGHT_MEM_BARRIER __asm __volatile ("sync":::"memory")
#else
#define WRITE_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
#define LIGHT_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
#endif
#else // PPC
#define READ_MEM_BARRIER __asm __volatile ("":::"memory")
#define WRITE_MEM_BARRIER __asm __volatile ("":::"memory")
#define LIGHT_MEM_BARRIER __asm __volatile ("":::"memory")
#endif // PPC
#endif // ARM
// Note: What is meant by LIGHT_MEM_BARRIER is a barrier which is sufficient
// to provide TSO semantics, i.e. StoreStore | LoadLoad | LoadStore.
inline void OrderAccess::loadload() { acquire(); }
inline void OrderAccess::storestore() { release(); }
inline void OrderAccess::loadstore() { acquire(); }
inline void OrderAccess::storeload() { fence(); }
inline void OrderAccess::loadload() { LIGHT_MEM_BARRIER; }
inline void OrderAccess::storestore() { LIGHT_MEM_BARRIER; }
inline void OrderAccess::loadstore() { LIGHT_MEM_BARRIER; }
inline void OrderAccess::storeload() { FULL_MEM_BARRIER; }
inline void OrderAccess::acquire() {
READ_MEM_BARRIER;
}
inline void OrderAccess::acquire() { LIGHT_MEM_BARRIER; }
inline void OrderAccess::release() { LIGHT_MEM_BARRIER; }
inline void OrderAccess::release() {
WRITE_MEM_BARRIER;
}
inline void OrderAccess::fence() { FULL_MEM_BARRIER; }
inline void OrderAccess::fence() {
FULL_MEM_BARRIER;
}
inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { jbyte data = *p; acquire(); return data; }
inline jshort OrderAccess::load_acquire(volatile jshort* p) { jshort data = *p; acquire(); return data; }
inline jint OrderAccess::load_acquire(volatile jint* p) { jint data = *p; acquire(); return data; }
inline jlong OrderAccess::load_acquire(volatile jlong* p) {
jlong tmp;
os::atomic_copy64(p, &tmp);
acquire();
return tmp;
}
inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { jubyte data = *p; acquire(); return data; }
inline jushort OrderAccess::load_acquire(volatile jushort* p) { jushort data = *p; acquire(); return data; }
inline juint OrderAccess::load_acquire(volatile juint* p) { juint data = *p; acquire(); return data; }
inline julong OrderAccess::load_acquire(volatile julong* p) {
julong tmp;
os::atomic_copy64(p, &tmp);
acquire();
return tmp;
}
inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { jfloat data = *p; acquire(); return data; }
inline jdouble OrderAccess::load_acquire(volatile jdouble* p) {
jdouble tmp;
os::atomic_copy64(p, &tmp);
acquire();
return tmp;
}
inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) {
intptr_t data = *p;
acquire();
return data;
}
inline void* OrderAccess::load_ptr_acquire(volatile void* p) {
void *data = *(void* volatile *)p;
acquire();
return data;
}
inline void* OrderAccess::load_ptr_acquire(const volatile void* p) {
void *data = *(void* const volatile *)p;
acquire();
return data;
}
inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { release(); *p = v; }
inline void OrderAccess::release_store(volatile jshort* p, jshort v) { release(); *p = v; }
inline void OrderAccess::release_store(volatile jint* p, jint v) { release(); *p = v; }
inline void OrderAccess::release_store(volatile jlong* p, jlong v)
{ release(); os::atomic_copy64(&v, p); }
inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { release(); *p = v; }
inline void OrderAccess::release_store(volatile jushort* p, jushort v) { release(); *p = v; }
inline void OrderAccess::release_store(volatile juint* p, juint v) { release(); *p = v; }
inline void OrderAccess::release_store(volatile julong* p, julong v)
{ release(); os::atomic_copy64(&v, p); }
inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { release(); *p = v; }
inline void OrderAccess::release_store(volatile jdouble* p, jdouble v)
{ release(); os::atomic_copy64(&v, p); }
inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { release(); *p = v; }
inline void OrderAccess::release_store_ptr(volatile void* p, void* v)
{ release(); *(void* volatile *)p = v; }
inline void OrderAccess::store_fence(jbyte* p, jbyte v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jshort* p, jshort v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jint* p, jint v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jlong* p, jlong v) { os::atomic_copy64(&v, p); fence(); }
inline void OrderAccess::store_fence(jubyte* p, jubyte v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jushort* p, jushort v) { *p = v; fence(); }
inline void OrderAccess::store_fence(juint* p, juint v) { *p = v; fence(); }
inline void OrderAccess::store_fence(julong* p, julong v) { os::atomic_copy64(&v, p); fence(); }
inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jdouble* p, jdouble v) { os::atomic_copy64(&v, p); fence(); }
inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) { *p = v; fence(); }
inline void OrderAccess::store_ptr_fence(void** p, void* v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile jint* p, jint v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) { release_store_ptr(p, v); fence(); }
inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) { release_store_ptr(p, v); fence(); }
#define VM_HAS_GENERALIZED_ORDER_ACCESS 1
#endif // OS_CPU_LINUX_ZERO_VM_ORDERACCESS_LINUX_ZERO_INLINE_HPP

109
hotspot/src/os_cpu/solaris_sparc/vm/orderAccess_solaris_sparc.inline.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -28,107 +28,30 @@
#include "runtime/atomic.inline.hpp"
#include "runtime/orderAccess.hpp"
// Compiler version last used for testing: solaris studio 12u3
// Please update this information when this file changes
// Implementation of class OrderAccess.
// Assume TSO.
// In solaris_sparc.il
extern "C" void _OrderAccess_acquire();
extern "C" void _OrderAccess_fence();
inline void OrderAccess::loadload() { acquire(); }
inline void OrderAccess::storestore() { release(); }
inline void OrderAccess::loadstore() { acquire(); }
inline void OrderAccess::storeload() { fence(); }
#ifdef _GNU_SOURCE
inline void OrderAccess::acquire() {
__asm__ volatile ("nop" : : :);
// A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions
inline void compiler_barrier() {
__asm__ volatile ("" : : : "memory");
}
inline void OrderAccess::release() {
jint* local_dummy = (jint*)&local_dummy;
__asm__ volatile("stw %%g0, [%0]" : : "r" (local_dummy) : "memory");
}
inline void OrderAccess::loadload() { compiler_barrier(); }
inline void OrderAccess::storestore() { compiler_barrier(); }
inline void OrderAccess::loadstore() { compiler_barrier(); }
inline void OrderAccess::storeload() { fence(); }
inline void OrderAccess::acquire() { compiler_barrier(); }
inline void OrderAccess::release() { compiler_barrier(); }
inline void OrderAccess::fence() {
__asm__ volatile ("membar #StoreLoad" : : :);
__asm__ volatile ("membar #StoreLoad" : : : "memory");
}
#else // _GNU_SOURCE
inline void OrderAccess::acquire() {
_OrderAccess_acquire();
}
inline void OrderAccess::release() {
// Avoid hitting the same cache-line from
// different threads.
volatile jint local_dummy = 0;
}
inline void OrderAccess::fence() {
_OrderAccess_fence();
}
#endif // _GNU_SOURCE
inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { return *p; }
inline jshort OrderAccess::load_acquire(volatile jshort* p) { return *p; }
inline jint OrderAccess::load_acquire(volatile jint* p) { return *p; }
inline jlong OrderAccess::load_acquire(volatile jlong* p) { return Atomic::load(p); }
inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { return *p; }
inline jushort OrderAccess::load_acquire(volatile jushort* p) { return *p; }
inline juint OrderAccess::load_acquire(volatile juint* p) { return *p; }
inline julong OrderAccess::load_acquire(volatile julong* p) { return Atomic::load((volatile jlong*)p); }
inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { return *p; }
inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { return *p; }
inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { return *p; }
inline void* OrderAccess::load_ptr_acquire(volatile void* p) { return *(void* volatile *)p; }
inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { return *(void* const volatile *)p; }
inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { *p = v; }
inline void OrderAccess::release_store(volatile jshort* p, jshort v) { *p = v; }
inline void OrderAccess::release_store(volatile jint* p, jint v) { *p = v; }
inline void OrderAccess::release_store(volatile jlong* p, jlong v) { Atomic::store(v, p); }
inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { *p = v; }
inline void OrderAccess::release_store(volatile jushort* p, jushort v) { *p = v; }
inline void OrderAccess::release_store(volatile juint* p, juint v) { *p = v; }
inline void OrderAccess::release_store(volatile julong* p, julong v) { Atomic::store((jlong)v, (volatile jlong*)p); }
inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { *p = v; }
inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { *p = v; }
inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { *p = v; }
inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { *(void* volatile *)p = v; }
inline void OrderAccess::store_fence(jbyte* p, jbyte v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jshort* p, jshort v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jint* p, jint v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jlong* p, jlong v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jubyte* p, jubyte v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jushort* p, jushort v) { *p = v; fence(); }
inline void OrderAccess::store_fence(juint* p, juint v) { *p = v; fence(); }
inline void OrderAccess::store_fence(julong* p, julong v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jdouble* p, jdouble v) { *p = v; fence(); }
inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) { *p = v; fence(); }
inline void OrderAccess::store_ptr_fence(void** p, void* v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jint* p, jint v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { *p = v; fence(); }
inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) { *p = v; fence(); }
inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) { *(void* volatile *)p = v; fence(); }
#define VM_HAS_GENERALIZED_ORDER_ACCESS 1
#endif // OS_CPU_SOLARIS_SPARC_VM_ORDERACCESS_SOLARIS_SPARC_INLINE_HPP

41
hotspot/src/os_cpu/solaris_sparc/vm/solaris_sparc.il
View File

@ -1,5 +1,5 @@
//
// Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2002, 2015, Oracle and/or its affiliates. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
@ -19,7 +19,7 @@
// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
// or visit www.oracle.com if you need additional information or have any
// questions.
//
//
//
// Get the raw thread ID from %g7
@ -35,11 +35,11 @@
// Clear SPARC fprs.FEF DU and DL bits --
// allows the kernel to avoid saving FPU state at context-switch time.
// Use for state-transition points (into _thread_blocked) or when
// parking.
// parking.
.inline _mark_fpu_nosave, 0
.volatile
wr %g0, 0, %fprs
wr %g0, 0, %fprs
.nonvolatile
.end
@ -85,7 +85,7 @@
// Support for jint Atomic::cmpxchg(jint exchange_value,
// volatile jint* dest,
// volatile jint* dest,
// jint compare_value)
//
// Arguments:
@ -103,8 +103,8 @@
.end
// Support for intptr_t Atomic::cmpxchg_ptr(intptr_t exchange_value,
// volatile intptr_t* dest,
// Support for intptr_t Atomic::cmpxchg_ptr(intptr_t exchange_value,
// volatile intptr_t* dest,
// intptr_t compare_value)
//
// 64-bit
@ -124,8 +124,8 @@
.end
// Support for jlong Atomic::cmpxchg(jlong exchange_value,
// volatile jlong* dest,
// Support for jlong Atomic::cmpxchg(jlong exchange_value,
// volatile jlong* dest,
// jlong compare_value)
//
// 32-bit calling conventions
@ -221,27 +221,6 @@
.end
// Support for void OrderAccess::acquire()
// The method is intentionally empty.
// It exists for the sole purpose of generating
// a C/C++ sequence point over which the compiler won't
// reorder code.
.inline _OrderAccess_acquire,0
.volatile
.nonvolatile
.end
// Support for void OrderAccess::fence()
.inline _OrderAccess_fence,0
.volatile
membar #StoreLoad
.nonvolatile
.end
// Support for void Prefetch::read(void *loc, intx interval)
//
// Prefetch for several reads.

111
hotspot/src/os_cpu/solaris_x86/vm/orderAccess_solaris_x86.inline.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -29,110 +29,35 @@
#include "runtime/orderAccess.hpp"
#include "runtime/os.hpp"
// Compiler version last used for testing: solaris studio 12u3
// Please update this information when this file changes
// Implementation of class OrderAccess.
// For Sun Studio - implementation is in solaris_i486.il.
// For gcc - implementation is just below.
extern "C" void _OrderAccess_acquire();
extern "C" void _OrderAccess_fence();
inline void OrderAccess::loadload() { acquire(); }
inline void OrderAccess::storestore() { release(); }
inline void OrderAccess::loadstore() { acquire(); }
inline void OrderAccess::storeload() { fence(); }
inline void OrderAccess::acquire() {
_OrderAccess_acquire();
// A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions
inline void compiler_barrier() {
__asm__ volatile ("" : : : "memory");
}
inline void OrderAccess::release() {
// Avoid hitting the same cache-line from
// different threads.
volatile jint local_dummy = 0;
}
inline void OrderAccess::loadload() { compiler_barrier(); }
inline void OrderAccess::storestore() { compiler_barrier(); }
inline void OrderAccess::loadstore() { compiler_barrier(); }
inline void OrderAccess::storeload() { fence(); }
inline void OrderAccess::acquire() { compiler_barrier(); }
inline void OrderAccess::release() { compiler_barrier(); }
inline void OrderAccess::fence() {
if (os::is_MP()) {
_OrderAccess_fence();
}
}
#ifdef _GNU_SOURCE
extern "C" {
inline void _OrderAccess_acquire() {
volatile intptr_t local_dummy;
#ifdef AMD64
__asm__ volatile ("movq 0(%%rsp), %0" : "=r" (local_dummy) : : "memory");
__asm__ volatile ("lock; addl $0,0(%%rsp)" : : : "cc", "memory");
#else
__asm__ volatile ("movl 0(%%esp),%0" : "=r" (local_dummy) : : "memory");
#endif // AMD64
}
inline void _OrderAccess_fence() {
// Always use locked addl since mfence is sometimes expensive
__asm__ volatile ("lock; addl $0,0(%%esp)" : : : "cc", "memory");
#endif
}
compiler_barrier();
}
#endif // GNU_SOURCE
inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { return *p; }
inline jshort OrderAccess::load_acquire(volatile jshort* p) { return *p; }
inline jint OrderAccess::load_acquire(volatile jint* p) { return *p; }
inline jlong OrderAccess::load_acquire(volatile jlong* p) { return Atomic::load(p); }
inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { return *p; }
inline jushort OrderAccess::load_acquire(volatile jushort* p) { return *p; }
inline juint OrderAccess::load_acquire(volatile juint* p) { return *p; }
inline julong OrderAccess::load_acquire(volatile julong* p) { return Atomic::load((volatile jlong*)p); }
inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { return *p; }
inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { return jdouble_cast(Atomic::load((volatile jlong*)p)); }
inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { return *p; }
inline void* OrderAccess::load_ptr_acquire(volatile void* p) { return *(void* volatile *)p; }
inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { return *(void* const volatile *)p; }
inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { *p = v; }
inline void OrderAccess::release_store(volatile jshort* p, jshort v) { *p = v; }
inline void OrderAccess::release_store(volatile jint* p, jint v) { *p = v; }
inline void OrderAccess::release_store(volatile jlong* p, jlong v) { Atomic::store(v, p); }
inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { *p = v; }
inline void OrderAccess::release_store(volatile jushort* p, jushort v) { *p = v; }
inline void OrderAccess::release_store(volatile juint* p, juint v) { *p = v; }
inline void OrderAccess::release_store(volatile julong* p, julong v) { Atomic::store((jlong)v, (volatile jlong*)p); }
inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { *p = v; }
inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { release_store((volatile jlong*)p, jlong_cast(v)); }
inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { *p = v; }
inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { *(void* volatile *)p = v; }
inline void OrderAccess::store_fence(jbyte* p, jbyte v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jshort* p, jshort v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jint* p, jint v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jlong* p, jlong v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jubyte* p, jubyte v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jushort* p, jushort v) { *p = v; fence(); }
inline void OrderAccess::store_fence(juint* p, juint v) { *p = v; fence(); }
inline void OrderAccess::store_fence(julong* p, julong v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jdouble* p, jdouble v) { *p = v; fence(); }
inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) { *p = v; fence(); }
inline void OrderAccess::store_ptr_fence(void** p, void* v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jint* p, jint v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { release_store((jlong *)p, (jlong)v); fence(); }
inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { release_store_fence((volatile jlong*)p, jlong_cast(v)); }
inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) { *p = v; fence(); }
inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) { *(void* volatile *)p = v; fence(); }
#define VM_HAS_GENERALIZED_ORDER_ACCESS 1
#endif // OS_CPU_SOLARIS_X86_VM_ORDERACCESS_SOLARIS_X86_INLINE_HPP

29
hotspot/src/os_cpu/solaris_x86/vm/solaris_x86_32.il
View File

@ -1,5 +1,5 @@
//
// Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
@ -19,7 +19,7 @@
// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
// or visit www.oracle.com if you need additional information or have any
// questions.
//
//
//
@ -34,19 +34,19 @@
// Get the raw thread ID from %gs:0
.inline _raw_thread_id,0
movl %gs:0, %eax
movl %gs:0, %eax
.end
// Get current sp
.inline _get_current_sp,0
.volatile
movl %esp, %eax
movl %esp, %eax
.end
// Get current fp
.inline _get_current_fp,0
.volatile
movl %ebp, %eax
movl %ebp, %eax
.end
// Support for os::rdtsc()
@ -76,8 +76,8 @@
xchgl (%ecx), %eax
.end
// Support for jbyte Atomic::cmpxchg(jbyte exchange_value,
// volatile jbyte *dest,
// Support for jbyte Atomic::cmpxchg(jbyte exchange_value,
// volatile jbyte *dest,
// jbyte compare_value)
// An additional bool (os::is_MP()) is passed as the last argument.
.inline _Atomic_cmpxchg_byte,4
@ -93,8 +93,8 @@
2:
.end
// Support for jint Atomic::cmpxchg(jint exchange_value,
// volatile jint *dest,
// Support for jint Atomic::cmpxchg(jint exchange_value,
// volatile jint *dest,
// jint compare_value)
// An additional bool (os::is_MP()) is passed as the last argument.
.inline _Atomic_cmpxchg,4
@ -141,17 +141,6 @@
fistpll (%eax)
.end
// Support for OrderAccess::acquire()
.inline _OrderAccess_acquire,0
movl 0(%esp), %eax
.end
// Support for OrderAccess::fence()
.inline _OrderAccess_fence,0
lock
addl $0, (%esp)
.end
// Support for u2 Bytes::swap_u2(u2 x)
.inline _raw_swap_u2,1
movl 0(%esp), %eax

29
hotspot/src/os_cpu/solaris_x86/vm/solaris_x86_64.il
View File

@ -1,5 +1,5 @@
//
// Copyright (c) 2004, 2012, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2004, 2015, Oracle and/or its affiliates. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
@ -19,7 +19,7 @@
// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
// or visit www.oracle.com if you need additional information or have any
// questions.
//
//
//
// The argument size of each inline directive is ignored by the compiler
@ -27,19 +27,19 @@
// Get the raw thread ID from %gs:0
.inline _raw_thread_id,0
movq %fs:0, %rax
movq %fs:0, %rax
.end
// Get current sp
.inline _get_current_sp,0
.volatile
movq %rsp, %rax
movq %rsp, %rax
.end
// Get current fp
.inline _get_current_fp,0
.volatile
movq %rbp, %rax
movq %rbp, %rax
.end
// Support for os::rdtsc()
@ -77,8 +77,8 @@
movq %rdi, %rax
.end
// Support for jbyte Atomic::cmpxchg(jbyte exchange_value,
// volatile jbyte *dest,
// Support for jbyte Atomic::cmpxchg(jbyte exchange_value,
// volatile jbyte *dest,
// jbyte compare_value)
.inline _Atomic_cmpxchg_byte,3
movb %dl, %al // compare_value
@ -86,8 +86,8 @@
cmpxchgb %dil, (%rsi)
.end
// Support for jint Atomic::cmpxchg(jint exchange_value,
// volatile jint *dest,
// Support for jint Atomic::cmpxchg(jint exchange_value,
// volatile jint *dest,
// jint compare_value)
.inline _Atomic_cmpxchg,3
movl %edx, %eax // compare_value
@ -104,17 +104,6 @@
cmpxchgq %rdi, (%rsi)
.end
// Support for OrderAccess::acquire()
.inline _OrderAccess_acquire,0
movl 0(%rsp), %eax
.end
// Support for OrderAccess::fence()
.inline _OrderAccess_fence,0
lock
addl $0, (%rsp)
.end
// Support for u2 Bytes::swap_u2(u2 x)
.inline _raw_swap_u2,1
movw %di, %ax

188
hotspot/src/os_cpu/windows_x86/vm/orderAccess_windows_x86.inline.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -25,29 +25,39 @@
#ifndef OS_CPU_WINDOWS_X86_VM_ORDERACCESS_WINDOWS_X86_INLINE_HPP
#define OS_CPU_WINDOWS_X86_VM_ORDERACCESS_WINDOWS_X86_INLINE_HPP
#include <intrin.h>
#include "runtime/atomic.inline.hpp"
#include "runtime/orderAccess.hpp"
#include "runtime/os.hpp"
// Compiler version last used for testing: Microsoft Visual Studio 2010
// Please update this information when this file changes
// Implementation of class OrderAccess.
inline void OrderAccess::loadload() { acquire(); }
inline void OrderAccess::storestore() { release(); }
inline void OrderAccess::loadstore() { acquire(); }
// A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions
inline void compiler_barrier() {
_ReadWriteBarrier();
}
// Note that in MSVC, volatile memory accesses are explicitly
// guaranteed to have acquire release semantics (w.r.t. compiler
// reordering) and therefore does not even need a compiler barrier
// for normal acquire release accesses. And all generalized
// bound calls like release_store go through OrderAccess::load
// and OrderAccess::store which do volatile memory accesses.
template<> inline void ScopedFence<X_ACQUIRE>::postfix() { }
template<> inline void ScopedFence<RELEASE_X>::prefix() { }
template<> inline void ScopedFence<RELEASE_X_FENCE>::prefix() { }
template<> inline void ScopedFence<RELEASE_X_FENCE>::postfix() { OrderAccess::fence(); }
inline void OrderAccess::loadload() { compiler_barrier(); }
inline void OrderAccess::storestore() { compiler_barrier(); }
inline void OrderAccess::loadstore() { compiler_barrier(); }
inline void OrderAccess::storeload() { fence(); }
inline void OrderAccess::acquire() {
#ifndef AMD64
__asm {
mov eax, dword ptr [esp];
}
#endif // !AMD64
}
inline void OrderAccess::release() {
// A volatile store has release semantics.
volatile jint local_dummy = 0;
}
inline void OrderAccess::acquire() { compiler_barrier(); }
inline void OrderAccess::release() { compiler_barrier(); }
inline void OrderAccess::fence() {
#ifdef AMD64
@ -59,157 +69,47 @@ inline void OrderAccess::fence() {
}
}
#endif // AMD64
compiler_barrier();
}
inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { return *p; }
inline jshort OrderAccess::load_acquire(volatile jshort* p) { return *p; }
inline jint OrderAccess::load_acquire(volatile jint* p) { return *p; }
inline jlong OrderAccess::load_acquire(volatile jlong* p) { return Atomic::load(p); }
inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { return *p; }
inline jushort OrderAccess::load_acquire(volatile jushort* p) { return *p; }
inline juint OrderAccess::load_acquire(volatile juint* p) { return *p; }
inline julong OrderAccess::load_acquire(volatile julong* p) { return Atomic::load((volatile jlong*)p); }
inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { return *p; }
inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { return jdouble_cast(Atomic::load((volatile jlong*)p)); }
inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { return *p; }
inline void* OrderAccess::load_ptr_acquire(volatile void* p) { return *(void* volatile *)p; }
inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { return *(void* const volatile *)p; }
inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { *p = v; }
inline void OrderAccess::release_store(volatile jshort* p, jshort v) { *p = v; }
inline void OrderAccess::release_store(volatile jint* p, jint v) { *p = v; }
inline void OrderAccess::release_store(volatile jlong* p, jlong v) { Atomic::store(v, p); }
inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { *p = v; }
inline void OrderAccess::release_store(volatile jushort* p, jushort v) { *p = v; }
inline void OrderAccess::release_store(volatile juint* p, juint v) { *p = v; }
inline void OrderAccess::release_store(volatile julong* p, julong v) { Atomic::store((jlong)v, (volatile jlong*)p); }
inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { *p = v; }
inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { release_store((volatile jlong*)p, jlong_cast(v)); }
inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { *p = v; }
inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { *(void* volatile *)p = v; }
inline void OrderAccess::store_fence(jbyte* p, jbyte v) {
#ifdef AMD64
*p = v; fence();
#else
#ifndef AMD64
template<>
inline void OrderAccess::specialized_release_store_fence<jbyte> (volatile jbyte* p, jbyte v) {
__asm {
mov edx, p;
mov al, v;
xchg al, byte ptr [edx];
}
#endif // AMD64
}
inline void OrderAccess::store_fence(jshort* p, jshort v) {
#ifdef AMD64
*p = v; fence();
#else
template<>
inline void OrderAccess::specialized_release_store_fence<jshort>(volatile jshort* p, jshort v) {
__asm {
mov edx, p;
mov ax, v;
xchg ax, word ptr [edx];
}
#endif // AMD64
}
inline void OrderAccess::store_fence(jint* p, jint v) {
#ifdef AMD64
*p = v; fence();
#else
template<>
inline void OrderAccess::specialized_release_store_fence<jint> (volatile jint* p, jint v) {
__asm {
mov edx, p;
mov eax, v;
xchg eax, dword ptr [edx];
}
}
#endif // AMD64
template<>
inline void OrderAccess::specialized_release_store_fence<jfloat>(volatile jfloat* p, jfloat v) {
release_store_fence((volatile jint*)p, jint_cast(v));
}
template<>
inline void OrderAccess::specialized_release_store_fence<jdouble>(volatile jdouble* p, jdouble v) {
release_store_fence((volatile jlong*)p, jlong_cast(v));
}
inline void OrderAccess::store_fence(jlong* p, jlong v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jubyte* p, jubyte v) { store_fence((jbyte*)p, (jbyte)v); }
inline void OrderAccess::store_fence(jushort* p, jushort v) { store_fence((jshort*)p, (jshort)v); }
inline void OrderAccess::store_fence(juint* p, juint v) { store_fence((jint*)p, (jint)v); }
inline void OrderAccess::store_fence(julong* p, julong v) { store_fence((jlong*)p, (jlong)v); }
inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; fence(); }
inline void OrderAccess::store_fence(jdouble* p, jdouble v) { *p = v; fence(); }
inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) {
#ifdef AMD64
*p = v; fence();
#else
store_fence((jint*)p, (jint)v);
#endif // AMD64
}
inline void OrderAccess::store_ptr_fence(void** p, void* v) {
#ifdef AMD64
*p = v; fence();
#else
store_fence((jint*)p, (jint)v);
#endif // AMD64
}
// Must duplicate definitions instead of calling store_fence because we don't want to cast away volatile.
inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) {
#ifdef AMD64
*p = v; fence();
#else
__asm {
mov edx, p;
mov al, v;
xchg al, byte ptr [edx];
}
#endif // AMD64
}
inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) {
#ifdef AMD64
*p = v; fence();
#else
__asm {
mov edx, p;
mov ax, v;
xchg ax, word ptr [edx];
}
#endif // AMD64
}
inline void OrderAccess::release_store_fence(volatile jint* p, jint v) {
#ifdef AMD64
*p = v; fence();
#else
__asm {
mov edx, p;
mov eax, v;
xchg eax, dword ptr [edx];
}
#endif // AMD64
}
inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) { release_store(p, v); fence(); }
inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { release_store_fence((volatile jbyte*)p, (jbyte)v); }
inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { release_store_fence((volatile jshort*)p, (jshort)v); }
inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { release_store_fence((volatile jint*)p, (jint)v); }
inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { release_store_fence((volatile jlong*)p, (jlong)v); }
inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { *p = v; fence(); }
inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { release_store_fence((volatile jlong*)p, jlong_cast(v)); }
inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) {
#ifdef AMD64
*p = v; fence();
#else
release_store_fence((volatile jint*)p, (jint)v);
#endif // AMD64
}
inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) {
#ifdef AMD64
*(void* volatile *)p = v; fence();
#else
release_store_fence((volatile jint*)p, (jint)v);
#endif // AMD64
}
#define VM_HAS_GENERALIZED_ORDER_ACCESS 1
#endif // OS_CPU_WINDOWS_X86_VM_ORDERACCESS_WINDOWS_X86_INLINE_HPP

7
hotspot/src/share/vm/c1/c1_LIR.cpp
View File

@ -142,16 +142,11 @@ LIR_Address::Scale LIR_Address::scale(BasicType type) {
#ifndef PRODUCT
void LIR_Address::verify() const {
void LIR_Address::verify0() const {
#if defined(SPARC) || defined(PPC)
assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
assert(disp() == 0 || index()->is_illegal(), "can't have both");
#endif
#ifdef ARM
assert(disp() == 0 || index()->is_illegal(), "can't have both");
// Note: offsets higher than 4096 must not be rejected here. They can
// be handled by the back-end or will be rejected if not.
#endif
#ifdef _LP64
assert(base()->is_cpu_register(), "wrong base operand");
#ifndef AARCH64

11
hotspot/src/share/vm/c1/c1_LIR.hpp
View File

@ -25,6 +25,7 @@
#ifndef SHARE_VM_C1_C1_LIR_HPP
#define SHARE_VM_C1_C1_LIR_HPP
#include "c1/c1_Defs.hpp"
#include "c1/c1_ValueType.hpp"
#include "oops/method.hpp"
@ -561,7 +562,13 @@ class LIR_Address: public LIR_OprPtr {
virtual BasicType type() const { return _type; }
virtual void print_value_on(outputStream* out) const PRODUCT_RETURN;
void verify() const PRODUCT_RETURN;
void verify0() const PRODUCT_RETURN;
#if defined(LIR_ADDRESS_PD_VERIFY) && !defined(PRODUCT)
void pd_verify() const;
void verify() const { pd_verify(); }
#else
void verify() const { verify0(); }
#endif
static Scale scale(BasicType type);
};
@ -610,7 +617,7 @@ class LIR_OprFact: public AllStatic {
LIR_OprDesc::float_type |
LIR_OprDesc::fpu_register |
LIR_OprDesc::single_size); }
#if defined(ARM)
#if defined(ARM32)
static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::fpu_register | LIR_OprDesc::double_size); }
static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) | LIR_OprDesc::float_type | LIR_OprDesc::cpu_register | LIR_OprDesc::single_size); }
static LIR_Opr double_softfp(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::cpu_register | LIR_OprDesc::double_size); }

35
hotspot/src/share/vm/c1/c1_LIRGenerator.cpp
View File

@ -23,6 +23,7 @@
*/
#include "precompiled.hpp"
#include "c1/c1_Defs.hpp"
#include "c1/c1_Compilation.hpp"
#include "c1/c1_FrameMap.hpp"
#include "c1/c1_Instruction.hpp"
@ -49,10 +50,7 @@
#define __ gen()->lir()->
#endif
// TODO: ARM - Use some recognizable constant which still fits architectural constraints
#ifdef ARM
#define PATCHED_ADDR (204)
#else
#ifndef PATCHED_ADDR
#define PATCHED_ADDR (max_jint)
#endif
@ -1600,24 +1598,9 @@ void LIRGenerator::CardTableModRef_post_barrier(LIR_OprDesc* addr, LIR_OprDesc*
}
assert(addr->is_register(), "must be a register at this point");
#ifdef ARM
// TODO: ARM - move to platform-dependent code
LIR_Opr tmp = FrameMap::R14_opr;
if (VM_Version::supports_movw()) {
__ move((LIR_Opr)card_table_base, tmp);
} else {
__ move(new LIR_Address(FrameMap::Rthread_opr, in_bytes(JavaThread::card_table_base_offset()), T_ADDRESS), tmp);
}
LIR_Address *card_addr = new LIR_Address(tmp, addr, (LIR_Address::Scale) -CardTableModRefBS::card_shift, 0, T_BYTE);
if(((int)ct->byte_map_base & 0xff) == 0) {
__ move(tmp, card_addr);
} else {
LIR_Opr tmp_zero = new_register(T_INT);
__ move(LIR_OprFact::intConst(0), tmp_zero);
__ move(tmp_zero, card_addr);
}
#else // ARM
#ifdef CARDTABLEMODREF_POST_BARRIER_HELPER
CardTableModRef_post_barrier_helper(addr, card_table_base);
#else
LIR_Opr tmp = new_pointer_register();
if (TwoOperandLIRForm) {
__ move(addr, tmp);
@ -1633,7 +1616,7 @@ void LIRGenerator::CardTableModRef_post_barrier(LIR_OprDesc* addr, LIR_OprDesc*
new LIR_Address(tmp, load_constant(card_table_base),
T_BYTE));
}
#endif // ARM
#endif
}
@ -2123,7 +2106,7 @@ void LIRGenerator::do_UnsafeGetRaw(UnsafeGetRaw* x) {
} else {
#ifdef X86
addr = new LIR_Address(base_op, index_op, LIR_Address::Scale(log2_scale), 0, dst_type);
#elif defined(ARM)
#elif defined(GENERATE_ADDRESS_IS_PREFERRED)
addr = generate_address(base_op, index_op, log2_scale, 0, dst_type);
#else
if (index_op->is_illegal() || log2_scale == 0) {
@ -2177,6 +2160,9 @@ void LIRGenerator::do_UnsafePutRaw(UnsafePutRaw* x) {
LIR_Opr base_op = base.result();
LIR_Opr index_op = idx.result();
#ifdef GENERATE_ADDRESS_IS_PREFERRED
LIR_Address* addr = generate_address(base_op, index_op, log2_scale, 0, x->basic_type());
#else
#ifndef _LP64
if (base_op->type() == T_LONG) {
base_op = new_register(T_INT);
@ -2210,6 +2196,7 @@ void LIRGenerator::do_UnsafePutRaw(UnsafePutRaw* x) {
}
LIR_Address* addr = new LIR_Address(base_op, index_op, x->basic_type());
#endif // !GENERATE_ADDRESS_IS_PREFERRED
__ move(value.result(), addr);
}

7
hotspot/src/share/vm/c1/c1_LIRGenerator.hpp
View File

@ -275,6 +275,9 @@ class LIRGenerator: public InstructionVisitor, public BlockClosure {
void G1SATBCardTableModRef_post_barrier(LIR_OprDesc* addr, LIR_OprDesc* new_val);
void CardTableModRef_post_barrier(LIR_OprDesc* addr, LIR_OprDesc* new_val);
#ifdef CARDTABLEMODREF_POST_BARRIER_HELPER
void CardTableModRef_post_barrier_helper(LIR_OprDesc* addr, LIR_Const* card_table_base);
#endif
static LIR_Opr result_register_for(ValueType* type, bool callee = false);
@ -546,6 +549,10 @@ class LIRGenerator: public InstructionVisitor, public BlockClosure {
#ifdef ASSERT
virtual void do_Assert (Assert* x);
#endif
#ifdef C1_LIRGENERATOR_MD_HPP
#include C1_LIRGENERATOR_MD_HPP
#endif
};

6
hotspot/src/share/vm/c1/c1_LinearScan.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2005, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2005, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -2123,7 +2123,7 @@ LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
#elif defined(ARM)
#elif defined(ARM32)
assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
@ -2712,7 +2712,7 @@ int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeV
#ifdef SPARC
assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
#endif
#ifdef ARM
#ifdef ARM32
assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
#endif
#ifdef PPC

4
hotspot/src/share/vm/c1/c1_Runtime1.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1999, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -1120,7 +1120,7 @@ JRT_ENTRY(void, Runtime1::patch_code(JavaThread* thread, Runtime1::StubID stub_i
#ifdef ARM
if((load_klass_or_mirror_patch_id ||
stub_id == Runtime1::load_appendix_patching_id) &&
!VM_Version::supports_movw()) {
nativeMovConstReg_at(copy_buff)->is_pc_relative()) {
nmethod* nm = CodeCache::find_nmethod(instr_pc);
address addr = NULL;
assert(nm != NULL, "invalid nmethod_pc");

2
hotspot/src/share/vm/classfile/classLoaderData.cpp
View File

@ -902,7 +902,7 @@ Klass* ClassLoaderDataGraphKlassIteratorAtomic::next_klass_in_cldg(Klass* klass)
}
Klass* ClassLoaderDataGraphKlassIteratorAtomic::next_klass() {
Klass* head = (Klass*)_next_klass;
Klass* head = _next_klass;
while (head != NULL) {
Klass* next = next_klass_in_cldg(head);

2
hotspot/src/share/vm/classfile/classLoaderData.hpp
View File

@ -315,7 +315,7 @@ class ClassLoaderData : public CHeapObj<mtClass> {
// An iterator that distributes Klasses to parallel worker threads.
class ClassLoaderDataGraphKlassIteratorAtomic : public StackObj {
volatile Klass* _next_klass;
Klass* volatile _next_klass;
public:
ClassLoaderDataGraphKlassIteratorAtomic();
Klass* next_klass();

2
hotspot/src/share/vm/gc_implementation/concurrentMarkSweep/concurrentMarkSweepGeneration.cpp
View File

@ -549,7 +549,7 @@ CMSCollector::CMSCollector(ConcurrentMarkSweepGeneration* cmsGen,
FLAG_SET_DEFAULT(ConcGCThreads, (ParallelGCThreads + 3)/4);
}
if (ConcGCThreads > 1) {
_conc_workers = new YieldingFlexibleWorkGang("Parallel CMS Threads",
_conc_workers = new YieldingFlexibleWorkGang("CMS Thread",
ConcGCThreads, true);
if (_conc_workers == NULL) {
warning("GC/CMS: _conc_workers allocation failure: "

2
hotspot/src/share/vm/gc_implementation/concurrentMarkSweep/concurrentMarkSweepThread.cpp
View File

@ -65,7 +65,7 @@ ConcurrentMarkSweepThread::ConcurrentMarkSweepThread(CMSCollector* collector)
assert(_collector == NULL, "Collector already set");
_collector = collector;
set_name("Concurrent Mark-Sweep GC Thread");
set_name("CMS Main Thread");
if (os::create_thread(this, os::cgc_thread)) {
// An old comment here said: "Priority should be just less

2
hotspot/src/share/vm/gc_implementation/g1/concurrentG1RefineThread.cpp
View File

@ -61,7 +61,7 @@ ConcurrentG1RefineThread(ConcurrentG1Refine* cg1r, ConcurrentG1RefineThread *nex
create_and_start();
// set name
set_name("G1 Concurrent Refinement Thread#%d", worker_id);
set_name("G1 Refine#%d", worker_id);
}
void ConcurrentG1RefineThread::initialize() {

46
hotspot/src/share/vm/gc_implementation/g1/concurrentMark.cpp
View File

@ -687,7 +687,7 @@ ConcurrentMark::ConcurrentMark(G1CollectedHeap* g1h, G1RegionToSpaceMapper* prev
gclog_or_tty->print_cr("CL Sleep Factor %1.4lf", cleanup_sleep_factor());
#endif
_parallel_workers = new FlexibleWorkGang("G1 Parallel Marking Threads",
_parallel_workers = new FlexibleWorkGang("G1 Marker",
_max_parallel_marking_threads, false, true);
if (_parallel_workers == NULL) {
vm_exit_during_initialization("Failed necessary allocation.");
@ -3561,6 +3561,15 @@ void CMTask::reset(CMBitMap* nextMarkBitMap) {
_termination_start_time_ms = 0.0;
#if _MARKING_STATS_
_aborted = 0;
_aborted_overflow = 0;
_aborted_cm_aborted = 0;
_aborted_yield = 0;
_aborted_timed_out = 0;
_aborted_satb = 0;
_aborted_termination = 0;
_steal_attempts = 0;
_steals = 0;
_local_pushes = 0;
_local_pops = 0;
_local_max_size = 0;
@ -3573,15 +3582,6 @@ void CMTask::reset(CMBitMap* nextMarkBitMap) {
_regions_claimed = 0;
_objs_found_on_bitmap = 0;
_satb_buffers_processed = 0;
_steal_attempts = 0;
_steals = 0;
_aborted = 0;
_aborted_overflow = 0;
_aborted_cm_aborted = 0;
_aborted_yield = 0;
_aborted_timed_out = 0;
_aborted_satb = 0;
_aborted_termination = 0;
#endif // _MARKING_STATS_
}
@ -3742,7 +3742,7 @@ void CMTask::move_entries_to_global_stack() {
gclog_or_tty->print_cr("[%u] pushed %d entries to the global stack",
_worker_id, n);
}
statsOnly( int tmp_size = _cm->mark_stack_size();
statsOnly( size_t tmp_size = _cm->mark_stack_size();
if (tmp_size > _global_max_size) {
_global_max_size = tmp_size;
}
@ -3777,7 +3777,7 @@ void CMTask::get_entries_from_global_stack() {
assert(success, "invariant");
}
statsOnly( int tmp_size = _task_queue->size();
statsOnly( size_t tmp_size = (size_t)_task_queue->size();
if (tmp_size > _local_max_size) {
_local_max_size = tmp_size;
}
@ -3934,24 +3934,24 @@ void CMTask::print_stats() {
gclog_or_tty->print_cr(" max = %1.2lfms, total = %1.2lfms",
_all_clock_intervals_ms.maximum(),
_all_clock_intervals_ms.sum());
gclog_or_tty->print_cr(" Clock Causes (cum): scanning = %d, marking = %d",
gclog_or_tty->print_cr(" Clock Causes (cum): scanning = " SIZE_FORMAT ", marking = " SIZE_FORMAT,
_clock_due_to_scanning, _clock_due_to_marking);
gclog_or_tty->print_cr(" Objects: scanned = %d, found on the bitmap = %d",
gclog_or_tty->print_cr(" Objects: scanned = " SIZE_FORMAT ", found on the bitmap = " SIZE_FORMAT,
_objs_scanned, _objs_found_on_bitmap);
gclog_or_tty->print_cr(" Local Queue: pushes = %d, pops = %d, max size = %d",
gclog_or_tty->print_cr(" Local Queue: pushes = " SIZE_FORMAT ", pops = " SIZE_FORMAT ", max size = " SIZE_FORMAT,
_local_pushes, _local_pops, _local_max_size);
gclog_or_tty->print_cr(" Global Stack: pushes = %d, pops = %d, max size = %d",
gclog_or_tty->print_cr(" Global Stack: pushes = " SIZE_FORMAT ", pops = " SIZE_FORMAT ", max size = " SIZE_FORMAT,
_global_pushes, _global_pops, _global_max_size);
gclog_or_tty->print_cr(" transfers to = %d, transfers from = %d",
gclog_or_tty->print_cr(" transfers to = " SIZE_FORMAT ", transfers from = " SIZE_FORMAT,
_global_transfers_to,_global_transfers_from);
gclog_or_tty->print_cr(" Regions: claimed = %d", _regions_claimed);
gclog_or_tty->print_cr(" SATB buffers: processed = %d", _satb_buffers_processed);
gclog_or_tty->print_cr(" Steals: attempts = %d, successes = %d",
gclog_or_tty->print_cr(" Regions: claimed = " SIZE_FORMAT, _regions_claimed);
gclog_or_tty->print_cr(" SATB buffers: processed = " SIZE_FORMAT, _satb_buffers_processed);
gclog_or_tty->print_cr(" Steals: attempts = " SIZE_FORMAT ", successes = " SIZE_FORMAT,
_steal_attempts, _steals);
gclog_or_tty->print_cr(" Aborted: %d, due to", _aborted);
gclog_or_tty->print_cr(" overflow: %d, global abort: %d, yield: %d",
gclog_or_tty->print_cr(" Aborted: " SIZE_FORMAT ", due to", _aborted);
gclog_or_tty->print_cr(" overflow: " SIZE_FORMAT ", global abort: " SIZE_FORMAT ", yield: " SIZE_FORMAT,
_aborted_overflow, _aborted_cm_aborted, _aborted_yield);
gclog_or_tty->print_cr(" time out: %d, SATB: %d, termination: %d",
gclog_or_tty->print_cr(" time out: " SIZE_FORMAT ", SATB: " SIZE_FORMAT ", termination: " SIZE_FORMAT,
_aborted_timed_out, _aborted_satb, _aborted_termination);
#endif // _MARKING_STATS_
}

48
hotspot/src/share/vm/gc_implementation/g1/concurrentMark.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2001, 2013, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2001, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -1039,36 +1039,36 @@ private:
NumberSeq _all_clock_intervals_ms;
double _interval_start_time_ms;
int _aborted;
int _aborted_overflow;
int _aborted_cm_aborted;
int _aborted_yield;
int _aborted_timed_out;
int _aborted_satb;
int _aborted_termination;
size_t _aborted;
size_t _aborted_overflow;
size_t _aborted_cm_aborted;
size_t _aborted_yield;
size_t _aborted_timed_out;
size_t _aborted_satb;
size_t _aborted_termination;
int _steal_attempts;
int _steals;
size_t _steal_attempts;
size_t _steals;
int _clock_due_to_marking;
int _clock_due_to_scanning;
size_t _clock_due_to_marking;
size_t _clock_due_to_scanning;
int _local_pushes;
int _local_pops;
int _local_max_size;
int _objs_scanned;
size_t _local_pushes;
size_t _local_pops;
size_t _local_max_size;
size_t _objs_scanned;
int _global_pushes;
int _global_pops;
int _global_max_size;
size_t _global_pushes;
size_t _global_pops;
size_t _global_max_size;
int _global_transfers_to;
int _global_transfers_from;
size_t _global_transfers_to;
size_t _global_transfers_from;
int _regions_claimed;
int _objs_found_on_bitmap;
size_t _regions_claimed;
size_t _objs_found_on_bitmap;
int _satb_buffers_processed;
size_t _satb_buffers_processed;
#endif // _MARKING_STATS_
// it updates the local fields after this task has claimed

4
hotspot/src/share/vm/gc_implementation/g1/concurrentMark.inline.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2001, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2001, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -252,7 +252,7 @@ inline void CMTask::push(oop obj) {
assert(success, "invariant");
}
statsOnly( int tmp_size = _task_queue->size();
statsOnly( size_t tmp_size = (size_t)_task_queue->size();
if (tmp_size > _local_max_size) {
_local_max_size = tmp_size;
}

4
hotspot/src/share/vm/gc_implementation/g1/concurrentMarkThread.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2001, 2013, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2001, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -48,7 +48,7 @@ ConcurrentMarkThread::ConcurrentMarkThread(ConcurrentMark* cm) :
_vtime_accum(0.0),
_vtime_mark_accum(0.0) {
set_name("G1 Main Concurrent Mark GC Thread");
set_name("G1 Main Marker");
create_and_start();
}

10
hotspot/src/share/vm/gc_implementation/g1/g1CollectedHeap.cpp
View File

@ -3538,7 +3538,7 @@ class RegisterHumongousWithInCSetFastTestClosure : public HeapRegionClosure {
r->rem_set()->clear_locked();
}
assert(r->rem_set()->is_empty(), "At this point any humongous candidate remembered set must be empty.");
g1h->register_humongous_region_with_in_cset_fast_test(region_idx);
g1h->register_humongous_region_with_cset(region_idx);
_candidate_humongous++;
}
_total_humongous++;
@ -3552,7 +3552,7 @@ class RegisterHumongousWithInCSetFastTestClosure : public HeapRegionClosure {
void flush_rem_set_entries() { _dcq.flush(); }
};
void G1CollectedHeap::register_humongous_regions_with_in_cset_fast_test() {
void G1CollectedHeap::register_humongous_regions_with_cset() {
if (!G1EagerReclaimHumongousObjects) {
g1_policy()->phase_times()->record_fast_reclaim_humongous_stats(0.0, 0, 0);
return;
@ -3859,7 +3859,7 @@ G1CollectedHeap::do_collection_pause_at_safepoint(double target_pause_time_ms) {
g1_policy()->finalize_cset(target_pause_time_ms, evacuation_info);
register_humongous_regions_with_in_cset_fast_test();
register_humongous_regions_with_cset();
assert(check_cset_fast_test(), "Inconsistency in the InCSetState table.");
@ -6077,7 +6077,7 @@ void G1CollectedHeap::free_collection_set(HeapRegion* cs_head, EvacuationInfo& e
HeapRegion* next = cur->next_in_collection_set();
assert(cur->in_collection_set(), "bad CS");
cur->set_next_in_collection_set(NULL);
cur->set_in_collection_set(false);
clear_in_cset(cur);
if (cur->is_young()) {
int index = cur->young_index_in_cset();
@ -6303,7 +6303,7 @@ void G1CollectedHeap::abandon_collection_set(HeapRegion* cs_head) {
HeapRegion* next = cur->next_in_collection_set();
assert(cur->in_collection_set(), "bad CS");
cur->set_next_in_collection_set(NULL);
cur->set_in_collection_set(false);
clear_in_cset(cur);
cur->set_young_index_in_cset(-1);
cur = next;
}

20
hotspot/src/share/vm/gc_implementation/g1/g1CollectedHeap.hpp
View File

@ -110,6 +110,7 @@ public:
void empty_list();
bool is_empty() { return _length == 0; }
uint length() { return _length; }
uint eden_length() { return length() - survivor_length(); }
uint survivor_length() { return _survivor_length; }
// Currently we do not keep track of the used byte sum for the
@ -119,7 +120,7 @@ public:
// we'll report the more accurate information then.
size_t eden_used_bytes() {
assert(length() >= survivor_length(), "invariant");
return (size_t) (length() - survivor_length()) * HeapRegion::GrainBytes;
return (size_t) eden_length() * HeapRegion::GrainBytes;
}
size_t survivor_used_bytes() {
return (size_t) survivor_length() * HeapRegion::GrainBytes;
@ -644,23 +645,21 @@ public:
// is considered a candidate for eager reclamation.
bool humongous_region_is_candidate(uint index);
// Register the given region to be part of the collection set.
inline void register_humongous_region_with_in_cset_fast_test(uint index);
inline void register_humongous_region_with_cset(uint index);
// Register regions with humongous objects (actually on the start region) in
// the in_cset_fast_test table.
void register_humongous_regions_with_in_cset_fast_test();
void register_humongous_regions_with_cset();
// We register a region with the fast "in collection set" test. We
// simply set to true the array slot corresponding to this region.
void register_young_region_with_in_cset_fast_test(HeapRegion* r) {
void register_young_region_with_cset(HeapRegion* r) {
_in_cset_fast_test.set_in_young(r->hrm_index());
}
void register_old_region_with_in_cset_fast_test(HeapRegion* r) {
void register_old_region_with_cset(HeapRegion* r) {
_in_cset_fast_test.set_in_old(r->hrm_index());
}
// This is a fast test on whether a reference points into the
// collection set or not. Assume that the reference
// points into the heap.
inline bool in_cset_fast_test(oop obj);
void clear_in_cset(const HeapRegion* hr) {
_in_cset_fast_test.clear(hr);
}
void clear_cset_fast_test() {
_in_cset_fast_test.clear();
@ -1245,6 +1244,7 @@ public:
// set. Slow implementation.
inline bool obj_in_cs(oop obj);
inline bool is_in_cset(const HeapRegion *hr);
inline bool is_in_cset(oop obj);
inline bool is_in_cset_or_humongous(const oop obj);

6
hotspot/src/share/vm/gc_implementation/g1/g1CollectedHeap.inline.hpp
View File

@ -234,6 +234,10 @@ inline bool G1CollectedHeap::is_in_cset(oop obj) {
return ret;
}
bool G1CollectedHeap::is_in_cset(const HeapRegion* hr) {
return _in_cset_fast_test.is_in_cset(hr);
}
bool G1CollectedHeap::is_in_cset_or_humongous(const oop obj) {
return _in_cset_fast_test.is_in_cset_or_humongous((HeapWord*)obj);
}
@ -242,7 +246,7 @@ InCSetState G1CollectedHeap::in_cset_state(const oop obj) {
return _in_cset_fast_test.at((HeapWord*)obj);
}
void G1CollectedHeap::register_humongous_region_with_in_cset_fast_test(uint index) {
void G1CollectedHeap::register_humongous_region_with_cset(uint index) {
_in_cset_fast_test.set_humongous(index);
}

26
hotspot/src/share/vm/gc_implementation/g1/g1CollectorPolicy.cpp
View File

@ -537,15 +537,12 @@ void G1CollectorPolicy::update_young_list_target_length(size_t rs_lengths) {
// This is how many young regions we already have (currently: the survivors).
uint base_min_length = recorded_survivor_regions();
// This is the absolute minimum young length, which ensures that we
// can allocate one eden region in the worst-case.
uint absolute_min_length = base_min_length + 1;
uint desired_min_length =
calculate_young_list_desired_min_length(base_min_length);
if (desired_min_length < absolute_min_length) {
desired_min_length = absolute_min_length;
}
uint desired_min_length = calculate_young_list_desired_min_length(base_min_length);
// This is the absolute minimum young length. Ensure that we
// will at least have one eden region available for allocation.
uint absolute_min_length = base_min_length + MAX2(_g1->young_list()->eden_length(), (uint)1);
// If we shrank the young list target it should not shrink below the current size.
desired_min_length = MAX2(desired_min_length, absolute_min_length);
// Calculate the absolute and desired max bounds.
// We will try our best not to "eat" into the reserve.
@ -1610,11 +1607,10 @@ void G1CollectorPolicy::add_old_region_to_cset(HeapRegion* hr) {
assert(hr->is_old(), "the region should be old");
assert(!hr->in_collection_set(), "should not already be in the CSet");
hr->set_in_collection_set(true);
_g1->register_old_region_with_cset(hr);
hr->set_next_in_collection_set(_collection_set);
_collection_set = hr;
_collection_set_bytes_used_before += hr->used();
_g1->register_old_region_with_in_cset_fast_test(hr);
size_t rs_length = hr->rem_set()->occupied();
_recorded_rs_lengths += rs_length;
_old_cset_region_length += 1;
@ -1744,10 +1740,8 @@ void G1CollectorPolicy::add_region_to_incremental_cset_common(HeapRegion* hr) {
_inc_cset_max_finger = MAX2(_inc_cset_max_finger, hr_end);
assert(!hr->in_collection_set(), "invariant");
hr->set_in_collection_set(true);
assert( hr->next_in_collection_set() == NULL, "invariant");
_g1->register_young_region_with_in_cset_fast_test(hr);
_g1->register_young_region_with_cset(hr);
assert(hr->next_in_collection_set() == NULL, "invariant");
}
// Add the region at the RHS of the incremental cset
@ -1925,7 +1919,7 @@ void G1CollectorPolicy::finalize_cset(double target_pause_time_ms, EvacuationInf
// [Newly Young Regions ++ Survivors from last pause].
uint survivor_region_length = young_list->survivor_length();
uint eden_region_length = young_list->length() - survivor_region_length;
uint eden_region_length = young_list->eden_length();
init_cset_region_lengths(eden_region_length, survivor_region_length);
HeapRegion* hr = young_list->first_survivor_region();

3
hotspot/src/share/vm/gc_implementation/g1/g1InCSetState.hpp
View File

@ -25,6 +25,7 @@
#ifndef SHARE_VM_GC_IMPLEMENTATION_G1_G1INCSETSTATE_HPP
#define SHARE_VM_GC_IMPLEMENTATION_G1_G1INCSETSTATE_HPP
#include "gc_implementation/g1/heapRegion.hpp"
#include "gc_implementation/g1/g1BiasedArray.hpp"
#include "memory/allocation.hpp"
@ -125,8 +126,10 @@ class G1InCSetStateFastTestBiasedMappedArray : public G1BiasedMappedArray<InCSet
bool is_in_cset_or_humongous(HeapWord* addr) const { return at(addr).is_in_cset_or_humongous(); }
bool is_in_cset(HeapWord* addr) const { return at(addr).is_in_cset(); }
bool is_in_cset(const HeapRegion* hr) const { return get_by_index(hr->hrm_index()).is_in_cset(); }
InCSetState at(HeapWord* addr) const { return get_by_address(addr); }
void clear() { G1BiasedMappedArray<InCSetState>::clear(); }
void clear(const HeapRegion* hr) { return set_by_index(hr->hrm_index(), InCSetState::NotInCSet); }
};
#endif // SHARE_VM_GC_IMPLEMENTATION_G1_G1INCSETSTATE_HPP

4
hotspot/src/share/vm/gc_implementation/g1/g1StringDedupThread.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -34,7 +34,7 @@ G1StringDedupThread* G1StringDedupThread::_thread = NULL;
G1StringDedupThread::G1StringDedupThread() :
ConcurrentGCThread() {
set_name("String Deduplication Thread");
set_name("G1 StrDedup");
create_and_start();
}

3
hotspot/src/share/vm/gc_implementation/g1/heapRegion.cpp
View File

@ -162,7 +162,7 @@ void HeapRegion::hr_clear(bool par, bool clear_space, bool locked) {
"we should have already filtered out humongous regions");
assert(_end == orig_end(),
"we should have already filtered out humongous regions");
assert(!_in_collection_set,
assert(!in_collection_set(),
err_msg("Should not clear heap region %u in the collection set", hrm_index()));
set_allocation_context(AllocationContext::system());
@ -262,7 +262,6 @@ HeapRegion::HeapRegion(uint hrm_index,
_hrm_index(hrm_index),
_allocation_context(AllocationContext::system()),
_humongous_start_region(NULL),
_in_collection_set(false),
_next_in_special_set(NULL),
_evacuation_failed(false),
_prev_marked_bytes(0), _next_marked_bytes(0), _gc_efficiency(0.0),

11
hotspot/src/share/vm/gc_implementation/g1/heapRegion.hpp
View File

@ -236,8 +236,6 @@ class HeapRegion: public G1OffsetTableContigSpace {
// For a humongous region, region in which it starts.
HeapRegion* _humongous_start_region;
// True iff the region is in current collection_set.
bool _in_collection_set;
// True iff an attempt to evacuate an object in the region failed.
bool _evacuation_failed;
@ -487,13 +485,8 @@ class HeapRegion: public G1OffsetTableContigSpace {
return _rem_set;
}
// True iff the region is in current collection_set.
bool in_collection_set() const {
return _in_collection_set;
}
void set_in_collection_set(bool b) {
_in_collection_set = b;
}
bool in_collection_set() const;
HeapRegion* next_in_collection_set() {
assert(in_collection_set(), "should only invoke on member of CS.");
assert(_next_in_special_set == NULL ||

4
hotspot/src/share/vm/gc_implementation/g1/heapRegion.inline.hpp
View File

@ -196,4 +196,8 @@ inline void HeapRegion::note_end_of_copying(bool during_initial_mark) {
}
}
inline bool HeapRegion::in_collection_set() const {
return G1CollectedHeap::heap()->is_in_cset(this);
}
#endif // SHARE_VM_GC_IMPLEMENTATION_G1_HEAPREGION_INLINE_HPP

2
hotspot/src/share/vm/gc_implementation/parallelScavenge/gcTaskThread.cpp
View File

@ -53,7 +53,7 @@ GCTaskThread::GCTaskThread(GCTaskManager* manager,
guarantee(_time_stamps != NULL, "Sanity");
}
set_id(which);
set_name("GC task thread#%d (ParallelGC)", which);
set_name("ParGC Thread#%d", which);
}
GCTaskThread::~GCTaskThread() {

1
hotspot/src/share/vm/interpreter/bytecodeInterpreter.cpp
View File

@ -34,6 +34,7 @@
#include "memory/resourceArea.hpp"
#include "oops/methodCounters.hpp"
#include "oops/objArrayKlass.hpp"
#include "oops/objArrayOop.inline.hpp"
#include "oops/oop.inline.hpp"
#include "prims/jvmtiExport.hpp"
#include "prims/jvmtiThreadState.hpp"

24
hotspot/src/share/vm/interpreter/interp_masm.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -27,25 +27,17 @@
#include "asm/macroAssembler.hpp"
#ifdef TARGET_ARCH_x86
#if defined INTERP_MASM_MD_HPP
# include INTERP_MASM_MD_HPP
#elif defined TARGET_ARCH_x86
# include "interp_masm_x86.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_sparc
#elif defined TARGET_ARCH_MODEL_sparc
# include "interp_masm_sparc.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_zero
#elif defined TARGET_ARCH_MODEL_zero
# include "interp_masm_zero.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_arm
# include "interp_masm_arm.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_ppc_32
# include "interp_masm_ppc_32.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_ppc_64
#elif defined TARGET_ARCH_MODEL_ppc_64
# include "interp_masm_ppc_64.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_aarch64
#elif defined TARGET_ARCH_MODEL_aarch64
# include "interp_masm_aarch64.hpp"
#endif

27
hotspot/src/share/vm/interpreter/templateTable.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -341,28 +341,19 @@ class TemplateTable: AllStatic {
static Template* template_for_wide(Bytecodes::Code code) { Bytecodes::wide_check(code); return &_template_table_wide[code]; }
// Platform specifics
#ifdef TARGET_ARCH_MODEL_x86_32
#if defined TEMPLATETABLE_MD_HPP
# include TEMPLATETABLE_MD_HPP
#elif defined TARGET_ARCH_MODEL_x86_32
# include "templateTable_x86_32.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_x86_64
#elif defined TARGET_ARCH_MODEL_x86_64
# include "templateTable_x86_64.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_sparc
#elif defined TARGET_ARCH_MODEL_sparc
# include "templateTable_sparc.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_zero
#elif defined TARGET_ARCH_MODEL_zero
# include "templateTable_zero.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_arm
# include "templateTable_arm.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_ppc_32
# include "templateTable_ppc_32.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_ppc_64
#elif defined TARGET_ARCH_MODEL_ppc_64
# include "templateTable_ppc_64.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_aarch64
#elif defined TARGET_ARCH_MODEL_aarch64
# include "templateTable_aarch64.hpp"
#endif

4
hotspot/src/share/vm/memory/generation.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -139,7 +139,7 @@ class Generation: public CHeapObj<mtGC> {
// GenGrain.
// Note: on ARM we add 1 bit for card_table_base to be properly aligned
// (we expect its low byte to be zero - see implementation of post_barrier)
LogOfGenGrain = 16 ARM_ONLY(+1),
LogOfGenGrain = 16 ARM32_ONLY(+1),
GenGrain = 1 << LogOfGenGrain
};

4
hotspot/src/share/vm/memory/sharedHeap.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -68,7 +68,7 @@ SharedHeap::SharedHeap(CollectorPolicy* policy_) :
}
_sh = this; // ch is static, should be set only once.
if (UseConcMarkSweepGC || UseG1GC) {
_workers = new FlexibleWorkGang("Parallel GC Threads", ParallelGCThreads,
_workers = new FlexibleWorkGang("GC Thread", ParallelGCThreads,
/* are_GC_task_threads */true,
/* are_ConcurrentGC_threads */false);
if (_workers == NULL) {

27
hotspot/src/share/vm/opto/ad.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -25,28 +25,19 @@
#ifndef SHARE_VM_OPTO_AD_HPP
#define SHARE_VM_OPTO_AD_HPP
#ifdef TARGET_ARCH_MODEL_x86_32
#if defined AD_MD_HPP
# include AD_MD_HPP
#elif defined TARGET_ARCH_MODEL_x86_32
# include "adfiles/ad_x86_32.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_x86_64
#elif defined TARGET_ARCH_MODEL_x86_64
# include "adfiles/ad_x86_64.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_sparc
#elif defined TARGET_ARCH_MODEL_sparc
# include "adfiles/ad_sparc.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_zero
#elif defined TARGET_ARCH_MODEL_zero
# include "adfiles/ad_zero.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_arm
# include "adfiles/ad_arm.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_ppc_32
# include "adfiles/ad_ppc_32.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_ppc_64
#elif defined TARGET_ARCH_MODEL_ppc_64
# include "adfiles/ad_ppc_64.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_aarch64
#elif defined TARGET_ARCH_MODEL_aarch64
# include "adfiles/ad_aarch64.hpp"
#endif

4
hotspot/src/share/vm/opto/chaitin.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -847,7 +847,7 @@ void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) {
case Op_RegD:
lrg.set_num_regs(2);
// Define platform specific register pressure
#if defined(SPARC) || defined(ARM)
#if defined(SPARC) || defined(ARM32)
lrg.set_reg_pressure(2);
#elif defined(IA32)
if( ireg == Op_RegL ) {

27
hotspot/src/share/vm/opto/optoreg.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2006, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -27,28 +27,19 @@
// AdGlobals contains c2 specific register handling code as specified
// in the .ad files.
#ifdef TARGET_ARCH_MODEL_x86_32
#if defined ADGLOBALS_MD_HPP
# include ADGLOBALS_MD_HPP
#elif defined TARGET_ARCH_MODEL_x86_32
# include "adfiles/adGlobals_x86_32.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_x86_64
#elif defined TARGET_ARCH_MODEL_x86_64
# include "adfiles/adGlobals_x86_64.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_sparc
#elif defined TARGET_ARCH_MODEL_sparc
# include "adfiles/adGlobals_sparc.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_zero
#elif defined TARGET_ARCH_MODEL_zero
# include "adfiles/adGlobals_zero.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_arm
# include "adfiles/adGlobals_arm.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_ppc_32
# include "adfiles/adGlobals_ppc_32.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_ppc_64
#elif defined TARGET_ARCH_MODEL_ppc_64
# include "adfiles/adGlobals_ppc_64.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_aarch64
#elif defined TARGET_ARCH_MODEL_aarch64
# include "adfiles/adGlobals_aarch64.hpp"
#endif

84
hotspot/src/share/vm/prims/whitebox.cpp
View File

@ -1133,6 +1133,75 @@ WB_ENTRY(void, WB_ForceSafepoint(JNIEnv* env, jobject wb))
VMThread::execute(&force_safepoint_op);
WB_END
template <typename T>
static bool GetMethodOption(JavaThread* thread, JNIEnv* env, jobject method, jstring name, T* value) {
assert(value != NULL, "sanity");
if (method == NULL || name == NULL) {
return false;
}
jmethodID jmid = reflected_method_to_jmid(thread, env, method);
CHECK_JNI_EXCEPTION_(env, false);
methodHandle mh(thread, Method::checked_resolve_jmethod_id(jmid));
// can't be in VM when we call JNI
ThreadToNativeFromVM ttnfv(thread);
const char* flag_name = env->GetStringUTFChars(name, NULL);
bool result = CompilerOracle::has_option_value(mh, flag_name, *value);
env->ReleaseStringUTFChars(name, flag_name);
return result;
}
WB_ENTRY(jobject, WB_GetMethodBooleaneOption(JNIEnv* env, jobject wb, jobject method, jstring name))
bool result;
if (GetMethodOption<bool> (thread, env, method, name, &result)) {
// can't be in VM when we call JNI
ThreadToNativeFromVM ttnfv(thread);
return booleanBox(thread, env, result);
}
return NULL;
WB_END
WB_ENTRY(jobject, WB_GetMethodIntxOption(JNIEnv* env, jobject wb, jobject method, jstring name))
intx result;
if (GetMethodOption <intx> (thread, env, method, name, &result)) {
// can't be in VM when we call JNI
ThreadToNativeFromVM ttnfv(thread);
return longBox(thread, env, result);
}
return NULL;
WB_END
WB_ENTRY(jobject, WB_GetMethodUintxOption(JNIEnv* env, jobject wb, jobject method, jstring name))
uintx result;
if (GetMethodOption <uintx> (thread, env, method, name, &result)) {
// can't be in VM when we call JNI
ThreadToNativeFromVM ttnfv(thread);
return longBox(thread, env, result);
}
return NULL;
WB_END
WB_ENTRY(jobject, WB_GetMethodDoubleOption(JNIEnv* env, jobject wb, jobject method, jstring name))
double result;
if (GetMethodOption <double> (thread, env, method, name, &result)) {
// can't be in VM when we call JNI
ThreadToNativeFromVM ttnfv(thread);
return doubleBox(thread, env, result);
}
return NULL;
WB_END
WB_ENTRY(jobject, WB_GetMethodStringOption(JNIEnv* env, jobject wb, jobject method, jstring name))
ccstr ccstrResult;
if (GetMethodOption <ccstr> (thread, env, method, name, &ccstrResult)) {
// can't be in VM when we call JNI
ThreadToNativeFromVM ttnfv(thread);
jstring result = env->NewStringUTF(ccstrResult);
CHECK_JNI_EXCEPTION_(env, NULL);
return result;
}
return NULL;
WB_END
//Some convenience methods to deal with objects from java
int WhiteBox::offset_for_field(const char* field_name, oop object,
Symbol* signature_symbol) {
@ -1333,6 +1402,21 @@ static JNINativeMethod methods[] = {
{CC"assertMatchingSafepointCalls", CC"(ZZ)V", (void*)&WB_AssertMatchingSafepointCalls },
{CC"isMonitorInflated", CC"(Ljava/lang/Object;)Z", (void*)&WB_IsMonitorInflated },
{CC"forceSafepoint", CC"()V", (void*)&WB_ForceSafepoint },
{CC"getMethodBooleanOption",
CC"(Ljava/lang/reflect/Executable;Ljava/lang/String;)Ljava/lang/Boolean;",
(void*)&WB_GetMethodBooleaneOption},
{CC"getMethodIntxOption",
CC"(Ljava/lang/reflect/Executable;Ljava/lang/String;)Ljava/lang/Long;",
(void*)&WB_GetMethodIntxOption},
{CC"getMethodUintxOption",
CC"(Ljava/lang/reflect/Executable;Ljava/lang/String;)Ljava/lang/Long;",
(void*)&WB_GetMethodUintxOption},
{CC"getMethodDoubleOption",
CC"(Ljava/lang/reflect/Executable;Ljava/lang/String;)Ljava/lang/Double;",
(void*)&WB_GetMethodDoubleOption},
{CC"getMethodStringOption",
CC"(Ljava/lang/reflect/Executable;Ljava/lang/String;)Ljava/lang/String;",
(void*)&WB_GetMethodStringOption},
};
#undef CC

2
hotspot/src/share/vm/runtime/arguments.cpp
View File

@ -321,6 +321,8 @@ static ObsoleteFlag obsolete_jvm_flags[] = {
{ "UseFastEmptyMethods", JDK_Version::jdk(9), JDK_Version::jdk(10) },
#endif // ZERO
{ "UseCompilerSafepoints", JDK_Version::jdk(9), JDK_Version::jdk(10) },
{ "AdaptiveSizePausePolicy", JDK_Version::jdk(9), JDK_Version::jdk(10) },
{ "ParallelGCRetainPLAB", JDK_Version::jdk(9), JDK_Version::jdk(10) },
{ NULL, JDK_Version(0), JDK_Version(0) }
};

15
hotspot/src/share/vm/runtime/globals.hpp
View File

@ -1080,9 +1080,6 @@ class CommandLineFlags {
notproduct(bool, ProfilerCheckIntervals, false, \
"Collect and print information on spacing of profiler ticks") \
\
develop(bool, PrintJVMWarnings, false, \
"Print warnings for unimplemented JVM functions") \
\
product(bool, PrintWarnings, true, \
"Print JVM warnings to output stream") \
\
@ -1207,10 +1204,6 @@ class CommandLineFlags {
"Use pthread-based instead of libthread-based synchronization " \
"(SPARC only)") \
\
product(bool, AdjustConcurrency, false, \
"Call thr_setconcurrency at thread creation time to avoid " \
"LWP starvation on MP systems (for Solaris Only)") \
\
product(bool, ReduceSignalUsage, false, \
"Reduce the use of OS signals in Java and/or the VM") \
\
@ -1557,11 +1550,6 @@ class CommandLineFlags {
product(uintx, ParallelGCBufferWastePct, 10, \
"Wasted fraction of parallel allocation buffer") \
\
diagnostic(bool, ParallelGCRetainPLAB, false, \
"Retain parallel allocation buffers across scavenges; " \
"it is disabled because this currently conflicts with " \
"parallel card scanning under certain conditions.") \
\
product(uintx, TargetPLABWastePct, 10, \
"Target wasted space in last buffer as percent of overall " \
"allocation") \
@ -2101,9 +2089,6 @@ class CommandLineFlags {
product(uintx, AdaptiveSizeThroughPutPolicy, 0, \
"Policy for changing generation size for throughput goals") \
\
product(uintx, AdaptiveSizePausePolicy, 0, \
"Policy for changing generation size for pause goals") \
\
develop(bool, PSAdjustTenuredGenForMinorPause, false, \
"Adjust tenured generation to achieve a minor pause goal") \
\

264
hotspot/src/share/vm/runtime/orderAccess.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -29,11 +29,7 @@
// Memory Access Ordering Model
//
// This interface is based on the JSR-133 Cookbook for Compiler Writers
// and on the IA64 memory model. It is the dynamic equivalent of the
// C/C++ volatile specifier. I.e., volatility restricts compile-time
// memory access reordering in a way similar to what we want to occur
// at runtime.
// This interface is based on the JSR-133 Cookbook for Compiler Writers.
//
// In the following, the terms 'previous', 'subsequent', 'before',
// 'after', 'preceding' and 'succeeding' refer to program order. The
@ -41,7 +37,6 @@
// relative to program order, while 'up' and 'above' refer to backward
// motion.
//
//
// We define four primitive memory barrier operations.
//
// LoadLoad: Load1(s); LoadLoad; Load2
@ -69,86 +64,88 @@
// operations. Stores before Store1 may *not* float below Load2 and any
// subsequent load operations.
//
// We define two further barriers: acquire and release.
//
// We define two further operations, 'release' and 'acquire'. They are
// mirror images of each other.
// Conceptually, acquire/release semantics form unidirectional and
// asynchronous barriers w.r.t. a synchronizing load(X) and store(X) pair.
// They should always be used in pairs to publish (release store) and
// access (load acquire) some implicitly understood shared data between
// threads in a relatively cheap fashion not requiring storeload. If not
// used in such a pair, it is advised to use a membar instead:
// acquire/release only make sense as pairs.
//
// Execution by a processor of release makes the effect of all memory
// accesses issued by it previous to the release visible to all
// processors *before* the release completes. The effect of subsequent
// memory accesses issued by it *may* be made visible *before* the
// release. I.e., subsequent memory accesses may float above the
// release, but prior ones may not float below it.
// T1: access_shared_data
// T1: ]release
// T1: (...)
// T1: store(X)
//
// Execution by a processor of acquire makes the effect of all memory
// accesses issued by it subsequent to the acquire visible to all
// processors *after* the acquire completes. The effect of prior memory
// accesses issued by it *may* be made visible *after* the acquire.
// I.e., prior memory accesses may float below the acquire, but
// subsequent ones may not float above it.
// T2: load(X)
// T2: (...)
// T2: acquire[
// T2: access_shared_data
//
// Finally, we define a 'fence' operation, which conceptually is a
// release combined with an acquire. In the real world these operations
// require one or more machine instructions which can float above and
// below the release or acquire, so we usually can't just issue the
// release-acquire back-to-back. All machines we know of implement some
// sort of memory fence instruction.
// It is guaranteed that if T2: load(X) synchronizes with (observes the
// value written by) T1: store(X), then the memory accesses before the T1:
// ]release happen before the memory accesses after the T2: acquire[.
//
// Total Store Order (TSO) machines can be seen as machines issuing a
// release store for each store and a load acquire for each load. Therefore
// there is an inherent resemblence between TSO and acquire/release
// semantics. TSO can be seen as an abstract machine where loads are
// executed immediately when encountered (hence loadload reordering not
// happening) but enqueues stores in a FIFO queue
// for asynchronous serialization (neither storestore or loadstore
// reordering happening). The only reordering happening is storeload due to
// the queue asynchronously serializing stores (yet in order).
//
// Acquire/release semantics essentially exploits this asynchronicity: when
// the load(X) acquire[ observes the store of ]release store(X), the
// accesses before the release must have happened before the accesses after
// acquire.
//
// The API offers both stand-alone acquire() and release() as well as bound
// load_acquire() and release_store(). It is guaranteed that these are
// semantically equivalent w.r.t. the defined model. However, since
// stand-alone acquire()/release() does not know which previous
// load/subsequent store is considered the synchronizing load/store, they
// may be more conservative in implementations. We advise using the bound
// variants whenever possible.
//
// Finally, we define a "fence" operation, as a bidirectional barrier.
// It guarantees that any memory access preceding the fence is not
// reordered w.r.t. any memory accesses subsequent to the fence in program
// order. This may be used to prevent sequences of loads from floating up
// above sequences of stores.
//
// The following table shows the implementations on some architectures:
//
// Constraint x86 sparc TSO ppc
// ---------------------------------------------------------------------------
// fence LoadStore | lock membar #StoreLoad sync
// StoreStore | addl 0,(sp)
// LoadLoad |
// StoreLoad
//
// release LoadStore | lwsync
// StoreStore
//
// acquire LoadLoad | lwsync
// LoadStore
//
// release_store <store> <store> lwsync
// <store>
//
// release_store_fence xchg <store> lwsync
// membar #StoreLoad <store>
// sync
//
//
// The standalone implementations of release and acquire need an associated
// dummy volatile store or load respectively. To avoid redundant operations,
// we can define the composite operators: 'release_store', 'store_fence' and
// 'load_acquire'. Here's a summary of the machine instructions corresponding
// to each operation.
// load_acquire <load> <load> <load>
// lwsync
//
// sparc RMO ia64 x86
// ---------------------------------------------------------------------
// fence membar #LoadStore | mf lock addl 0,(sp)
// #StoreStore |
// #LoadLoad |
// #StoreLoad
//
// release membar #LoadStore | st.rel [sp]=r0 movl $0,<dummy>
// #StoreStore
// st %g0,[]
//
// acquire ld [%sp],%g0 ld.acq <r>=[sp] movl (sp),<r>
// membar #LoadLoad |
// #LoadStore
//
// release_store membar #LoadStore | st.rel <store>
// #StoreStore
// st
//
// store_fence st st lock xchg
// fence mf
//
// load_acquire ld ld.acq <load>
// membar #LoadLoad |
// #LoadStore
//
// Using only release_store and load_acquire, we can implement the
// following ordered sequences.
//
// 1. load, load == load_acquire, load
// or load_acquire, load_acquire
// 2. load, store == load, release_store
// or load_acquire, store
// or load_acquire, release_store
// 3. store, store == store, release_store
// or release_store, release_store
//
// These require no membar instructions for sparc-TSO and no extra
// instructions for ia64.
//
// Ordering a load relative to preceding stores requires a store_fence,
// Ordering a load relative to preceding stores requires a StoreLoad,
// which implies a membar #StoreLoad between the store and load under
// sparc-TSO. A fence is required by ia64. On x86, we use locked xchg.
//
// 4. store, load == store_fence, load
//
// Use store_fence to make sure all stores done in an 'interesting'
// region are made visible prior to both subsequent loads and stores.
// sparc-TSO. On x86, we use explicitly locked add.
//
// Conventional usage is to issue a load_acquire for ordered loads. Use
// release_store for ordered stores when you care only that prior stores
@ -157,27 +154,19 @@
// release_store_fence to update values like the thread state, where we
// don't want the current thread to continue until all our prior memory
// accesses (including the new thread state) are visible to other threads.
// This is equivalent to the volatile semantics of the Java Memory Model.
//
// C++ Volatile Semantics
//
// C++ Volatility
//
// C++ guarantees ordering at operations termed 'sequence points' (defined
// to be volatile accesses and calls to library I/O functions). 'Side
// effects' (defined as volatile accesses, calls to library I/O functions
// and object modification) previous to a sequence point must be visible
// at that sequence point. See the C++ standard, section 1.9, titled
// "Program Execution". This means that all barrier implementations,
// including standalone loadload, storestore, loadstore, storeload, acquire
// and release must include a sequence point, usually via a volatile memory
// access. Other ways to guarantee a sequence point are, e.g., use of
// indirect calls and linux's __asm__ volatile.
// Note: as of 6973570, we have replaced the originally static "dummy" field
// (see above) by a volatile store to the stack. All of the versions of the
// compilers that we currently use (SunStudio, gcc and VC++) respect the
// semantics of volatile here. If you build HotSpot using other
// compilers, you may need to verify that no compiler reordering occurs
// across the sequence point represented by the volatile access.
//
// C++ volatile semantics prevent compiler re-ordering between
// volatile memory accesses. However, reordering between non-volatile
// and volatile memory accesses is in general undefined. For compiler
// reordering constraints taking non-volatile memory accesses into
// consideration, a compiler barrier has to be used instead. Some
// compiler implementations may choose to enforce additional
// constraints beyond those required by the language. Note also that
// both volatile semantics and compiler barrier do not prevent
// hardware reordering.
//
// os::is_MP Considered Redundant
//
@ -240,8 +229,32 @@
// order. If their implementations change such that these assumptions
// are violated, a whole lot of code will break.
enum ScopedFenceType {
X_ACQUIRE
, RELEASE_X
, RELEASE_X_FENCE
};
template <ScopedFenceType T>
class ScopedFenceGeneral: public StackObj {
public:
void prefix() {}
void postfix() {}
};
template <ScopedFenceType T>
class ScopedFence : public ScopedFenceGeneral<T> {
void *const _field;
public:
ScopedFence(void *const field) : _field(field) { prefix(); }
~ScopedFence() { postfix(); }
void prefix() { ScopedFenceGeneral<T>::prefix(); }
void postfix() { ScopedFenceGeneral<T>::postfix(); }
};
class OrderAccess : AllStatic {
public:
// barriers
static void loadload();
static void storestore();
static void loadstore();
@ -280,20 +293,6 @@ class OrderAccess : AllStatic {
static void release_store_ptr(volatile intptr_t* p, intptr_t v);
static void release_store_ptr(volatile void* p, void* v);
static void store_fence(jbyte* p, jbyte v);
static void store_fence(jshort* p, jshort v);
static void store_fence(jint* p, jint v);
static void store_fence(jlong* p, jlong v);
static void store_fence(jubyte* p, jubyte v);
static void store_fence(jushort* p, jushort v);
static void store_fence(juint* p, juint v);
static void store_fence(julong* p, julong v);
static void store_fence(jfloat* p, jfloat v);
static void store_fence(jdouble* p, jdouble v);
static void store_ptr_fence(intptr_t* p, intptr_t v);
static void store_ptr_fence(void** p, void* v);
static void release_store_fence(volatile jbyte* p, jbyte v);
static void release_store_fence(volatile jshort* p, jshort v);
static void release_store_fence(volatile jint* p, jint v);
@ -313,6 +312,47 @@ class OrderAccess : AllStatic {
// routine if it exists, It should only be used by platforms that
// don't have another way to do the inline assembly.
static void StubRoutines_fence();
// Give platforms a variation point to specialize.
template<typename T> static T specialized_load_acquire (volatile T* p );
template<typename T> static void specialized_release_store (volatile T* p, T v);
template<typename T> static void specialized_release_store_fence(volatile T* p, T v);
template<typename FieldType, ScopedFenceType FenceType>
static void ordered_store(volatile FieldType* p, FieldType v);
template<typename FieldType, ScopedFenceType FenceType>
static FieldType ordered_load(volatile FieldType* p);
static void store(volatile jbyte* p, jbyte v);
static void store(volatile jshort* p, jshort v);
static void store(volatile jint* p, jint v);
static void store(volatile jlong* p, jlong v);
static void store(volatile jdouble* p, jdouble v);
static void store(volatile jfloat* p, jfloat v);
static jbyte load (volatile jbyte* p);
static jshort load (volatile jshort* p);
static jint load (volatile jint* p);
static jlong load (volatile jlong* p);
static jdouble load (volatile jdouble* p);
static jfloat load (volatile jfloat* p);
// The following store_fence methods are deprecated and will be removed
// when all repos conform to the new generalized OrderAccess.
static void store_fence(jbyte* p, jbyte v);
static void store_fence(jshort* p, jshort v);
static void store_fence(jint* p, jint v);
static void store_fence(jlong* p, jlong v);
static void store_fence(jubyte* p, jubyte v);
static void store_fence(jushort* p, jushort v);
static void store_fence(juint* p, juint v);
static void store_fence(julong* p, julong v);
static void store_fence(jfloat* p, jfloat v);
static void store_fence(jdouble* p, jdouble v);
static void store_ptr_fence(intptr_t* p, intptr_t v);
static void store_ptr_fence(void** p, void* v);
};
#endif // SHARE_VM_RUNTIME_ORDERACCESS_HPP

91
hotspot/src/share/vm/runtime/orderAccess.inline.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2015, Oracle and/or its affiliates. All rights reserved.
* Copyright 2014 SAP AG. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -26,6 +26,7 @@
#ifndef SHARE_VM_RUNTIME_ORDERACCESS_INLINE_HPP
#define SHARE_VM_RUNTIME_ORDERACCESS_INLINE_HPP
#include "runtime/atomic.inline.hpp"
#include "runtime/orderAccess.hpp"
// Linux
@ -74,4 +75,92 @@
# include "orderAccess_bsd_zero.inline.hpp"
#endif
#ifdef VM_HAS_GENERALIZED_ORDER_ACCESS
template<> inline void ScopedFenceGeneral<X_ACQUIRE>::postfix() { OrderAccess::acquire(); }
template<> inline void ScopedFenceGeneral<RELEASE_X>::prefix() { OrderAccess::release(); }
template<> inline void ScopedFenceGeneral<RELEASE_X_FENCE>::prefix() { OrderAccess::release(); }
template<> inline void ScopedFenceGeneral<RELEASE_X_FENCE>::postfix() { OrderAccess::fence(); }
template <typename FieldType, ScopedFenceType FenceType>
inline void OrderAccess::ordered_store(volatile FieldType* p, FieldType v) {
ScopedFence<FenceType> f((void*)p);
store(p, v);
}
template <typename FieldType, ScopedFenceType FenceType>
inline FieldType OrderAccess::ordered_load(volatile FieldType* p) {
ScopedFence<FenceType> f((void*)p);
return load(p);
}
inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { return specialized_load_acquire(p); }
inline jshort OrderAccess::load_acquire(volatile jshort* p) { return specialized_load_acquire(p); }
inline jint OrderAccess::load_acquire(volatile jint* p) { return specialized_load_acquire(p); }
inline jlong OrderAccess::load_acquire(volatile jlong* p) { return specialized_load_acquire(p); }
inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { return specialized_load_acquire(p); }
inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { return specialized_load_acquire(p); }
inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { return (jubyte) specialized_load_acquire((volatile jbyte*)p); }
inline jushort OrderAccess::load_acquire(volatile jushort* p) { return (jushort)specialized_load_acquire((volatile jshort*)p); }
inline juint OrderAccess::load_acquire(volatile juint* p) { return (juint) specialized_load_acquire((volatile jint*)p); }
inline julong OrderAccess::load_acquire(volatile julong* p) { return (julong) specialized_load_acquire((volatile jlong*)p); }
inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { return (intptr_t)specialized_load_acquire(p); }
inline void* OrderAccess::load_ptr_acquire(volatile void* p) { return (void*)specialized_load_acquire((volatile intptr_t*)p); }
inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { return (void*)specialized_load_acquire((volatile intptr_t*)p); }
inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { specialized_release_store(p, v); }
inline void OrderAccess::release_store(volatile jshort* p, jshort v) { specialized_release_store(p, v); }
inline void OrderAccess::release_store(volatile jint* p, jint v) { specialized_release_store(p, v); }
inline void OrderAccess::release_store(volatile jlong* p, jlong v) { specialized_release_store(p, v); }
inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { specialized_release_store(p, v); }
inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { specialized_release_store(p, v); }
inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { specialized_release_store((volatile jbyte*) p, (jbyte) v); }
inline void OrderAccess::release_store(volatile jushort* p, jushort v) { specialized_release_store((volatile jshort*)p, (jshort)v); }
inline void OrderAccess::release_store(volatile juint* p, juint v) { specialized_release_store((volatile jint*) p, (jint) v); }
inline void OrderAccess::release_store(volatile julong* p, julong v) { specialized_release_store((volatile jlong*) p, (jlong) v); }
inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { specialized_release_store(p, v); }
inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { specialized_release_store((volatile intptr_t*)p, (intptr_t)v); }
inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) { specialized_release_store_fence(p, v); }
inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) { specialized_release_store_fence(p, v); }
inline void OrderAccess::release_store_fence(volatile jint* p, jint v) { specialized_release_store_fence(p, v); }
inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) { specialized_release_store_fence(p, v); }
inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { specialized_release_store_fence(p, v); }
inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { specialized_release_store_fence(p, v); }
inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { specialized_release_store_fence((volatile jbyte*) p, (jbyte) v); }
inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { specialized_release_store_fence((volatile jshort*)p, (jshort)v); }
inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { specialized_release_store_fence((volatile jint*) p, (jint) v); }
inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { specialized_release_store_fence((volatile jlong*) p, (jlong) v); }
inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) { specialized_release_store_fence(p, v); }
inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) { specialized_release_store_fence((volatile intptr_t*)p, (intptr_t)v); }
// The following methods can be specialized using simple template specialization
// in the platform specific files for optimization purposes. Otherwise the
// generalized variant is used.
template<typename T> inline T OrderAccess::specialized_load_acquire (volatile T* p) { return ordered_load<T, X_ACQUIRE>(p); }
template<typename T> inline void OrderAccess::specialized_release_store (volatile T* p, T v) { ordered_store<T, RELEASE_X>(p, v); }
template<typename T> inline void OrderAccess::specialized_release_store_fence(volatile T* p, T v) { ordered_store<T, RELEASE_X_FENCE>(p, v); }
// Generalized atomic volatile accesses valid in OrderAccess
// All other types can be expressed in terms of these.
inline void OrderAccess::store(volatile jbyte* p, jbyte v) { *p = v; }
inline void OrderAccess::store(volatile jshort* p, jshort v) { *p = v; }
inline void OrderAccess::store(volatile jint* p, jint v) { *p = v; }
inline void OrderAccess::store(volatile jlong* p, jlong v) { Atomic::store(v, p); }
inline void OrderAccess::store(volatile jdouble* p, jdouble v) { Atomic::store(jlong_cast(v), (volatile jlong*)p); }
inline void OrderAccess::store(volatile jfloat* p, jfloat v) { *p = v; }
inline jbyte OrderAccess::load(volatile jbyte* p) { return *p; }
inline jshort OrderAccess::load(volatile jshort* p) { return *p; }
inline jint OrderAccess::load(volatile jint* p) { return *p; }
inline jlong OrderAccess::load(volatile jlong* p) { return Atomic::load(p); }
inline jdouble OrderAccess::load(volatile jdouble* p) { return jdouble_cast(Atomic::load((volatile jlong*)p)); }
inline jfloat OrderAccess::load(volatile jfloat* p) { return *p; }
#endif // VM_HAS_GENERALIZED_ORDER_ACCESS
#endif // SHARE_VM_RUNTIME_ORDERACCESS_INLINE_HPP

28
hotspot/src/share/vm/runtime/stubRoutines.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -84,32 +84,22 @@ class StubRoutines: AllStatic {
// Dependencies
friend class StubGenerator;
#ifdef TARGET_ARCH_MODEL_x86_32
#if defined STUBROUTINES_MD_HPP
# include STUBROUTINES_MD_HPP
#elif defined TARGET_ARCH_MODEL_x86_32
# include "stubRoutines_x86_32.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_x86_64
#elif defined TARGET_ARCH_MODEL_x86_64
# include "stubRoutines_x86_64.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_sparc
#elif defined TARGET_ARCH_MODEL_sparc
# include "stubRoutines_sparc.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_zero
#elif defined TARGET_ARCH_MODEL_zero
# include "stubRoutines_zero.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_arm
# include "stubRoutines_arm.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_ppc_32
# include "stubRoutines_ppc_32.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_ppc_64
#elif defined TARGET_ARCH_MODEL_ppc_64
# include "stubRoutines_ppc_64.hpp"
#endif
#ifdef TARGET_ARCH_MODEL_aarch64
#elif defined TARGET_ARCH_MODEL_aarch64
# include "stubRoutines_aarch64.hpp"
#endif
static jint _verify_oop_count;
static address _verify_oop_subroutine_entry;

12
hotspot/src/share/vm/runtime/vm_version.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1998, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1998, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -187,18 +187,18 @@ const char* Abstract_VM_Version::jre_release_version() {
AIX_ONLY("aix") \
BSD_ONLY("bsd")
#ifndef CPU
#ifdef ZERO
#define CPU ZERO_LIBARCH
#else
#define CPU IA32_ONLY("x86") \
IA64_ONLY("ia64") \
AMD64_ONLY("amd64") \
ARM_ONLY("arm") \
PPC32_ONLY("ppc") \
PPC64_ONLY("ppc64") \
AARCH64_ONLY("aarch64") \
SPARC_ONLY("sparc")
#endif // ZERO
#endif
const char *Abstract_VM_Version::vm_platform_string() {
return OS "-" CPU;
@ -251,12 +251,6 @@ const char* Abstract_VM_Version::internal_vm_info_string() {
#ifndef FLOAT_ARCH
#if defined(__SOFTFP__)
#define FLOAT_ARCH_STR "-sflt"
#elif defined(E500V2)
#define FLOAT_ARCH_STR "-e500v2"
#elif defined(ARM)
#define FLOAT_ARCH_STR "-vfp"
#elif defined(PPC32)
#define FLOAT_ARCH_STR "-hflt"
#else
#define FLOAT_ARCH_STR ""
#endif

3
hotspot/src/share/vm/services/mallocSiteTable.cpp
View File

@ -135,8 +135,7 @@ bool MallocSiteTable::walk(MallocSiteWalker* walker) {
*/
MallocSite* MallocSiteTable::lookup_or_add(const NativeCallStack& key, size_t* bucket_idx,
size_t* pos_idx) {
int index = hash_to_index(key.hash());
assert(index >= 0, err_msg("Negative index %d", index));
unsigned int index = hash_to_index(key.hash());
*bucket_idx = (size_t)index;
*pos_idx = 0;

3
hotspot/src/share/vm/services/mallocSiteTable.hpp
View File

@ -238,8 +238,7 @@ class MallocSiteTable : AllStatic {
static MallocSite* malloc_site(size_t bucket_idx, size_t pos_idx);
static bool walk(MallocSiteWalker* walker);
static inline int hash_to_index(int hash) {
hash = (hash > 0) ? hash : (-hash);
static inline unsigned int hash_to_index(unsigned int hash) {
return (hash % table_size);
}

4
hotspot/src/share/vm/utilities/globalDefinitions_gcc.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1998, 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1998, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -220,7 +220,7 @@ extern "C" {
#define DEBUG_EXCEPTION ::abort();
#ifdef ARM
#ifdef ARM32
#ifdef SOLARIS
#define BREAKPOINT __asm__ volatile (".long 0xe1200070")
#else

4
hotspot/src/share/vm/utilities/globalDefinitions_sparcWorks.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -33,7 +33,9 @@
# include <ctype.h>
#define __USE_LEGACY_PROTOTYPES__
# include <dirent.h>
#undef __USE_LEGACY_PROTOTYPES__
# include <string.h>
# include <strings.h> // for bsd'isms
# include <stdarg.h>

11
hotspot/src/share/vm/utilities/macros.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -392,7 +392,6 @@
#define NOT_E500V2(code) code
#endif
#ifdef ARM
#define ARM_ONLY(code) code
#define NOT_ARM(code)
@ -401,6 +400,14 @@
#define NOT_ARM(code) code
#endif
#ifdef ARM32
#define ARM32_ONLY(code) code
#define NOT_ARM32(code)
#else
#define ARM32_ONLY(code)
#define NOT_ARM32(code) code
#endif
#ifdef AARCH64
#define AARCH64_ONLY(code) code
#define NOT_AARCH64(code)

16
hotspot/src/share/vm/utilities/nativeCallStack.cpp
View File

@ -55,6 +55,7 @@ NativeCallStack::NativeCallStack(address* pc, int frameCount) {
for (; index < NMT_TrackingStackDepth; index ++) {
_stack[index] = NULL;
}
_hash_value = 0;
}
// number of stack frames captured
@ -69,19 +70,16 @@ int NativeCallStack::frames() const {
}
// Hash code. Any better algorithm?
int NativeCallStack::hash() const {
long hash_val = _hash_value;
unsigned int NativeCallStack::hash() const {
uintptr_t hash_val = _hash_value;
if (hash_val == 0) {
long pc;
int index;
for (index = 0; index < NMT_TrackingStackDepth; index ++) {
pc = (long)_stack[index];
if (pc == 0) break;
hash_val += pc;
for (int index = 0; index < NMT_TrackingStackDepth; index++) {
if (_stack[index] == NULL) break;
hash_val += (uintptr_t)_stack[index];
}
NativeCallStack* p = const_cast<NativeCallStack*>(this);
p->_hash_value = (int)(hash_val & 0xFFFFFFFF);
p->_hash_value = (unsigned int)(hash_val & 0xFFFFFFFF);
}
return _hash_value;
}

6
hotspot/src/share/vm/utilities/nativeCallStack.hpp
View File

@ -56,8 +56,8 @@ class NativeCallStack : public StackObj {
static const NativeCallStack EMPTY_STACK;
private:
address _stack[NMT_TrackingStackDepth];
int _hash_value;
address _stack[NMT_TrackingStackDepth];
unsigned int _hash_value;
public:
NativeCallStack(int toSkip = 0, bool fillStack = false);
@ -89,7 +89,7 @@ class NativeCallStack : public StackObj {
}
// Hash code. Any better algorithm?
int hash() const;
unsigned int hash() const;
void print_on(outputStream* out) const;
void print_on(outputStream* out, int indent) const;

2
hotspot/src/share/vm/utilities/workgroup.cpp
View File

@ -236,7 +236,7 @@ void AbstractWorkGang::threads_do(ThreadClosure* tc) const {
GangWorker::GangWorker(AbstractWorkGang* gang, uint id) {
_gang = gang;
set_id(id);
set_name("Gang worker#%d (%s)", id, gang->name());
set_name("%s#%d", gang->name(), id);
}
void GangWorker::run() {

104
hotspot/test/compiler/oracle/GetMethodOptionTest.java Normal file
View File

@ -0,0 +1,104 @@
/*
* Copyright (c) 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*/
import java.lang.reflect.Executable;
import java.util.function.BiFunction;
import com.oracle.java.testlibrary.Asserts;
import sun.hotspot.WhiteBox;
/*
* @test
* @bug 8074980
* @library /testlibrary /../../test/lib
* @build sun.hotspot.WhiteBox com.oracle.java.testlibrary.Asserts GetMethodOptionTest
* @run main ClassFileInstaller sun.hotspot.WhiteBox
* sun.hotspot.WhiteBox$WhiteBoxPermission
* @run main/othervm -Xbootclasspath/a:. -XX:+UnlockDiagnosticVMOptions -XX:+WhiteBoxAPI
* -XX:CompileCommand=option,GetMethodOptionTest::test,ccstrlist,MyListOption,_foo,_bar
* -XX:CompileCommand=option,GetMethodOptionTest::test,ccstr,MyStrOption,_foo
* -XX:CompileCommand=option,GetMethodOptionTest::test,bool,MyBoolOption,false
* -XX:CompileCommand=option,GetMethodOptionTest::test,intx,MyIntxOption,-1
* -XX:CompileCommand=option,GetMethodOptionTest::test,uintx,MyUintxOption,1
* -XX:CompileCommand=option,GetMethodOptionTest::test,MyFlag
* -XX:CompileCommand=option,GetMethodOptionTest::test,double,MyDoubleOption1,1.123
* -XX:CompileCommand=option,GetMethodOptionTest.test,double,MyDoubleOption2,1.123
* -XX:CompileCommand=option,GetMethodOptionTest::test,bool,MyBoolOptionX,false,intx,MyIntxOptionX,-1,uintx,MyUintxOptionX,1,MyFlagX,double,MyDoubleOptionX,1.123
* GetMethodOptionTest
*/
public class GetMethodOptionTest {
private static final WhiteBox WB = WhiteBox.getWhiteBox();
public static void main(String[] args) {
Executable test = getMethod("test");
Executable test2 = getMethod("test2");
BiFunction<Executable, String, Object> getter = WB::getMethodOption;
for (TestCase testCase : TestCase.values()) {
Object expected = testCase.value;
String name = testCase.name();
Asserts.assertEQ(expected, getter.apply(test, name),
testCase + ": universal getter returns wrong value");
Asserts.assertEQ(expected, testCase.getter.apply(test, name),
testCase + ": specific getter returns wrong value");
Asserts.assertEQ(null, getter.apply(test2, name),
testCase + ": universal getter returns value for unused method");
Asserts.assertEQ(null, testCase.getter.apply(test2, name),
testCase + ": type specific getter returns value for unused method");
}
}
private static void test() { }
private static void test2() { }
private static enum TestCase {
MyListOption("_foo _bar", WB::getMethodStringOption),
MyStrOption("_foo", WB::getMethodStringOption),
MyBoolOption(false, WB::getMethodBooleanOption),
MyIntxOption(-1L, WB::getMethodIntxOption),
MyUintxOption(1L, WB::getMethodUintxOption),
MyFlag(true, WB::getMethodBooleanOption),
MyDoubleOption1(1.123d, WB::getMethodDoubleOption),
MyDoubleOption2(1.123d, WB::getMethodDoubleOption),
MyBoolOptionX(false, WB::getMethodBooleanOption),
MyIntxOptionX(-1L, WB::getMethodIntxOption),
MyUintxOptionX(1L, WB::getMethodUintxOption),
MyFlagX(true, WB::getMethodBooleanOption),
MyDoubleOptionX(1.123d, WB::getMethodDoubleOption);
public final Object value;
public final BiFunction<Executable, String, Object> getter;
private TestCase(Object value, BiFunction<Executable, String, Object> getter) {
this.value = value;
this.getter = getter;
}
}
private static Executable getMethod(String name) {
Executable result;
try {
result = GetMethodOptionTest.class.getDeclaredMethod(name);
} catch (NoSuchMethodException | SecurityException e) {
throw new Error("TESTBUG : can't get method " + name, e);
}
return result;
}
}

6
hotspot/test/compiler/whitebox/DeoptimizeFramesTest.java
View File

@ -31,11 +31,13 @@
* @run main/othervm -Xbootclasspath/a:. -XX:+UnlockDiagnosticVMOptions
* -XX:+WhiteBoxAPI -Xmixed
* -XX:CompileCommand=compileonly,DeoptimizeFramesTest$TestCaseImpl::method
* -XX:-DeoptimizeRandom -XX:-DeoptimizeALot DeoptimizeFramesTest true
* -XX:+IgnoreUnexpectedVMOptions -XX:-DeoptimizeRandom -XX:-DeoptimizeALot
* DeoptimizeFramesTest true
* @run main/othervm -Xbootclasspath/a:. -XX:+UnlockDiagnosticVMOptions
* -XX:+WhiteBoxAPI -Xmixed
* -XX:CompileCommand=compileonly,DeoptimizeFramesTest$TestCaseImpl::method
* -XX:-DeoptimizeRandom -XX:-DeoptimizeALot DeoptimizeFramesTest false
* -XX:+IgnoreUnexpectedVMOptions -XX:-DeoptimizeRandom -XX:-DeoptimizeALot
* DeoptimizeFramesTest false
* @summary testing of WB::deoptimizeFrames()
*/
import java.lang.reflect.Executable;

5
hotspot/test/gc/parallelScavenge/TestDynShrinkHeap.java
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -22,7 +22,6 @@
*/
/**
* @ignore 8019361
* @test TestDynShrinkHeap
* @bug 8016479
* @requires vm.gc=="Parallel" | vm.gc=="null"
@ -35,7 +34,7 @@ import java.lang.management.ManagementFactory;
import java.lang.management.MemoryUsage;
import java.util.ArrayList;
import sun.management.ManagementFactoryHelper;
import static com.oracle.java.testlibrary.Asserts.*;
import static com.oracle.java.testlibrary.Asserts.assertLessThan;
public class TestDynShrinkHeap {