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8202395: AARCH64: wrong encoding for SIMD instructions zip, trn, uzp

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Reviewed-by: aph
This commit is contained in:
Dmitrij Pochepko 2018-05-11 21:22:28 +03:00
parent 078a1f3a17
commit cae7789afc
1 changed files with 2 additions and 1 deletions
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3
src/hotspot/cpu/aarch64/assembler_aarch64.hpp
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@ -2410,7 +2410,8 @@ public:
#define INSN(NAME, opcode) \
void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
starti; \
f(0, 31), f(0b001110, 29, 24), f(0, 21), f(0b001110, 15, 10); \
f(0, 31), f(0b001110, 29, 24), f(0, 21), f(0, 15); \
f(opcode, 14, 12), f(0b10, 11, 10); \
rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); \
f(T & 1, 30), f(T >> 1, 23, 22); \
}