6997311: SIGFPE in new long division asm code
Use unsigned DIV instruction Reviewed-by: never
This commit is contained in:
Vladimir Kozlov
parent
085e1ad6e1
commit
ce2df719c6
@ -1275,6 +1275,12 @@ void Assembler::idivl(Register src) {
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emit_byte(0xF8 | encode);
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}
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void Assembler::divl(Register src) { // Unsigned
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int encode = prefix_and_encode(src->encoding());
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emit_byte(0xF7);
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emit_byte(0xF0 | encode);
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}
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void Assembler::imull(Register dst, Register src) {
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int encode = prefix_and_encode(dst->encoding(), src->encoding());
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emit_byte(0x0F);
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@ -1011,6 +1011,7 @@ private:
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void hlt();
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void idivl(Register src);
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void divl(Register src); // Unsigned division
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void idivq(Register src);
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@ -8863,48 +8863,64 @@ instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlag
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effect( TEMP tmp, TEMP tmp2, KILL cr );
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ins_cost(1000);
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format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
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"XOR $tmp2,$tmp2\n\t"
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"CMP $tmp,EDX\n\t"
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"JA,s fast\n\t"
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"MOV $tmp2,EAX\n\t"
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"MOV EAX,EDX\n\t"
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"SAR EDX,31\n\t"
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"IDIV $tmp\n\t"
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"XCHG EAX,$tmp2 \n\t"
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"IDIV $tmp\n\t"
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"CDQ\n\t"
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"ADD EDX,$tmp2\n\t"
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"MOV EDX,0\n\t"
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"JLE,s pos\n\t"
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"LNEG EAX : $tmp2\n\t"
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"DIV $tmp # unsigned division\n\t"
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"XCHG EAX,$tmp2\n\t"
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"DIV $tmp\n\t"
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"LNEG $tmp2 : EAX\n\t"
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"JMP,s done\n"
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"pos:\n\t"
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"DIV $tmp\n\t"
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"XCHG EAX,$tmp2\n"
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"fast:\n\t"
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"IDIV $tmp\n\t"
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"XOR EDX,EDX\n"
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"DIV $tmp\n"
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"done:\n\t"
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"MOV EDX,$tmp2\n\t"
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"NEG EDX:EAX # if $imm < 0" %}
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ins_encode %{
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int con = (int)$imm$$constant;
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assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
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int pcon = (con > 0) ? con : -con;
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Label Lfast, Ldone;
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Label Lfast, Lpos, Ldone;
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__ movl($tmp$$Register, pcon);
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__ xorl($tmp2$$Register,$tmp2$$Register);
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__ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
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__ jccb(Assembler::above, Lfast);
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__ jccb(Assembler::above, Lfast); // result fits into 32 bit
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__ movl($tmp2$$Register, $dst$$Register); // save
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__ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
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__ sarl(HIGH_FROM_LOW($dst$$Register), 31); // src sign
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__ idivl($tmp$$Register);
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__ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
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__ jccb(Assembler::lessEqual, Lpos); // result is positive
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// Negative dividend.
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// convert value to positive to use unsigned division
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__ lneg($dst$$Register, $tmp2$$Register);
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__ divl($tmp$$Register);
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__ xchgl($dst$$Register, $tmp2$$Register);
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__ idivl($tmp$$Register);
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__ cdql();
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__ addl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
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__ divl($tmp$$Register);
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// revert result back to negative
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__ lneg($tmp2$$Register, $dst$$Register);
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__ jmpb(Ldone);
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__ bind(Lpos);
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__ divl($tmp$$Register); // Use unsigned division
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__ xchgl($dst$$Register, $tmp2$$Register);
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// Fallthrow for final divide, tmp2 has 32 bit hi result
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__ bind(Lfast);
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// fast path: src is positive and result fits into 32 bit
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__ idivl($tmp$$Register);
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__ xorl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
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// fast path: src is positive
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__ divl($tmp$$Register); // Use unsigned division
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__ bind(Ldone);
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__ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
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if (con < 0) {
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__ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
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}
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@ -8922,18 +8938,27 @@ instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlag
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"JA,s fast\n\t"
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"MOV $tmp2,EAX\n\t"
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"MOV EAX,EDX\n\t"
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"SAR EDX,31\n\t"
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"IDIV $tmp\n\t"
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"MOV EDX,0\n\t"
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"JLE,s pos\n\t"
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"LNEG EAX : $tmp2\n\t"
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"DIV $tmp # unsigned division\n\t"
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"MOV EAX,$tmp2\n\t"
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"DIV $tmp\n\t"
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"NEG EDX\n\t"
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"JMP,s done\n"
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"pos:\n\t"
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"DIV $tmp\n\t"
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"MOV EAX,$tmp2\n"
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"fast:\n\t"
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"IDIV $tmp\n\t"
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"DIV $tmp\n"
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"done:\n\t"
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"MOV EAX,EDX\n\t"
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"SAR EDX,31\n\t" %}
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ins_encode %{
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int con = (int)$imm$$constant;
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assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
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int pcon = (con > 0) ? con : -con;
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Label Lfast;
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Label Lfast, Lpos, Ldone;
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__ movl($tmp$$Register, pcon);
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__ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
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@ -8941,12 +8966,28 @@ instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlag
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__ movl($tmp2$$Register, $dst$$Register); // save
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__ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
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__ sarl(HIGH_FROM_LOW($dst$$Register), 31); // src sign
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__ idivl($tmp$$Register);
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__ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
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__ jccb(Assembler::lessEqual, Lpos); // result is positive
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// Negative dividend.
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// convert value to positive to use unsigned division
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__ lneg($dst$$Register, $tmp2$$Register);
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__ divl($tmp$$Register);
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__ movl($dst$$Register, $tmp2$$Register);
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__ divl($tmp$$Register);
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// revert remainder back to negative
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__ negl(HIGH_FROM_LOW($dst$$Register));
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__ jmpb(Ldone);
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__ bind(Lpos);
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__ divl($tmp$$Register);
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__ movl($dst$$Register, $tmp2$$Register);
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__ bind(Lfast);
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__ idivl($tmp$$Register);
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// fast path: src is positive
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__ divl($tmp$$Register);
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__ bind(Ldone);
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__ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
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__ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2009, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -108,8 +108,10 @@ public class Test implements Runnable {
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if (quo != quo0 || rem != rem0) {
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if (VERBOSE) {
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System.out.println(" " + dividend + " / " + divisor() + " = " +
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quo + ", " + dividend + " % " + divisor() + " = " + rem);
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System.out.println("Computed: " + dividend + " / " + divisor() + " = " +
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quo + ", " + dividend + " % " + divisor() + " = " + rem );
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System.out.println("expected: " + dividend + " / " + divisor() + " = " +
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quo0 + ", " + dividend + " % " + divisor() + " = " + rem0);
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// Report sign of rem failure
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if (rem != 0 && (rem ^ dividend) < 0) {
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System.out.println(" rem & dividend have different signs");
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@ -168,7 +170,7 @@ public class Test implements Runnable {
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for (int i = start; i <= end; i++) {
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for (int s = 0; s < 64; s += 4) {
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total++;
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long dividend = i << s;
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long dividend = ((long)i) << s;
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if (!checkL(dividend)) {
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wrong++;
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// Stop on the first failure
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