8285390: PPC64: Handle integral division overflow during parsing
Reviewed-by: lucy
This commit is contained in:
Martin Doerr
parent
f42631e354
commit
d3606a34fa
47
src/hotspot/cpu/ppc/parse_ppc.cpp
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47
src/hotspot/cpu/ppc/parse_ppc.cpp
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/*
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* Copyright (c) 2022, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#include "precompiled.hpp"
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#ifdef COMPILER2
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#include "opto/parse.hpp"
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#include "interpreter/bytecodes.hpp"
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bool Parse::do_one_bytecode_targeted() {
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switch (bc()) {
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case Bytecodes::_idiv: // fallthrough
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case Bytecodes::_irem: // fallthrough
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#ifdef _LP64
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case Bytecodes::_ldiv: // fallthrough
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case Bytecodes::_lrem:
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#endif
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do_divmod_fixup();
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return true;
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default:
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return false;
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}
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}
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#endif // COMPILER2
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@ -2407,10 +2407,6 @@ const RegMask Matcher::method_handle_invoke_SP_save_mask() {
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return RegMask();
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}
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bool Parse::do_one_bytecode_targeted() {
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return false;
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}
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%}
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//----------ENCODING BLOCK-----------------------------------------------------
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@ -8857,26 +8853,10 @@ instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
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ins_pipe(pipe_class_default);
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%}
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// Integer Division with Immediate -1: Negate.
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instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
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match(Set dst (DivI src1 src2));
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ins_cost(DEFAULT_COST);
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format %{ "NEG $dst, $src1 \t// /-1" %}
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size(4);
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ins_encode %{
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__ neg($dst$$Register, $src1$$Register);
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%}
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ins_pipe(pipe_class_default);
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%}
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// Integer Division with constant, but not -1.
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// We should be able to improve this by checking the type of src2.
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// It might well be that src2 is known to be positive.
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instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
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match(Set dst (DivI src1 src2));
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predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
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ins_cost(2*DEFAULT_COST);
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// Integer Division, but not min_jint / -1
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instruct noOvfDivI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
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match(Set dst (NoOvfDivI src1 src2));
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ins_cost(3*DEFAULT_COST);
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format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
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size(4);
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@ -8886,56 +8866,10 @@ instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
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ins_pipe(pipe_class_default);
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%}
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instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{
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effect(USE_DEF dst, USE src1, USE crx);
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predicate(false);
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ins_variable_size_depending_on_alignment(true);
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format %{ "CMOVE $dst, neg($src1), $crx" %}
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// Worst case is branch + move + stop, no stop without scheduler.
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size(8);
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ins_encode %{
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Label done;
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__ bne($crx$$CondRegister, done);
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__ neg($dst$$Register, $src1$$Register);
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__ bind(done);
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%}
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ins_pipe(pipe_class_default);
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%}
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// Integer Division with Registers not containing constants.
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instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
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match(Set dst (DivI src1 src2));
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ins_cost(10*DEFAULT_COST);
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expand %{
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immI16 imm %{ (int)-1 %}
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flagsReg tmp1;
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cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
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divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
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cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
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%}
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%}
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// Long Division with Immediate -1: Negate.
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instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
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match(Set dst (DivL src1 src2));
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ins_cost(DEFAULT_COST);
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format %{ "NEG $dst, $src1 \t// /-1, long" %}
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size(4);
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ins_encode %{
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__ neg($dst$$Register, $src1$$Register);
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%}
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ins_pipe(pipe_class_default);
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%}
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// Long Division with constant, but not -1.
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instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
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match(Set dst (DivL src1 src2));
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predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
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ins_cost(2*DEFAULT_COST);
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// Long Division, but not min_jlong / -1
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instruct noOvfDivL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
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match(Set dst (NoOvfDivL src1 src2));
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ins_cost(3*DEFAULT_COST);
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format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
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size(4);
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@ -8945,71 +8879,31 @@ instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
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ins_pipe(pipe_class_default);
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%}
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instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{
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effect(USE_DEF dst, USE src1, USE crx);
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predicate(false);
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ins_variable_size_depending_on_alignment(true);
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format %{ "CMOVE $dst, neg($src1), $crx" %}
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// Worst case is branch + move + stop, no stop without scheduler.
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size(8);
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ins_encode %{
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Label done;
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__ bne($crx$$CondRegister, done);
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__ neg($dst$$Register, $src1$$Register);
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__ bind(done);
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%}
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ins_pipe(pipe_class_default);
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%}
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// Long Division with Registers not containing constants.
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instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
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match(Set dst (DivL src1 src2));
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ins_cost(10*DEFAULT_COST);
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expand %{
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immL16 imm %{ (int)-1 %}
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flagsReg tmp1;
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cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
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divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
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cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
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%}
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%}
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// Integer Remainder with registers.
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instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
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match(Set dst (ModI src1 src2));
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ins_cost(10*DEFAULT_COST);
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match(Set dst (NoOvfModI src1 src2));
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ins_cost(5*DEFAULT_COST);
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expand %{
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immI16 imm %{ (int)-1 %}
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flagsReg tmp1;
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iRegIdst tmp1;
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iRegIdst tmp2;
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iRegIdst tmp3;
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cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
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divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
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cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
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mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
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subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
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noOvfDivI_reg_reg(tmp1, src1, src2);
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mulI_reg_reg(tmp2, src2, tmp1);
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subI_reg_reg(dst, src1, tmp2);
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%}
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%}
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// Long Remainder with registers
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instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
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match(Set dst (ModL src1 src2));
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ins_cost(10*DEFAULT_COST);
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match(Set dst (NoOvfModL src1 src2));
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ins_cost(5*DEFAULT_COST);
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expand %{
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immL16 imm %{ (int)-1 %}
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flagsReg tmp1;
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iRegLdst tmp1;
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iRegLdst tmp2;
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iRegLdst tmp3;
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cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
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divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
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cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
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mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
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subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
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noOvfDivL_reg_reg(tmp1, src1, src2);
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mulL_reg_reg(tmp2, src2, tmp1);
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subL_reg_reg(dst, src1, tmp2);
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%}
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%}
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