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8297715: RISC-V: C2: Use single-bit instructions from the Zbs extension

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Reviewed-by: fjiang, yadongwang, shade
This commit is contained in:
Fei Yang 2022-12-02 08:26:22 +00:00
parent 9bbcb546c8
commit d50015af99
4 changed files with 26 additions and 2 deletions
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3
src/hotspot/cpu/riscv/assembler_riscv.hpp
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@ -1670,7 +1670,7 @@ enum Nf {
// ==================================== // ====================================
// RISC-V Bit-Manipulation Extension // RISC-V Bit-Manipulation Extension
// Currently only support Zba and Zbb bitmanip extensions. // Currently only support Zba, Zbb and Zbs bitmanip extensions.
// ==================================== // ====================================
#define INSN(NAME, op, funct3, funct7) \ #define INSN(NAME, op, funct3, funct7) \
void NAME(Register Rd, Register Rs1, Register Rs2) { \ void NAME(Register Rd, Register Rs1, Register Rs2) { \
@ -1745,6 +1745,7 @@ enum Nf {
INSN(rori, 0b0010011, 0b101, 0b011000); INSN(rori, 0b0010011, 0b101, 0b011000);
INSN(slli_uw, 0b0011011, 0b001, 0b000010); INSN(slli_uw, 0b0011011, 0b001, 0b000010);
INSN(bexti, 0b0010011, 0b101, 0b010010);
#undef INSN #undef INSN

1
src/hotspot/cpu/riscv/globals_riscv.hpp
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@ -102,6 +102,7 @@ define_pd_global(intx, InlineSmallCode, 1000);
product(bool, UseRVV, false, EXPERIMENTAL, "Use RVV instructions") \ product(bool, UseRVV, false, EXPERIMENTAL, "Use RVV instructions") \
product(bool, UseZba, false, EXPERIMENTAL, "Use Zba instructions") \ product(bool, UseZba, false, EXPERIMENTAL, "Use Zba instructions") \
product(bool, UseZbb, false, EXPERIMENTAL, "Use Zbb instructions") \ product(bool, UseZbb, false, EXPERIMENTAL, "Use Zbb instructions") \
product(bool, UseZbs, false, EXPERIMENTAL, "Use Zbs instructions") \
product(bool, UseZic64b, false, EXPERIMENTAL, "Use Zic64b instructions") \ product(bool, UseZic64b, false, EXPERIMENTAL, "Use Zic64b instructions") \
product(bool, UseZicbom, false, EXPERIMENTAL, "Use Zicbom instructions") \ product(bool, UseZicbom, false, EXPERIMENTAL, "Use Zicbom instructions") \
product(bool, UseZicbop, false, EXPERIMENTAL, "Use Zicbop instructions") \ product(bool, UseZicbop, false, EXPERIMENTAL, "Use Zicbop instructions") \

8
src/hotspot/cpu/riscv/riscv.ad
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@ -2984,6 +2984,14 @@ operand immI_16bits()
interface(CONST_INTER); interface(CONST_INTER);
%} %}
operand immIpowerOf2() %{
predicate(is_power_of_2((juint)(n->get_int())));
match(ConI);
op_cost(0);
format %{ %}
interface(CONST_INTER);
%}
// Long Immediate: low 32-bit mask // Long Immediate: low 32-bit mask
operand immL_32bits() operand immL_32bits()
%{ %{

14
src/hotspot/cpu/riscv/riscv_b.ad
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@ -525,3 +525,17 @@ instruct ornL_reg_reg_b(iRegLNoSp dst, iRegL src1, iRegL src2, immL_M1 m1) %{
ins_pipe(ialu_reg_reg); ins_pipe(ialu_reg_reg);
%} %}
// AndI 0b0..010..0 + ConvI2B
instruct convI2Bool_andI_reg_immIpowerOf2(iRegINoSp dst, iRegIorL2I src, immIpowerOf2 mask) %{
predicate(UseZbs);
match(Set dst (Conv2B (AndI src mask)));
ins_cost(ALU_COST);
format %{ "bexti $dst, $src, $mask\t#@convI2Bool_andI_reg_immIpowerOf2" %}
ins_encode %{
__ bexti($dst$$Register, $src$$Register, exact_log2((juint)($mask$$constant)));
%}
ins_pipe(ialu_reg_reg);
%}