8241874: [PPC64]: Improve performance of Long.reverseBytes() and Integer.reverseBytes() on Power9
Reviewed-by: mdoerr, mhorie
This commit is contained in:
Corey Ashford
Michihiro Horie
parent
0d09d682a4
commit
d945999862
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2002, 2019, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2012, 2018 SAP SE. All rights reserved.
|
||||
* Copyright (c) 2002, 2020, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2012, 2020 SAP SE. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -530,6 +530,8 @@ class Assembler : public AbstractAssembler {
|
||||
XXLXOR_OPCODE = (60u << OPCODE_SHIFT | 154u << 3),
|
||||
XXLEQV_OPCODE = (60u << OPCODE_SHIFT | 186u << 3),
|
||||
XVDIVSP_OPCODE = (60u << OPCODE_SHIFT | 88u << 3),
|
||||
XXBRD_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 23u << 16), // XX2-FORM
|
||||
XXBRW_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 15u << 16), // XX2-FORM
|
||||
XVDIVDP_OPCODE = (60u << OPCODE_SHIFT | 120u << 3),
|
||||
XVABSSP_OPCODE = (60u << OPCODE_SHIFT | 409u << 2),
|
||||
XVABSDP_OPCODE = (60u << OPCODE_SHIFT | 473u << 2),
|
||||
@ -2227,11 +2229,15 @@ class Assembler : public AbstractAssembler {
|
||||
inline void xxmrghw( VectorSRegister d, VectorSRegister a, VectorSRegister b);
|
||||
inline void xxmrglw( VectorSRegister d, VectorSRegister a, VectorSRegister b);
|
||||
inline void mtvsrd( VectorSRegister d, Register a);
|
||||
inline void mfvsrd( Register d, VectorSRegister a);
|
||||
inline void mtvsrwz( VectorSRegister d, Register a);
|
||||
inline void mfvsrwz( Register d, VectorSRegister a);
|
||||
inline void xxspltw( VectorSRegister d, VectorSRegister b, int ui2);
|
||||
inline void xxlor( VectorSRegister d, VectorSRegister a, VectorSRegister b);
|
||||
inline void xxlxor( VectorSRegister d, VectorSRegister a, VectorSRegister b);
|
||||
inline void xxleqv( VectorSRegister d, VectorSRegister a, VectorSRegister b);
|
||||
inline void xxbrd( VectorSRegister d, VectorSRegister b);
|
||||
inline void xxbrw( VectorSRegister d, VectorSRegister b);
|
||||
inline void xvdivsp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
|
||||
inline void xvdivdp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
|
||||
inline void xvabssp( VectorSRegister d, VectorSRegister b);
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2002, 2019, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2012, 2018 SAP SE. All rights reserved.
|
||||
* Copyright (c) 2002, 2020, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2012, 2020 SAP SE. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -776,11 +776,15 @@ inline void Assembler::lxvd2x( VectorSRegister d, Register s1, Register s2) { e
|
||||
inline void Assembler::stxvd2x( VectorSRegister d, Register s1) { emit_int32( STXVD2X_OPCODE | vsrs(d) | ra(0) | rb(s1)); }
|
||||
inline void Assembler::stxvd2x( VectorSRegister d, Register s1, Register s2) { emit_int32( STXVD2X_OPCODE | vsrs(d) | ra0mem(s1) | rb(s2)); }
|
||||
inline void Assembler::mtvsrd( VectorSRegister d, Register a) { emit_int32( MTVSRD_OPCODE | vsrt(d) | ra(a)); }
|
||||
inline void Assembler::mfvsrd( Register d, VectorSRegister a) { emit_int32( MFVSRD_OPCODE | vsrs(a) | ra(d)); }
|
||||
inline void Assembler::mtvsrwz( VectorSRegister d, Register a) { emit_int32( MTVSRWZ_OPCODE | vsrt(d) | ra(a)); }
|
||||
inline void Assembler::mfvsrwz( Register d, VectorSRegister a) { emit_int32( MFVSRWZ_OPCODE | vsrs(a) | ra(d)); }
|
||||
inline void Assembler::xxspltw( VectorSRegister d, VectorSRegister b, int ui2) { emit_int32( XXSPLTW_OPCODE | vsrt(d) | vsrb(b) | xxsplt_uim(uimm(ui2,2))); }
|
||||
inline void Assembler::xxlor( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXLOR_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
|
||||
inline void Assembler::xxlxor( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXLXOR_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
|
||||
inline void Assembler::xxleqv( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXLEQV_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
|
||||
inline void Assembler::xxbrd( VectorSRegister d, VectorSRegister b) { emit_int32( XXBRD_OPCODE | vsrt(d) | vsrb(b) ); }
|
||||
inline void Assembler::xxbrw( VectorSRegister d, VectorSRegister b) { emit_int32( XXBRW_OPCODE | vsrt(d) | vsrb(b) ); }
|
||||
inline void Assembler::xvdivsp( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XVDIVSP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
|
||||
inline void Assembler::xvdivdp( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XVDIVDP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
|
||||
inline void Assembler::xvabssp( VectorSRegister d, VectorSRegister b) { emit_int32( XVABSSP_OPCODE | vsrt(d) | vsrb(b)); }
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2002, 2020, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2012, 2018 SAP SE. All rights reserved.
|
||||
* Copyright (c) 2012, 2020 SAP SE. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -112,6 +112,8 @@ define_pd_global(intx, InitArrayShortSize, 9*BytesPerLong);
|
||||
"Use load instructions for stack banging.") \
|
||||
\
|
||||
/* special instructions */ \
|
||||
product(bool, UseVectorByteReverseInstructionsPPC64, false, \
|
||||
"Use Power9 xxbr* vector byte reverse instructions.") \
|
||||
\
|
||||
product(bool, UseCountLeadingZerosInstructionsPPC64, true, \
|
||||
"Use count leading zeros instructions.") \
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
//
|
||||
// Copyright (c) 2011, 2020, Oracle and/or its affiliates. All rights reserved.
|
||||
// Copyright (c) 2012, 2019 SAP SE. All rights reserved.
|
||||
// Copyright (c) 2012, 2020 SAP SE. All rights reserved.
|
||||
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
//
|
||||
// This code is free software; you can redistribute it and/or modify it
|
||||
@ -13732,6 +13732,24 @@ instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
|
||||
%}
|
||||
%}
|
||||
|
||||
instruct bytes_reverse_int_vec(iRegIdst dst, iRegIsrc src, vecX tmpV) %{
|
||||
match(Set dst (ReverseBytesI src));
|
||||
predicate(UseVectorByteReverseInstructionsPPC64);
|
||||
effect(TEMP tmpV);
|
||||
ins_cost(DEFAULT_COST*3);
|
||||
size(12);
|
||||
format %{ "MTVSRWZ $tmpV, $src\n"
|
||||
"\tXXBRW $tmpV, $tmpV\n"
|
||||
"\tMFVSRWZ $dst, $tmpV" %}
|
||||
|
||||
ins_encode %{
|
||||
__ mtvsrwz($tmpV$$VectorSRegister, $src$$Register);
|
||||
__ xxbrw($tmpV$$VectorSRegister, $tmpV$$VectorSRegister);
|
||||
__ mfvsrwz($dst$$Register, $tmpV$$VectorSRegister);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
instruct bytes_reverse_long_Ex(iRegLdst dst, iRegLsrc src) %{
|
||||
match(Set dst (ReverseBytesL src));
|
||||
ins_cost(15*DEFAULT_COST);
|
||||
@ -13771,6 +13789,24 @@ instruct bytes_reverse_long_Ex(iRegLdst dst, iRegLsrc src) %{
|
||||
%}
|
||||
%}
|
||||
|
||||
instruct bytes_reverse_long_vec(iRegLdst dst, iRegLsrc src, vecX tmpV) %{
|
||||
match(Set dst (ReverseBytesL src));
|
||||
predicate(UseVectorByteReverseInstructionsPPC64);
|
||||
effect(TEMP tmpV);
|
||||
ins_cost(DEFAULT_COST*3);
|
||||
size(12);
|
||||
format %{ "MTVSRD $tmpV, $src\n"
|
||||
"\tXXBRD $tmpV, $tmpV\n"
|
||||
"\tMFVSRD $dst, $tmpV" %}
|
||||
|
||||
ins_encode %{
|
||||
__ mtvsrd($tmpV$$VectorSRegister, $src$$Register);
|
||||
__ xxbrd($tmpV$$VectorSRegister, $tmpV$$VectorSRegister);
|
||||
__ mfvsrd($dst$$Register, $tmpV$$VectorSRegister);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
instruct bytes_reverse_ushort_Ex(iRegIdst dst, iRegIsrc src) %{
|
||||
match(Set dst (ReverseBytesUS src));
|
||||
ins_cost(2*DEFAULT_COST);
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2012, 2019 SAP SE. All rights reserved.
|
||||
* Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2012, 2020 SAP SE. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -141,6 +141,9 @@ void VM_Version::initialize() {
|
||||
if (FLAG_IS_DEFAULT(UseCharacterCompareIntrinsics)) {
|
||||
FLAG_SET_ERGO(UseCharacterCompareIntrinsics, true);
|
||||
}
|
||||
if (FLAG_IS_DEFAULT(UseVectorByteReverseInstructionsPPC64)) {
|
||||
FLAG_SET_ERGO(UseVectorByteReverseInstructionsPPC64, true);
|
||||
}
|
||||
} else {
|
||||
if (UseCountTrailingZerosInstructionsPPC64) {
|
||||
warning("UseCountTrailingZerosInstructionsPPC64 specified, but needs at least Power9.");
|
||||
@ -150,6 +153,10 @@ void VM_Version::initialize() {
|
||||
warning("UseCharacterCompareIntrinsics specified, but needs at least Power9.");
|
||||
FLAG_SET_DEFAULT(UseCharacterCompareIntrinsics, false);
|
||||
}
|
||||
if (UseVectorByteReverseInstructionsPPC64) {
|
||||
warning("UseVectorByteReverseInstructionsPPC64 specified, but needs at least Power9.");
|
||||
FLAG_SET_DEFAULT(UseVectorByteReverseInstructionsPPC64, false);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user