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8318827: RISC-V: Improve readability of fclass result testing

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Reviewed-by: vkempik, luhenry, fyang
This commit is contained in:
Feilong Jiang 2023-10-29 10:15:41 +00:00
parent 1ec0d02717
commit db3402577a
4 changed files with 28 additions and 13 deletions
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21
src/hotspot/cpu/riscv/assembler_riscv.hpp
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@ -1074,7 +1074,26 @@ enum operand_size { int8, int16, int32, uint32, int64 };
#undef INSN
// Float and Double Conversion Instruction
enum fclass_mask {
minf = 1 << 0, // negative infinite
mnorm = 1 << 1, // negative normal number
msubnorm = 1 << 2, // negative subnormal number
mzero = 1 << 3, // negative zero
pzero = 1 << 4, // positive zero
psubnorm = 1 << 5, // positive subnormal number
pnorm = 1 << 6, // positive normal number
pinf = 1 << 7, // positive infinite
snan = 1 << 8, // signaling NaN
qnan = 1 << 9, // quiet NaN
zero = mzero | pzero,
subnorm = msubnorm | psubnorm,
norm = mnorm | pnorm,
inf = minf | pinf,
nan = snan | qnan,
finite = zero | subnorm | norm,
};
// Float and Double Conversion/Classify Instruction
#define INSN(NAME, op, funct3, funct5, funct7) \
void NAME(Register Rd, FloatRegister Rs1) { \
unsigned insn = 0; \

10
src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
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@ -1571,7 +1571,7 @@ void C2_MacroAssembler::minmax_fp(FloatRegister dst, FloatRegister src1, FloatRe
is_double ? fclass_d(t1, src2)
: fclass_s(t1, src2);
orr(t0, t0, t1);
andi(t0, t0, 0b1100000000); //if src1 or src2 is quiet or signaling NaN then return NaN
andi(t0, t0, fclass_mask::nan); // if src1 or src2 is quiet or signaling NaN then return NaN
beqz(t0, Compare);
is_double ? fadd_d(dst, src1, src2)
: fadd_s(dst, src1, src2);
@ -1669,12 +1669,8 @@ void C2_MacroAssembler::signum_fp(FloatRegister dst, FloatRegister src, FloatReg
is_double ? fmv_d(dst, src)
: fmv_s(dst, src);
//bitmask 0b1100011000 specifies this bits:
// 3 - src is -0
// 4 - src is +0
// 8 - src is signaling NaN
// 9 - src is a quiet NaN
andi(tmp1, tmp1, 0b1100011000);
// check if input is -0, +0, signaling NaN or quiet NaN
andi(tmp1, tmp1, fclass_mask::zero | fclass_mask::nan);
bnez(tmp1, done);

2
src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
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@ -4246,7 +4246,7 @@ void MacroAssembler::FLOATCVT##_safe(Register dst, FloatRegister src, Register t
fclass_##FLOATSIG(tmp, src); \
mv(dst, zr); \
/* check if src is NaN */ \
andi(tmp, tmp, 0b1100000000); \
andi(tmp, tmp, fclass_mask::nan); \
bnez(tmp, done); \
FLOATCVT(dst, src); \
bind(done); \

8
src/hotspot/cpu/riscv/riscv.ad
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@ -7361,7 +7361,7 @@ instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
format %{ "isInfinite $dst, $src" %}
ins_encode %{
__ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), 0b0010000001);
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::fclass_mask::inf);
__ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
%}
@ -7376,7 +7376,7 @@ instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
format %{ "isInfinite $dst, $src" %}
ins_encode %{
__ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), 0b0010000001);
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::fclass_mask::inf);
__ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
%}
@ -7391,7 +7391,7 @@ instruct isFiniteF_reg_reg(iRegINoSp dst, fRegF src)
format %{ "isFinite $dst, $src" %}
ins_encode %{
__ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), 0b0001111110);
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::fclass_mask::finite);
__ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
%}
@ -7406,7 +7406,7 @@ instruct isFiniteD_reg_reg(iRegINoSp dst, fRegD src)
format %{ "isFinite $dst, $src" %}
ins_encode %{
__ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), 0b0001111110);
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::fclass_mask::finite);
__ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
%}