8044242: Remove dead NativeMovRegMemPatching class
Reviewed-by: twisti, kvn
This commit is contained in:
Mikael Vidstedt
parent
4c5c9f2ce7
commit
e09b9cbc3c
@ -690,149 +690,6 @@ void NativeMovRegMem::test() {
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// End code for unit testing implementation of NativeMovRegMem class
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//--------------------------------------------------------------------------------
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void NativeMovRegMemPatching::copy_instruction_to(address new_instruction_address) {
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Untested("copy_instruction_to");
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int instruction_size = next_instruction_address() - instruction_address();
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for (int i = 0; i < instruction_size; i += wordSize) {
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*(long*)(new_instruction_address + i) = *(long*)(address(this) + i);
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}
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}
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void NativeMovRegMemPatching::verify() {
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NativeInstruction::verify();
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// make sure code pattern is actually a "ld" or "st" of some sort.
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int i0 = long_at(0);
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int op3 = inv_op3(i0);
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assert((int)nop_offset == (int)NativeMovConstReg::add_offset, "sethi size ok");
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if (!(is_op(i0, Assembler::ldst_op) &&
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inv_immed(i0) &&
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0 != (op3 < op3_ldst_int_limit
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? (1 << op3 ) & (op3_mask_ld | op3_mask_st)
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: (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf)))) {
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int i1 = long_at(ldst_offset);
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Register rd = inv_rd(i0);
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op3 = inv_op3(i1);
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if (!is_op(i1, Assembler::ldst_op) && rd == inv_rs2(i1) &&
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0 != (op3 < op3_ldst_int_limit
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? (1 << op3 ) & (op3_mask_ld | op3_mask_st)
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: (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf))) {
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fatal("not a ld* or st* op");
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}
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}
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}
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void NativeMovRegMemPatching::print() {
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if (is_immediate()) {
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tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + %d]", p2i(instruction_address()), offset());
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} else {
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tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + reg]", p2i(instruction_address()));
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}
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}
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// Code for unit testing implementation of NativeMovRegMemPatching class
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void NativeMovRegMemPatching::test() {
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#ifdef ASSERT
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ResourceMark rm;
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CodeBuffer cb("test", 1000, 1000);
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MacroAssembler* a = new MacroAssembler(&cb);
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NativeMovRegMemPatching* nm;
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uint idx = 0;
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uint idx1;
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int offsets[] = {
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0x0,
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0xffffffff,
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0x7fffffff,
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0x80000000,
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4096,
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4097,
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0x20,
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0x4000,
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};
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VM_Version::allow_all();
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AddressLiteral al(0xffffffff, relocInfo::external_word_type);
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a->ldsw( G5, al.low10(), G4); idx++;
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a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
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a->ldsw( G5, I3, G4 ); idx++;
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a->ldsb( G5, al.low10(), G4); idx++;
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a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
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a->ldsb( G5, I3, G4 ); idx++;
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a->ldsh( G5, al.low10(), G4); idx++;
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a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
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a->ldsh( G5, I3, G4 ); idx++;
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a->lduw( G5, al.low10(), G4); idx++;
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a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
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a->lduw( G5, I3, G4 ); idx++;
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a->ldub( G5, al.low10(), G4); idx++;
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a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
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a->ldub( G5, I3, G4 ); idx++;
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a->lduh( G5, al.low10(), G4); idx++;
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a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
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a->lduh( G5, I3, G4 ); idx++;
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a->ldx( G5, al.low10(), G4); idx++;
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a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
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a->ldx( G5, I3, G4 ); idx++;
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a->ldd( G5, al.low10(), G4); idx++;
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a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
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a->ldd( G5, I3, G4 ); idx++;
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a->ldf( FloatRegisterImpl::D, O2, -1, F14 ); idx++;
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a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
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a->ldf( FloatRegisterImpl::S, O0, I3, F15 ); idx++;
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a->stw( G5, G4, al.low10()); idx++;
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a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
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a->stw( G5, G4, I3 ); idx++;
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a->stb( G5, G4, al.low10()); idx++;
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a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
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a->stb( G5, G4, I3 ); idx++;
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a->sth( G5, G4, al.low10()); idx++;
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a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
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a->sth( G5, G4, I3 ); idx++;
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a->stx( G5, G4, al.low10()); idx++;
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a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
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a->stx( G5, G4, I3 ); idx++;
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a->std( G5, G4, al.low10()); idx++;
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a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
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a->std( G5, G4, I3 ); idx++;
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a->stf( FloatRegisterImpl::S, F18, O2, -1 ); idx++;
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a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
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a->stf( FloatRegisterImpl::S, F15, O0, I3 ); idx++;
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nm = nativeMovRegMemPatching_at( cb.insts_begin() );
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nm->print();
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nm->set_offset( low10(0) );
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nm->print();
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nm->add_offset_in_bytes( low10(0xbb) * wordSize );
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nm->print();
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while (--idx) {
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nm = nativeMovRegMemPatching_at( nm->next_instruction_address() );
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nm->print();
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for (idx1 = 0; idx1 < ARRAY_SIZE(offsets); idx1++) {
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nm->set_offset( nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1] );
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assert(nm->offset() == (nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1]),
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"check unit test");
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nm->print();
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}
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nm->add_offset_in_bytes( low10(0xbb) * wordSize );
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nm->print();
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}
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VM_Version::revert();
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#endif // ASSERT
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}
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// End code for unit testing implementation of NativeMovRegMemPatching class
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//--------------------------------------------------------------------------------
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@ -38,7 +38,6 @@
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// - - NativeMovConstReg
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// - - NativeMovConstRegPatching
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// - - NativeMovRegMem
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// - - NativeMovRegMemPatching
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// - - NativeJump
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// - - NativeGeneralJump
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// - - NativeIllegalInstruction
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@ -710,96 +709,6 @@ class NativeMovRegMem: public NativeInstruction {
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};
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// An interface for accessing/manipulating native memory ops
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// ld* [reg + offset], reg
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// st* reg, [reg + offset]
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// sethi %hi(imm), reg; nop; add reg, %lo(imm), reg; ld* [reg1 + reg], reg2
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// sethi %hi(imm), reg; nop; add reg, %lo(imm), reg; st* reg2, [reg1 + reg]
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// Ops covered: {lds,ldu,st}{w,b,h}, {ld,st}{d,x}
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//
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// Note that it is identical to NativeMovRegMem with the exception of a nop between the
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// sethi and the add. The nop is required to be in the delay slot of the call instruction
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// which overwrites the sethi during patching.
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class NativeMovRegMemPatching;
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inline NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address);
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class NativeMovRegMemPatching: public NativeInstruction {
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public:
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enum Sparc_specific_constants {
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op3_mask_ld = 1 << Assembler::lduw_op3 |
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1 << Assembler::ldub_op3 |
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1 << Assembler::lduh_op3 |
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1 << Assembler::ldd_op3 |
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1 << Assembler::ldsw_op3 |
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1 << Assembler::ldsb_op3 |
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1 << Assembler::ldsh_op3 |
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1 << Assembler::ldx_op3,
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op3_mask_st = 1 << Assembler::stw_op3 |
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1 << Assembler::stb_op3 |
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1 << Assembler::sth_op3 |
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1 << Assembler::std_op3 |
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1 << Assembler::stx_op3,
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op3_ldst_int_limit = Assembler::ldf_op3,
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op3_mask_ldf = 1 << (Assembler::ldf_op3 - op3_ldst_int_limit) |
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1 << (Assembler::lddf_op3 - op3_ldst_int_limit),
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op3_mask_stf = 1 << (Assembler::stf_op3 - op3_ldst_int_limit) |
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1 << (Assembler::stdf_op3 - op3_ldst_int_limit),
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offset_width = 13,
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sethi_offset = 0,
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#ifdef _LP64
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nop_offset = 7 * BytesPerInstWord,
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#else
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nop_offset = 4,
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#endif
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add_offset = nop_offset + BytesPerInstWord,
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ldst_offset = add_offset + BytesPerInstWord
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};
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bool is_immediate() const {
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// check if instruction is ld* [reg + offset], reg or st* reg, [reg + offset]
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int i0 = long_at(0);
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return (is_op(i0, Assembler::ldst_op));
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}
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address instruction_address() const { return addr_at(0); }
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address next_instruction_address() const {
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return addr_at(is_immediate()? 4 : 16);
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}
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int offset() const {
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return is_immediate()? inv_simm(long_at(0), offset_width) :
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nativeMovConstRegPatching_at(addr_at(0))->data();
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}
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void set_offset(int x) {
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if (is_immediate()) {
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guarantee(fits_in_simm(x, offset_width), "data block offset overflow");
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set_long_at(0, set_simm(long_at(0), x, offset_width));
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}
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else
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nativeMovConstRegPatching_at(addr_at(0))->set_data(x);
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}
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void add_offset_in_bytes(intptr_t radd_offset) {
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set_offset (offset() + radd_offset);
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}
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void copy_instruction_to(address new_instruction_address);
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void verify();
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void print ();
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// unit test stuff
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static void test();
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private:
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friend inline NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) {
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NativeMovRegMemPatching* test = (NativeMovRegMemPatching*)address;
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#ifdef ASSERT
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test->verify();
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#endif
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return test;
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}
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};
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// An interface for accessing/manipulating native jumps
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// jump_to addr
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// == sethi %hi22(addr), temp ; jumpl reg, %lo10(addr), G0 ; <delay>
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@ -327,18 +327,6 @@ inline NativeMovRegMem* nativeMovRegMem_at (address address) {
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return test;
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}
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class NativeMovRegMemPatching: public NativeMovRegMem {
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private:
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friend NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) {
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NativeMovRegMemPatching* test = (NativeMovRegMemPatching*)(address - instruction_offset);
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#ifdef ASSERT
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test->verify();
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#endif
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return test;
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}
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};
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// An interface for accessing/manipulating native leal instruction of form:
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// leal reg, [reg + offset]
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