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8215888: Register to register spill may use AVX 512 move instruction on unsupported platform

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Reviewed-by: vlivanov, thartmann
This commit is contained in:
Sandhya Viswanathan 2019-01-03 14:55:13 -08:00
parent a97d8a9a76
commit e1071d80bd
2 changed files with 14 additions and 14 deletions
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4
src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp
View File

@ -649,7 +649,7 @@ void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_cod
case T_FLOAT: {
if (dest->is_single_xmm()) {
if (LP64_ONLY(UseAVX < 2 &&) c->is_zero_float()) {
if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
__ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
} else {
__ movflt(dest->as_xmm_float_reg(),
@ -671,7 +671,7 @@ void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_cod
case T_DOUBLE: {
if (dest->is_double_xmm()) {
if (LP64_ONLY(UseAVX < 2 &&) c->is_zero_double()) {
if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
__ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
} else {
__ movdbl(dest->as_xmm_double_reg(),

24
src/hotspot/cpu/x86/x86.ad
View File

@ -2924,11 +2924,11 @@ instruct MoveVecX2Leg(legVecX dst, vecX src) %{
match(Set dst src);
format %{ "movdqu $dst,$src\t! load vector (16 bytes)" %}
ins_encode %{
if (UseAVX < 2 || VM_Version::supports_avx512vl()) {
__ movdqu($dst$$XMMRegister, $src$$XMMRegister);
} else {
if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
int vector_len = 2;
__ evmovdquq($dst$$XMMRegister, $src$$XMMRegister, vector_len);
} else {
__ movdqu($dst$$XMMRegister, $src$$XMMRegister);
}
%}
ins_pipe( fpu_reg_reg );
@ -2939,11 +2939,11 @@ instruct MoveLeg2VecX(vecX dst, legVecX src) %{
match(Set dst src);
format %{ "movdqu $dst,$src\t! load vector (16 bytes)" %}
ins_encode %{
if (UseAVX < 2 || VM_Version::supports_avx512vl()) {
__ movdqu($dst$$XMMRegister, $src$$XMMRegister);
} else {
if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
int vector_len = 2;
__ evmovdquq($dst$$XMMRegister, $src$$XMMRegister, vector_len);
} else {
__ movdqu($dst$$XMMRegister, $src$$XMMRegister);
}
%}
ins_pipe( fpu_reg_reg );
@ -2966,11 +2966,11 @@ instruct MoveVecY2Leg(legVecY dst, vecY src) %{
match(Set dst src);
format %{ "vmovdqu $dst,$src\t! load vector (32 bytes)" %}
ins_encode %{
if (UseAVX < 2 || VM_Version::supports_avx512vl()) {
__ vmovdqu($dst$$XMMRegister, $src$$XMMRegister);
} else {
if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
int vector_len = 2;
__ evmovdquq($dst$$XMMRegister, $src$$XMMRegister, vector_len);
} else {
__ vmovdqu($dst$$XMMRegister, $src$$XMMRegister);
}
%}
ins_pipe( fpu_reg_reg );
@ -2981,11 +2981,11 @@ instruct MoveLeg2VecY(vecY dst, legVecY src) %{
match(Set dst src);
format %{ "vmovdqu $dst,$src\t! load vector (32 bytes)" %}
ins_encode %{
if (UseAVX < 2 || VM_Version::supports_avx512vl()) {
__ vmovdqu($dst$$XMMRegister, $src$$XMMRegister);
} else {
if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
int vector_len = 2;
__ evmovdquq($dst$$XMMRegister, $src$$XMMRegister, vector_len);
} else {
__ vmovdqu($dst$$XMMRegister, $src$$XMMRegister);
}
%}
ins_pipe( fpu_reg_reg );