8141633: Implement VarHandles/Unsafe intrinsics on AArch64
Reviewed-by: roland
This commit is contained in:
parent
3e441ea1a2
commit
e22a63d1c6
hotspot/src/cpu/aarch64/vm
@ -1942,12 +1942,35 @@ source %{
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bool is_CAS(int opcode)
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{
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return (opcode == Op_CompareAndSwapI ||
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opcode == Op_CompareAndSwapL ||
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opcode == Op_CompareAndSwapN ||
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opcode == Op_CompareAndSwapP);
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switch(opcode) {
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// We handle these
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case Op_CompareAndSwapI:
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case Op_CompareAndSwapL:
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case Op_CompareAndSwapP:
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case Op_CompareAndSwapN:
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// case Op_CompareAndSwapB:
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// case Op_CompareAndSwapS:
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return true;
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// These are TBD
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case Op_WeakCompareAndSwapB:
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case Op_WeakCompareAndSwapS:
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case Op_WeakCompareAndSwapI:
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case Op_WeakCompareAndSwapL:
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case Op_WeakCompareAndSwapP:
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case Op_WeakCompareAndSwapN:
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case Op_CompareAndExchangeB:
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case Op_CompareAndExchangeS:
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case Op_CompareAndExchangeI:
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case Op_CompareAndExchangeL:
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case Op_CompareAndExchangeP:
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case Op_CompareAndExchangeN:
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return false;
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default:
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return false;
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}
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}
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// leading_to_trailing
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//
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//graph traversal helper which detects the normal case Mem feed from
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@ -4238,14 +4261,16 @@ encode %{
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MacroAssembler _masm(&cbuf);
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guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
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__ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
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Assembler::xword, /*acquire*/ false, /*release*/ true);
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Assembler::xword, /*acquire*/ false, /*release*/ true,
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/*weak*/ false, noreg);
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%}
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enc_class aarch64_enc_cmpxchgw(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
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MacroAssembler _masm(&cbuf);
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guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
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__ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
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Assembler::word, /*acquire*/ false, /*release*/ true);
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Assembler::word, /*acquire*/ false, /*release*/ true,
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/*weak*/ false, noreg);
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%}
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@ -4257,14 +4282,16 @@ encode %{
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MacroAssembler _masm(&cbuf);
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guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
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__ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
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Assembler::xword, /*acquire*/ true, /*release*/ true);
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Assembler::xword, /*acquire*/ true, /*release*/ true,
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/*weak*/ false, noreg);
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%}
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enc_class aarch64_enc_cmpxchgw_acq(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
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MacroAssembler _masm(&cbuf);
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guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
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__ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
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Assembler::word, /*acquire*/ true, /*release*/ true);
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Assembler::word, /*acquire*/ true, /*release*/ true,
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/*weak*/ false, noreg);
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%}
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@ -5803,6 +5830,7 @@ operand iRegLNoSp()
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%{
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constraint(ALLOC_IN_RC(no_special_reg));
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match(RegL);
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match(iRegL_R0);
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format %{ %}
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interface(REG_INTER);
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%}
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@ -5924,6 +5952,39 @@ operand iRegP_R10()
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interface(REG_INTER);
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%}
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// Long 64 bit Register R0 only
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operand iRegL_R0()
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%{
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constraint(ALLOC_IN_RC(r0_reg));
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match(RegL);
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match(iRegLNoSp);
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op_cost(0);
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format %{ %}
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interface(REG_INTER);
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%}
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// Long 64 bit Register R2 only
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operand iRegL_R2()
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%{
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constraint(ALLOC_IN_RC(r2_reg));
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match(RegL);
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match(iRegLNoSp);
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op_cost(0);
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format %{ %}
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interface(REG_INTER);
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%}
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// Long 64 bit Register R3 only
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operand iRegL_R3()
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%{
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constraint(ALLOC_IN_RC(r3_reg));
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match(RegL);
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match(iRegLNoSp);
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op_cost(0);
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format %{ %}
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interface(REG_INTER);
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%}
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// Long 64 bit Register R11 only
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operand iRegL_R11()
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%{
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@ -5980,7 +6041,7 @@ operand iRegI_R3()
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%}
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// Register R2 only
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// Register R4 only
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operand iRegI_R4()
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%{
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constraint(ALLOC_IN_RC(int_r4_reg));
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@ -6004,6 +6065,33 @@ operand iRegN()
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interface(REG_INTER);
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%}
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operand iRegN_R0()
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%{
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constraint(ALLOC_IN_RC(r0_reg));
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match(iRegN);
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op_cost(0);
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format %{ %}
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interface(REG_INTER);
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%}
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operand iRegN_R2()
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%{
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constraint(ALLOC_IN_RC(r2_reg));
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match(iRegN);
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op_cost(0);
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format %{ %}
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interface(REG_INTER);
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%}
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operand iRegN_R3()
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%{
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constraint(ALLOC_IN_RC(r3_reg));
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match(iRegN);
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op_cost(0);
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format %{ %}
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interface(REG_INTER);
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%}
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// Integer 64 bit Register not Special
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operand iRegNNoSp()
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%{
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@ -9390,12 +9478,12 @@ instruct storeIConditional(indirect mem, iRegINoSp oldval, iRegINoSp newval, rFl
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ins_pipe(pipe_slow);
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%}
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// XXX No flag versions for CompareAndSwap{I,L,P,N} because matcher
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// can't match them
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// standard CompareAndSwapX when we are using barriers
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// these have higher priority than the rules selected by a predicate
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// XXX No flag versions for CompareAndSwap{I,L,P,N} because matcher
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// can't match them
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instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{
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match(Set res (CompareAndSwapI mem (Binary oldval newval)));
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@ -9547,6 +9635,216 @@ instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegNNoSp oldval, iRegN
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%}
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// ---------------------------------------------------------------------
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// Sundry CAS operations. Note that release is always true,
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// regardless of the memory ordering of the CAS. This is because we
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// need the volatile case to be sequentially consistent but there is
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// no trailing StoreLoad barrier emitted by C2. Unfortunately we
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// can't check the type of memory ordering here, so we always emit a
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// STLXR.
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// This section is generated from aarch64_ad_cas.m4
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instruct compareAndExchangeB(iRegI_R0 res, indirect mem, iRegI_R2 oldval, iRegI_R3 newval, rFlagsReg cr) %{
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match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
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ins_cost(2 * VOLATILE_REF_COST);
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effect(KILL cr);
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format %{
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"cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
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%}
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ins_encode %{
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__ uxtbw(rscratch2, $oldval$$Register);
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__ cmpxchg($mem$$Register, rscratch2, $newval$$Register,
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Assembler::byte, /*acquire*/ false, /*release*/ true,
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/*weak*/ false, $res$$Register);
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__ sxtbw($res$$Register, $res$$Register);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct compareAndExchangeS(iRegI_R0 res, indirect mem, iRegI_R2 oldval, iRegI_R3 newval, rFlagsReg cr) %{
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match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
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ins_cost(2 * VOLATILE_REF_COST);
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effect(KILL cr);
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format %{
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"cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
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%}
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ins_encode %{
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__ uxthw(rscratch2, $oldval$$Register);
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__ cmpxchg($mem$$Register, rscratch2, $newval$$Register,
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Assembler::halfword, /*acquire*/ false, /*release*/ true,
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/*weak*/ false, $res$$Register);
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__ sxthw($res$$Register, $res$$Register);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct compareAndExchangeI(iRegI_R0 res, indirect mem, iRegI_R2 oldval, iRegI_R3 newval, rFlagsReg cr) %{
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match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
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ins_cost(2 * VOLATILE_REF_COST);
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effect(KILL cr);
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format %{
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"cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
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%}
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ins_encode %{
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__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
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Assembler::word, /*acquire*/ false, /*release*/ true,
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/*weak*/ false, $res$$Register);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct compareAndExchangeL(iRegL_R0 res, indirect mem, iRegL_R2 oldval, iRegL_R3 newval, rFlagsReg cr) %{
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match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
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ins_cost(2 * VOLATILE_REF_COST);
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effect(KILL cr);
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format %{
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"cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
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%}
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ins_encode %{
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__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
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Assembler::xword, /*acquire*/ false, /*release*/ true,
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/*weak*/ false, $res$$Register);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct compareAndExchangeN(iRegN_R0 res, indirect mem, iRegN_R2 oldval, iRegN_R3 newval, rFlagsReg cr) %{
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match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
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ins_cost(2 * VOLATILE_REF_COST);
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effect(KILL cr);
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format %{
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"cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
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%}
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ins_encode %{
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__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
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Assembler::word, /*acquire*/ false, /*release*/ true,
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/*weak*/ false, $res$$Register);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct compareAndExchangeP(iRegP_R0 res, indirect mem, iRegP_R2 oldval, iRegP_R3 newval, rFlagsReg cr) %{
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match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
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ins_cost(2 * VOLATILE_REF_COST);
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effect(KILL cr);
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format %{
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"cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval"
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%}
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ins_encode %{
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__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
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Assembler::xword, /*acquire*/ false, /*release*/ true,
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/*weak*/ false, $res$$Register);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
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match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
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ins_cost(2 * VOLATILE_REF_COST);
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effect(KILL cr);
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format %{
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"cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
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"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
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%}
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ins_encode %{
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__ uxtbw(rscratch2, $oldval$$Register);
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__ cmpxchg($mem$$Register, rscratch2, $newval$$Register,
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Assembler::byte, /*acquire*/ false, /*release*/ true,
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/*weak*/ true, noreg);
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__ csetw($res$$Register, Assembler::EQ);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
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match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
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ins_cost(2 * VOLATILE_REF_COST);
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effect(KILL cr);
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format %{
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"cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
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"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
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%}
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ins_encode %{
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__ uxthw(rscratch2, $oldval$$Register);
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__ cmpxchg($mem$$Register, rscratch2, $newval$$Register,
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Assembler::halfword, /*acquire*/ false, /*release*/ true,
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/*weak*/ true, noreg);
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__ csetw($res$$Register, Assembler::EQ);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
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match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
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ins_cost(2 * VOLATILE_REF_COST);
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effect(KILL cr);
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format %{
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"cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
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"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
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%}
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ins_encode %{
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__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
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Assembler::word, /*acquire*/ false, /*release*/ true,
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/*weak*/ true, noreg);
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__ csetw($res$$Register, Assembler::EQ);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr) %{
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match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
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ins_cost(2 * VOLATILE_REF_COST);
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effect(KILL cr);
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format %{
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"cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
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"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
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%}
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ins_encode %{
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__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
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Assembler::xword, /*acquire*/ false, /*release*/ true,
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/*weak*/ true, noreg);
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__ csetw($res$$Register, Assembler::EQ);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval, rFlagsReg cr) %{
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match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
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ins_cost(2 * VOLATILE_REF_COST);
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effect(KILL cr);
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format %{
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"cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
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"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
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%}
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ins_encode %{
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__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
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Assembler::word, /*acquire*/ false, /*release*/ true,
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/*weak*/ true, noreg);
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__ csetw($res$$Register, Assembler::EQ);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
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match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
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ins_cost(2 * VOLATILE_REF_COST);
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effect(KILL cr);
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format %{
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"cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval"
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"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
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%}
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ins_encode %{
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__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
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Assembler::xword, /*acquire*/ false, /*release*/ true,
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/*weak*/ true, noreg);
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__ csetw($res$$Register, Assembler::EQ);
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%}
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ins_pipe(pipe_slow);
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%}
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// ---------------------------------------------------------------------
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instruct get_and_setI(indirect mem, iRegINoSp newv, iRegI prev) %{
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match(Set prev (GetAndSetI mem newv));
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format %{ "atomic_xchgw $prev, $newv, [$mem]" %}
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@ -1556,13 +1556,13 @@ void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
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}
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void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
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__ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, rscratch1);
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__ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
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__ cset(rscratch1, Assembler::NE);
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__ membar(__ AnyAny);
|
||||
}
|
||||
|
||||
void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
|
||||
__ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, rscratch1);
|
||||
__ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
|
||||
__ cset(rscratch1, Assembler::NE);
|
||||
__ membar(__ AnyAny);
|
||||
}
|
||||
|
109
hotspot/src/cpu/aarch64/vm/cas.m4
Normal file
109
hotspot/src/cpu/aarch64/vm/cas.m4
Normal file
@ -0,0 +1,109 @@
|
||||
// Sundry CAS operations. Note that release is always true,
|
||||
// regardless of the memory ordering of the CAS. This is because we
|
||||
// need the volatile case to be sequentially consistent but there is
|
||||
// no trailing StoreLoad barrier emitted by C2. Unfortunately we
|
||||
// can't check the type of memory ordering here, so we always emit a
|
||||
// STLXR.
|
||||
|
||||
define(`CAS_INSN',
|
||||
`
|
||||
instruct compareAndExchange$1$5(iReg$2_R0 res, indirect mem, iReg$2_R2 oldval, iReg$2_R3 newval, rFlagsReg cr) %{
|
||||
match(Set res (CompareAndExchange$1 mem (Binary oldval newval)));
|
||||
ifelse($5,Acq,' predicate(needs_acquiring_load_exclusive(n));
|
||||
ins_cost(VOLATILE_REF_COST);`,' ins_cost(2 * VOLATILE_REF_COST);`)
|
||||
effect(KILL cr);
|
||||
format %{
|
||||
"cmpxchg $res = $mem, $oldval, $newval\t# ($3, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
|
||||
Assembler::$4, /*acquire*/ ifelse($5,Acq,true,false), /*release*/ true,
|
||||
/*weak*/ false, $res$$Register);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}')dnl
|
||||
define(`CAS_INSN4',
|
||||
`
|
||||
instruct compareAndExchange$1$7(iReg$2_R0 res, indirect mem, iReg$2_R2 oldval, iReg$2_R3 newval, rFlagsReg cr) %{
|
||||
match(Set res (CompareAndExchange$1 mem (Binary oldval newval)));
|
||||
ifelse($7,Acq,' predicate(needs_acquiring_load_exclusive(n));
|
||||
ins_cost(VOLATILE_REF_COST);`,' ins_cost(2 * VOLATILE_REF_COST);`)
|
||||
effect(KILL cr);
|
||||
format %{
|
||||
"cmpxchg $res = $mem, $oldval, $newval\t# ($3, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ $5(rscratch2, $oldval$$Register);
|
||||
__ cmpxchg($mem$$Register, rscratch2, $newval$$Register,
|
||||
Assembler::$4, /*acquire*/ ifelse($5,Acq,true,false), /*release*/ true,
|
||||
/*weak*/ false, $res$$Register);
|
||||
__ $6($res$$Register, $res$$Register);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}')dnl
|
||||
CAS_INSN4(B,I,byte,byte,uxtbw,sxtbw)
|
||||
CAS_INSN4(S,I,short,halfword,uxthw,sxthw)
|
||||
CAS_INSN(I,I,int,word)
|
||||
CAS_INSN(L,L,long,xword)
|
||||
CAS_INSN(N,N,narrow oop,word)
|
||||
CAS_INSN(P,P,ptr,xword)
|
||||
dnl
|
||||
dnl CAS_INSN4(B,I,byte,byte,uxtbw,sxtbw,Acq)
|
||||
dnl CAS_INSN4(S,I,short,halfword,uxthw,sxthw,Acq)
|
||||
dnl CAS_INSN(I,I,int,word,Acq)
|
||||
dnl CAS_INSN(L,L,long,xword,Acq)
|
||||
dnl CAS_INSN(N,N,narrow oop,word,Acq)
|
||||
dnl CAS_INSN(P,P,ptr,xword,Acq)
|
||||
dnl
|
||||
define(`CAS_INSN2',
|
||||
`
|
||||
instruct weakCompareAndSwap$1$6(iRegINoSp res, indirect mem, iReg$2 oldval, iReg$2 newval, rFlagsReg cr) %{
|
||||
match(Set res (WeakCompareAndSwap$1 mem (Binary oldval newval)));
|
||||
ifelse($6,Acq,' predicate(needs_acquiring_load_exclusive(n));
|
||||
ins_cost(VOLATILE_REF_COST);`,' ins_cost(2 * VOLATILE_REF_COST);`)
|
||||
effect(KILL cr);
|
||||
format %{
|
||||
"cmpxchg $res = $mem, $oldval, $newval\t# ($3, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ uxt$5(rscratch2, $oldval$$Register);
|
||||
__ cmpxchg($mem$$Register, rscratch2, $newval$$Register,
|
||||
Assembler::$4, /*acquire*/ ifelse($6,Acq,true,false), /*release*/ true,
|
||||
/*weak*/ true, noreg);
|
||||
__ csetw($res$$Register, Assembler::EQ);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}')dnl
|
||||
define(`CAS_INSN3',
|
||||
`
|
||||
instruct weakCompareAndSwap$1$5(iRegINoSp res, indirect mem, iReg$2 oldval, iReg$2 newval, rFlagsReg cr) %{
|
||||
match(Set res (WeakCompareAndSwap$1 mem (Binary oldval newval)));
|
||||
ifelse($5,Acq,' predicate(needs_acquiring_load_exclusive(n));
|
||||
ins_cost(VOLATILE_REF_COST);`,' ins_cost(2 * VOLATILE_REF_COST);`)
|
||||
effect(KILL cr);
|
||||
format %{
|
||||
"cmpxchg $res = $mem, $oldval, $newval\t# ($3, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
|
||||
Assembler::$4, /*acquire*/ ifelse($5,Acq,true,false), /*release*/ true,
|
||||
/*weak*/ true, noreg);
|
||||
__ csetw($res$$Register, Assembler::EQ);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}')dnl
|
||||
CAS_INSN2(B,I,byte,byte,bw)
|
||||
CAS_INSN2(S,I,short,halfword,hw)
|
||||
CAS_INSN3(I,I,int,word)
|
||||
CAS_INSN3(L,L,long,xword)
|
||||
CAS_INSN3(N,N,narrow oop,word)
|
||||
CAS_INSN3(P,P,ptr,xword)
|
||||
dnl CAS_INSN2(B,I,byte,byte,bw,Acq)
|
||||
dnl CAS_INSN2(S,I,short,halfword,hw,Acq)
|
||||
dnl CAS_INSN3(I,I,int,word,Acq)
|
||||
dnl CAS_INSN3(L,L,long,xword,Acq)
|
||||
dnl CAS_INSN3(N,N,narrow oop,word,Acq)
|
||||
dnl CAS_INSN3(P,P,ptr,xword,Acq)
|
||||
dnl
|
@ -2141,30 +2141,40 @@ void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Regis
|
||||
b(*fail);
|
||||
}
|
||||
|
||||
// A generic CAS; success or failure is in the EQ flag.
|
||||
// A generic CAS; success or failure is in the EQ flag. A weak CAS
|
||||
// doesn't retry and may fail spuriously. If the oldval is wanted,
|
||||
// Pass a register for the result, otherwise pass noreg.
|
||||
|
||||
// Clobbers rscratch1
|
||||
void MacroAssembler::cmpxchg(Register addr, Register expected,
|
||||
Register new_val,
|
||||
enum operand_size size,
|
||||
bool acquire, bool release,
|
||||
Register tmp) {
|
||||
bool weak,
|
||||
Register result) {
|
||||
if (result == noreg) result = rscratch1;
|
||||
if (UseLSE) {
|
||||
mov(tmp, expected);
|
||||
lse_cas(tmp, new_val, addr, size, acquire, release, /*not_pair*/ true);
|
||||
cmp(tmp, expected);
|
||||
mov(result, expected);
|
||||
lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true);
|
||||
cmp(result, expected);
|
||||
} else {
|
||||
BLOCK_COMMENT("cmpxchg {");
|
||||
Label retry_load, done;
|
||||
if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH))
|
||||
prfm(Address(addr), PSTL1STRM);
|
||||
bind(retry_load);
|
||||
load_exclusive(tmp, addr, size, acquire);
|
||||
load_exclusive(result, addr, size, acquire);
|
||||
if (size == xword)
|
||||
cmp(tmp, expected);
|
||||
cmp(result, expected);
|
||||
else
|
||||
cmpw(tmp, expected);
|
||||
cmpw(result, expected);
|
||||
br(Assembler::NE, done);
|
||||
store_exclusive(tmp, new_val, addr, size, release);
|
||||
cbnzw(tmp, retry_load);
|
||||
store_exclusive(rscratch1, new_val, addr, size, release);
|
||||
if (weak) {
|
||||
cmpw(rscratch1, 0u); // If the store fails, return NE to our caller.
|
||||
} else {
|
||||
cbnzw(rscratch1, retry_load);
|
||||
}
|
||||
bind(done);
|
||||
BLOCK_COMMENT("} cmpxchg");
|
||||
}
|
||||
|
@ -995,10 +995,11 @@ public:
|
||||
}
|
||||
|
||||
// A generic CAS; success or failure is in the EQ flag.
|
||||
// Clobbers rscratch1
|
||||
void cmpxchg(Register addr, Register expected, Register new_val,
|
||||
enum operand_size size,
|
||||
bool acquire, bool release,
|
||||
Register tmp = rscratch1);
|
||||
bool acquire, bool release, bool weak,
|
||||
Register result);
|
||||
|
||||
// Calls
|
||||
|
||||
|
Loading…
x
Reference in New Issue
Block a user