8199138: Add RISC-V support to Zero
Reviewed-by: erikj, stuefe
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@ -120,6 +120,12 @@ AC_DEFUN([PLATFORM_EXTRACT_VARS_FROM_CPU],
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VAR_CPU_BITS=64
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VAR_CPU_ENDIAN=little
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;;
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riscv64)
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VAR_CPU=riscv64
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VAR_CPU_ARCH=riscv
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VAR_CPU_BITS=64
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VAR_CPU_ENDIAN=little
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;;
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s390)
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VAR_CPU=s390
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VAR_CPU_ARCH=s390
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@ -485,6 +491,8 @@ AC_DEFUN([PLATFORM_SETUP_LEGACY_VARS_HELPER],
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HOTSPOT_$1_CPU_DEFINE=S390
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elif test "x$OPENJDK_$1_CPU" = xs390x; then
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HOTSPOT_$1_CPU_DEFINE=S390
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elif test "x$OPENJDK_$1_CPU" = xriscv64; then
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HOTSPOT_$1_CPU_DEFINE=RISCV
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elif test "x$OPENJDK_$1_CPU" != x; then
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HOTSPOT_$1_CPU_DEFINE=$(echo $OPENJDK_$1_CPU | tr a-z A-Z)
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fi
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@ -1851,6 +1851,9 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
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#ifndef EM_AARCH64
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#define EM_AARCH64 183 /* ARM AARCH64 */
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#endif
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#ifndef EM_RISCV
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#define EM_RISCV 243 /* RISC-V */
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#endif
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static const arch_t arch_array[]={
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{EM_386, EM_386, ELFCLASS32, ELFDATA2LSB, (char*)"IA 32"},
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@ -1877,6 +1880,7 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
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{EM_PARISC, EM_PARISC, ELFCLASS32, ELFDATA2MSB, (char*)"PARISC"},
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{EM_68K, EM_68K, ELFCLASS32, ELFDATA2MSB, (char*)"M68k"},
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{EM_AARCH64, EM_AARCH64, ELFCLASS64, ELFDATA2LSB, (char*)"AARCH64"},
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{EM_RISCV, EM_RISCV, ELFCLASS64, ELFDATA2LSB, (char*)"RISC-V"},
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};
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#if (defined IA32)
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@ -1911,9 +1915,11 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
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static Elf32_Half running_arch_code=EM_68K;
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#elif (defined SH)
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static Elf32_Half running_arch_code=EM_SH;
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#elif (defined RISCV)
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static Elf32_Half running_arch_code=EM_RISCV;
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#else
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#error Method os::dll_load requires that one of following is defined:\
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AARCH64, ALPHA, ARM, AMD64, IA32, IA64, M68K, MIPS, MIPSEL, PARISC, __powerpc__, __powerpc64__, S390, SH, __sparc
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AARCH64, ALPHA, ARM, AMD64, IA32, IA64, M68K, MIPS, MIPSEL, PARISC, __powerpc__, __powerpc64__, RISCV, S390, SH, __sparc
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#endif
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// Identify compatibility class for VM's architecture and library's architecture
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