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8075093: Enable UseFPUForSpilling support on SPARC

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Use single-cycle MOV instructions (MOVdTOx, MOVxTOd) for spills on SPARC which have them.

Reviewed-by: kvn
This commit is contained in:
Shrinivas Joshi 2015-09-02 15:11:22 -07:00 committed by Vladimir Kozlov
parent b641aad954
commit f10466290d
1 changed files with 12 additions and 3 deletions
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15
hotspot/src/cpu/sparc/vm/vm_version_sparc.cpp
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@ -218,9 +218,6 @@ void VM_Version::initialize() {
FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
}
// Currently not supported anywhere.
FLAG_SET_DEFAULT(UseFPUForSpilling, false);
MaxVectorSize = 8;
assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
@ -266,6 +263,18 @@ void VM_Version::initialize() {
if (!has_vis1()) // Drop to 0 if no VIS1 support
UseVIS = 0;
// Enable UseFPUForSpilling if low-latency GP-to-FP register move instructions are available
if (UseVIS > 2) { // FP spill use VIS3 MOVxTOd/MOVdTOx
if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
FLAG_SET_DEFAULT(UseFPUForSpilling, true);
}
} else if (UseFPUForSpilling) {
if (!FLAG_IS_DEFAULT(UseFPUForSpilling)) {
warning("Spill to float registers requires VIS3 instructions (not available on this CPU).");
}
FLAG_SET_DEFAULT(UseFPUForSpilling, false);
}
// SPARC T4 and above should have support for AES instructions
if (has_aes()) {
if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3