8272058: 25 Null pointer dereference defect groups in 4 files
Reviewed-by: gziemski, coleenp, dlong
This commit is contained in:
parent
28e02fa2cb
commit
f5de6fa799
src/hotspot/cpu/aarch64
@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
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* Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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*
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@ -160,8 +160,7 @@ int MacroAssembler::pd_patch_instruction_size(address branch, address target) {
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Instruction_aarch64::patch(branch+8, 20, 5, (dest >>= 16) & 0xffff);
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Instruction_aarch64::patch(branch+8, 20, 5, (dest >>= 16) & 0xffff);
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assert(target_addr_for_insn(branch) == target, "should be");
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assert(target_addr_for_insn(branch) == target, "should be");
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instructions = 3;
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instructions = 3;
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} else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
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} else if (NativeInstruction::is_ldrw_to_zr(address(&insn))) {
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Instruction_aarch64::extract(insn, 4, 0) == 0b11111) {
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// nothing to do
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// nothing to do
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assert(target == 0, "did not expect to relocate target for polling page load");
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assert(target == 0, "did not expect to relocate target for polling page load");
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} else {
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} else {
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@ -284,15 +283,19 @@ address MacroAssembler::target_addr_for_insn(address insn_addr, unsigned insn) {
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return address(uint64_t(Instruction_aarch64::extract(insns[0], 20, 5))
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return address(uint64_t(Instruction_aarch64::extract(insns[0], 20, 5))
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+ (uint64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
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+ (uint64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
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+ (uint64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
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+ (uint64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
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} else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
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Instruction_aarch64::extract(insn, 4, 0) == 0b11111) {
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return 0;
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} else {
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} else {
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ShouldNotReachHere();
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ShouldNotReachHere();
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}
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}
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return address(((uint64_t)insn_addr + (offset << 2)));
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return address(((uint64_t)insn_addr + (offset << 2)));
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}
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}
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address MacroAssembler::target_addr_for_insn_or_null(address insn_addr, unsigned insn) {
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if (NativeInstruction::is_ldrw_to_zr(address(&insn))) {
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return 0;
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}
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return MacroAssembler::target_addr_for_insn(insn_addr, insn);
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}
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void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod) {
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void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod) {
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if (acquire) {
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if (acquire) {
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lea(rscratch1, Address(rthread, JavaThread::polling_word_offset()));
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lea(rscratch1, Address(rthread, JavaThread::polling_word_offset()));
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
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* Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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*
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@ -606,10 +606,15 @@ public:
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static bool uses_implicit_null_check(void* address);
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static bool uses_implicit_null_check(void* address);
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static address target_addr_for_insn(address insn_addr, unsigned insn);
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static address target_addr_for_insn(address insn_addr, unsigned insn);
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static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
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static address target_addr_for_insn(address insn_addr) {
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static address target_addr_for_insn(address insn_addr) {
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unsigned insn = *(unsigned*)insn_addr;
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unsigned insn = *(unsigned*)insn_addr;
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return target_addr_for_insn(insn_addr, insn);
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return target_addr_for_insn(insn_addr, insn);
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}
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}
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static address target_addr_for_insn_or_null(address insn_addr) {
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unsigned insn = *(unsigned*)insn_addr;
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return target_addr_for_insn_or_null(insn_addr, insn);
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}
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// Required platform-specific helpers for Label::patch_instructions.
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// Required platform-specific helpers for Label::patch_instructions.
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// They _shadow_ the declarations in AbstractAssembler, which are undefined.
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// They _shadow_ the declarations in AbstractAssembler, which are undefined.
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
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* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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*
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@ -315,7 +315,7 @@ void NativeMovRegMem::set_offset(int x) {
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void NativeMovRegMem::verify() {
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void NativeMovRegMem::verify() {
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#ifdef ASSERT
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#ifdef ASSERT
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address dest = MacroAssembler::target_addr_for_insn(instruction_address());
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address dest = MacroAssembler::target_addr_for_insn_or_null(instruction_address());
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#endif
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#endif
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}
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}
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@ -329,7 +329,7 @@ void NativeJump::check_verified_entry_alignment(address entry, address verified_
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address NativeJump::jump_destination() const {
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address NativeJump::jump_destination() const {
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address dest = MacroAssembler::target_addr_for_insn(instruction_address());
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address dest = MacroAssembler::target_addr_for_insn_or_null(instruction_address());
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// We use jump to self as the unresolved address which the inline
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// We use jump to self as the unresolved address which the inline
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// cache code (and relocs) know about
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// cache code (and relocs) know about
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