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8253469: ARM32 Zero: replace usages of __sync_synchronize() with OrderAccess::fence

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Reviewed-by: dholmes
This commit is contained in:
Aleksey Shipilev 2020-09-25 10:14:04 +00:00
parent 1b79326c05
commit f62eefc02b
2 changed files with 10 additions and 6 deletions
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8
src/hotspot/os_cpu/bsd_zero/atomic_bsd_zero.hpp
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@ -26,6 +26,7 @@
#ifndef OS_CPU_BSD_ZERO_ATOMIC_BSD_ZERO_HPP
#define OS_CPU_BSD_ZERO_ATOMIC_BSD_ZERO_HPP
#include "orderAccess_bsd_zero.hpp"
#include "runtime/os.hpp"
// Implementation of class atomic
@ -218,8 +219,9 @@ inline T Atomic::PlatformXchg<4>::operator()(T volatile* dest,
// All atomic operations are expected to be full memory barriers
// (see atomic.hpp). However, __sync_lock_test_and_set is not
// a full memory barrier, but an acquire barrier. Hence, this added
// barrier.
__sync_synchronize();
// barrier. Some platforms (notably ARM) have peculiarities with
// their barrier implementations, delegate it to OrderAccess.
OrderAccess::fence();
return result;
#endif // M68K
#endif // ARM
@ -232,7 +234,7 @@ inline T Atomic::PlatformXchg<8>::operator()(T volatile* dest,
atomic_memory_order order) const {
STATIC_ASSERT(8 == sizeof(T));
T result = __sync_lock_test_and_set (dest, exchange_value);
__sync_synchronize();
OrderAccess::fence();
return result;
}

8
src/hotspot/os_cpu/linux_zero/atomic_linux_zero.hpp
View File

@ -26,6 +26,7 @@
#ifndef OS_CPU_LINUX_ZERO_ATOMIC_LINUX_ZERO_HPP
#define OS_CPU_LINUX_ZERO_ATOMIC_LINUX_ZERO_HPP
#include "orderAccess_linux_zero.hpp"
#include "runtime/os.hpp"
// Implementation of class atomic
@ -74,8 +75,9 @@ inline T Atomic::PlatformXchg<4>::operator()(T volatile* dest,
// All atomic operations are expected to be full memory barriers
// (see atomic.hpp). However, __sync_lock_test_and_set is not
// a full memory barrier, but an acquire barrier. Hence, this added
// barrier.
__sync_synchronize();
// barrier. Some platforms (notably ARM) have peculiarities with
// their barrier implementations, delegate it to OrderAccess.
OrderAccess::fence();
return result;
}
@ -86,7 +88,7 @@ inline T Atomic::PlatformXchg<8>::operator()(T volatile* dest,
atomic_memory_order order) const {
STATIC_ASSERT(8 == sizeof(T));
T result = __sync_lock_test_and_set (dest, exchange_value);
__sync_synchronize();
OrderAccess::fence();
return result;
}