8328998: Encoding support for Intel APX extended general-purpose registers
Reviewed-by: kvn, sviswanathan, jbhateja
This commit is contained in:
steveatgh
Sandhya Viswanathan
parent
ddd73b4583
commit
f8a3e4e428
File diff suppressed because it is too large
Load Diff
@ -308,17 +308,29 @@ class Address {
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private:
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bool base_needs_rex() const {
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return _base->is_valid() && _base->encoding() >= 8;
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return _base->is_valid() && ((_base->encoding() & 8) == 8);
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}
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bool base_needs_rex2() const {
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return _base->is_valid() && _base->encoding() >= 16;
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}
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bool index_needs_rex() const {
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return _index->is_valid() &&_index->encoding() >= 8;
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return _index->is_valid() && ((_index->encoding() & 8) == 8);
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}
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bool index_needs_rex2() const {
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return _index->is_valid() &&_index->encoding() >= 16;
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}
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bool xmmindex_needs_rex() const {
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return _xmmindex->is_valid() && ((_xmmindex->encoding() & 8) == 8);
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}
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bool xmmindex_needs_rex2() const {
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return _xmmindex->is_valid() && _xmmindex->encoding() >= 16;
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}
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relocInfo::relocType reloc() const { return _rspec.type(); }
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friend class Assembler;
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@ -508,12 +520,26 @@ class Assembler : public AbstractAssembler {
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REX_WRX = 0x4E,
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REX_WRXB = 0x4F,
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REX2 = 0xd5,
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WREX2 = REX2 << 8,
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VEX_3bytes = 0xC4,
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VEX_2bytes = 0xC5,
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EVEX_4bytes = 0x62,
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Prefix_EMPTY = 0x0
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};
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enum PrefixBits {
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REXBIT_B = 0x01,
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REXBIT_X = 0x02,
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REXBIT_R = 0x04,
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REXBIT_W = 0x08,
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REX2BIT_B4 = 0x10,
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REX2BIT_X4 = 0x20,
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REX2BIT_R4 = 0x40,
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REX2BIT_M0 = 0x80
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};
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enum VexPrefix {
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VEX_B = 0x20,
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VEX_X = 0x40,
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@ -525,10 +551,18 @@ class Assembler : public AbstractAssembler {
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EVEX_F = 0x04,
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EVEX_V = 0x08,
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EVEX_Rb = 0x10,
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EVEX_B = 0x20,
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EVEX_X = 0x40,
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EVEX_Z = 0x80
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};
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enum ExtEvexPrefix {
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EEVEX_R = 0x10,
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EEVEX_B = 0x08,
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EEVEX_X = 0x04,
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EEVEX_V = 0x08
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};
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enum EvexRoundPrefix {
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EVEX_RNE = 0x0,
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EVEX_RD = 0x1,
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@ -540,7 +574,7 @@ class Assembler : public AbstractAssembler {
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VEX_SIMD_NONE = 0x0,
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VEX_SIMD_66 = 0x1,
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VEX_SIMD_F3 = 0x2,
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VEX_SIMD_F2 = 0x3
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VEX_SIMD_F2 = 0x3,
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};
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enum VexOpcode {
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@ -548,6 +582,7 @@ class Assembler : public AbstractAssembler {
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VEX_OPCODE_0F = 0x1,
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VEX_OPCODE_0F_38 = 0x2,
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VEX_OPCODE_0F_3A = 0x3,
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VEX_OPCODE_0F_3C = 0x4,
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VEX_OPCODE_MASK = 0x1F
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};
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@ -572,7 +607,8 @@ class Assembler : public AbstractAssembler {
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EVEX_OVM = 20,
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EVEX_M128 = 21,
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EVEX_DUP = 22,
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EVEX_ETUP = 23
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EVEX_NOSCALE = 23,
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EVEX_ETUP = 24
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};
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enum EvexInputSizeInBits {
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@ -686,33 +722,62 @@ private:
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InstructionAttr *_attributes;
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void set_attributes(InstructionAttr* attributes);
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int get_base_prefix_bits(int enc);
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int get_index_prefix_bits(int enc);
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int get_base_prefix_bits(Register base);
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int get_index_prefix_bits(Register index);
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int get_reg_prefix_bits(int enc);
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// 64bit prefixes
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void prefix(Register reg);
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void prefix(Register dst, Register src, Prefix p);
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void prefix_rex2(Register dst, Register src);
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void prefix(Register dst, Address adr, Prefix p);
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void prefix_rex2(Register dst, Address adr);
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void prefix(Address adr);
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void prefix(Address adr, Register reg, bool byteinst = false);
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// The is_map1 bool indicates an x86 map1 instruction which, when
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// legacy encoded, uses a 0x0F opcode prefix. By specification, the
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// opcode prefix is omitted when using rex2 encoding in support
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// of APX extended GPRs.
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void prefix(Address adr, bool is_map1 = false);
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void prefix_rex2(Address adr, bool is_map1 = false);
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void prefix(Address adr, Register reg, bool byteinst = false, bool is_map1 = false);
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void prefix_rex2(Address adr, Register reg, bool byteinst = false, bool is_map1 = false);
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void prefix(Address adr, XMMRegister reg);
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void prefix_rex2(Address adr, XMMRegister reg);
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int prefix_and_encode(int reg_enc, bool byteinst = false);
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int prefix_and_encode(int dst_enc, int src_enc) {
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return prefix_and_encode(dst_enc, false, src_enc, false);
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int prefix_and_encode(int reg_enc, bool byteinst = false, bool is_map1 = false);
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int prefix_and_encode_rex2(int reg_enc, bool is_map1 = false);
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int prefix_and_encode(int dst_enc, int src_enc, bool is_map1 = false) {
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return prefix_and_encode(dst_enc, false, src_enc, false, is_map1);
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}
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int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte);
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int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte, bool is_map1 = false);
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int prefix_and_encode_rex2(int dst_enc, int src_enc, int init_bits = 0);
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// Some prefixq variants always emit exactly one prefix byte, so besides a
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// prefix-emitting method we provide a method to get the prefix byte to emit,
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// which can then be folded into a byte stream.
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int8_t get_prefixq(Address adr);
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int8_t get_prefixq(Address adr, Register reg);
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int get_prefixq(Address adr, bool is_map1 = false);
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int get_prefixq_rex2(Address adr, bool is_map1 = false);
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int get_prefixq(Address adr, Register reg, bool is_map1 = false);
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int get_prefixq_rex2(Address adr, Register reg, bool ismap1 = false);
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void prefixq(Address adr);
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void prefixq(Address adr, Register reg);
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void prefixq(Address adr, Register reg, bool is_map1 = false);
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void prefixq(Address adr, XMMRegister reg);
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void prefixq_rex2(Address adr, XMMRegister src);
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int prefixq_and_encode(int reg_enc);
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int prefixq_and_encode(int dst_enc, int src_enc);
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bool prefix_is_rex2(int prefix);
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int prefixq_and_encode(int reg_enc, bool is_map1 = false);
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int prefixq_and_encode_rex2(int reg_enc, bool is_map1 = false);
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int prefixq_and_encode(int dst_enc, int src_enc, bool is_map1 = false);
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int prefixq_and_encode_rex2(int dst_enc, int src_enc, bool is_map1 = false);
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bool needs_rex2(Register reg1, Register reg2 = noreg, Register reg3 = noreg);
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bool needs_eevex(Register reg1, Register reg2 = noreg, Register reg3 = noreg);
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bool needs_eevex(int enc1, int enc2 = -1, int enc3 = -1);
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void rex_prefix(Address adr, XMMRegister xreg,
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VexSimdPrefix pre, VexOpcode opc, bool rex_w);
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@ -721,22 +786,21 @@ private:
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void vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc);
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void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v,
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int nds_enc, VexSimdPrefix pre, VexOpcode opc);
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void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_v, bool evex_r, bool evex_b,
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bool eevex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc);
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void vex_prefix(Address adr, int nds_enc, int xreg_enc,
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VexSimdPrefix pre, VexOpcode opc,
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void vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc,
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InstructionAttr *attributes);
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int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
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VexSimdPrefix pre, VexOpcode opc,
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InstructionAttr *attributes);
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InstructionAttr *attributes, bool src_is_gpr = false);
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void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
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VexOpcode opc, InstructionAttr *attributes);
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int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
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VexOpcode opc, InstructionAttr *attributes);
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VexOpcode opc, InstructionAttr *attributes, bool src_is_gpr = false);
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// Helper functions for groups of instructions
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void emit_arith_b(int op1, int op2, Register dst, int imm8);
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@ -821,6 +885,10 @@ private:
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void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
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void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
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void emit_prefix_and_int8(int prefix, int b1);
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void emit_opcode_prefix_and_encoding(int byte1, int ocp_and_encoding);
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void emit_opcode_prefix_and_encoding(int byte1, int byte2, int ocp_and_encoding);
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void emit_opcode_prefix_and_encoding(int byte1, int byte2, int ocp_and_encoding, int byte3);
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bool always_reachable(AddressLiteral adr) NOT_LP64( { return true; } );
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bool reachable(AddressLiteral adr) NOT_LP64( { return true; } );
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@ -907,6 +975,8 @@ private:
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// Instruction prefixes
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void prefix(Prefix p);
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void prefix16(int p);
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public:
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// Creation
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@ -30,23 +30,53 @@
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#include "code/codeCache.hpp"
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#ifndef _LP64
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inline int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { return reg_enc; }
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inline int Assembler::prefixq_and_encode(int reg_enc) { return reg_enc; }
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inline int Assembler::prefix_and_encode(int reg_enc, bool byteinst, bool is_map1)
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{
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int opc_prefix = is_map1 ? 0x0F00 : 0;
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return opc_prefix | reg_enc;
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}
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inline int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) { return dst_enc << 3 | src_enc; }
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inline int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { return dst_enc << 3 | src_enc; }
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inline int Assembler::prefixq_and_encode(int reg_enc, bool is_map1) {
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int opc_prefix = is_map1 ? 0xF00 : 0;
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return opc_prefix | reg_enc;
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}
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inline int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte, bool is_map1) {
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int opc_prefix = is_map1 ? 0xF00 : 0;
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return opc_prefix | (dst_enc << 3 | src_enc);
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}
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inline int Assembler::prefixq_and_encode(int dst_enc, int src_enc, bool is_map1) {
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int opc_prefix = is_map1 ? 0xF00 : 0;
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return opc_prefix | dst_enc << 3 | src_enc;
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}
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inline void Assembler::prefix(Register reg) {}
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inline void Assembler::prefix(Register dst, Register src, Prefix p) {}
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inline void Assembler::prefix(Register dst, Address adr, Prefix p) {}
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inline void Assembler::prefix(Address adr) {}
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inline void Assembler::prefix(Address adr, bool is_map1) {
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if (is_map1) {
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emit_int8(0x0F);
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}
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}
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inline void Assembler::prefixq(Address adr) {}
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inline void Assembler::prefix(Address adr, Register reg, bool byteinst) {}
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inline void Assembler::prefixq(Address adr, Register reg) {}
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inline void Assembler::prefix(Address adr, Register reg, bool byteinst, bool is_map1) {
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if (is_map1) {
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emit_int8(0x0F);
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}
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}
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inline void Assembler::prefixq(Address adr, Register reg, bool is_map1) {
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if (is_map1) {
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emit_int8(0x0F);
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}
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}
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inline void Assembler::prefix(Address adr, XMMRegister reg) {}
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inline void Assembler::prefixq(Address adr, XMMRegister reg) {}
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#endif // _LP64
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#endif // CPU_X86_ASSEMBLER_X86_INLINE_HPP
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@ -232,8 +232,10 @@ define_pd_global(intx, InitArrayShortSize, 8*BytesPerLong);
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\
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product(bool, IntelJccErratumMitigation, true, DIAGNOSTIC, \
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"Turn off JVM mitigations related to Intel micro code " \
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"mitigations for the Intel JCC erratum")
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"mitigations for the Intel JCC erratum") \
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\
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product(bool, UseAPX, false, EXPERIMENTAL, \
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"Use Advanced Performance Extensions on x86") \
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// end of ARCH_FLAGS
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#endif // CPU_X86_GLOBALS_X86_HPP
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@ -1002,6 +1002,14 @@ void VM_Version::get_processor_features() {
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}
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}
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// APX support not enabled yet
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if (UseAPX) {
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if (!FLAG_IS_DEFAULT(UseAPX)) {
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warning("APX is not supported on this CPU.");
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}
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FLAG_SET_DEFAULT(UseAPX, false);
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}
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if (FLAG_IS_DEFAULT(IntelJccErratumMitigation)) {
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_has_intel_jcc_erratum = compute_has_intel_jcc_erratum();
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} else {
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