stan/jdk-24
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

8331577: RISC-V: C2 CountLeadingZerosV

Browse Source 
8331578: RISC-V: C2 CountTrailingZerosV

Reviewed-by: fyang
This commit is contained in:
Hamlin Li 2024-05-10 13:59:09 +00:00
parent 675fbe699e
commit f95c937405
3 changed files with 72 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/hotspot/cpu/riscv/assembler_riscv.hpp
View File

@ -1891,6 +1891,9 @@ enum Nf {
INSN(vbrev8_v, 0b1010111, 0b010, 0b01000, 0b010010); // reverse bits in every byte of element
INSN(vrev8_v, 0b1010111, 0b010, 0b01001, 0b010010); // reverse bytes in every elememt
INSN(vclz_v, 0b1010111, 0b010, 0b01100, 0b010010); // count leading zeros
INSN(vctz_v, 0b1010111, 0b010, 0b01101, 0b010010); // count trailing zeros
#undef INSN
#define INSN(NAME, op, funct3, vm, funct6) \

76
src/hotspot/cpu/riscv/riscv_v.ad
View File

@ -73,6 +73,8 @@ source %{
return false;
}
break;
case Op_CountTrailingZerosV:
case Op_CountLeadingZerosV:
case Op_ReverseBytesV:
case Op_PopCountVL:
case Op_PopCountVI:
@ -3759,14 +3761,14 @@ instruct vsignum_reg(vReg dst, vReg zero, vReg one, vRegMask_V0 v0) %{
// -------------------------------- Reverse Bytes Vector Operations ------------------------
instruct vreverse_bytes_masked(vReg dst, vReg src, vRegMask_V0 v0) %{
match(Set dst (ReverseBytesV src v0));
format %{ "vreverse_bytes_masked $dst, $src, v0" %}
instruct vreverse_bytes_masked(vReg dst_src, vRegMask_V0 v0) %{
match(Set dst_src (ReverseBytesV dst_src v0));
format %{ "vreverse_bytes_masked $dst_src, $dst_src, v0" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
uint vlen = Matcher::vector_length(this);
__ vsetvli_helper(bt, vlen);
__ vrev8_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), Assembler::v0_t);
__ vrev8_v(as_VectorRegister($dst_src$$reg), as_VectorRegister($dst_src$$reg), Assembler::v0_t);
%}
ins_pipe(pipe_slow);
%}
@ -3817,16 +3819,16 @@ instruct vconvF2HF(vReg dst, vReg src, vReg vtmp, vRegMask_V0 v0, iRegINoSp tmp)
// ------------------------------ Popcount vector ------------------------------
instruct vpopcount_masked(vReg dst, vReg src, vRegMask_V0 v0) %{
match(Set dst (PopCountVI src v0));
match(Set dst (PopCountVL src v0));
instruct vpopcount_masked(vReg dst_src, vRegMask_V0 v0) %{
match(Set dst_src (PopCountVI dst_src v0));
match(Set dst_src (PopCountVL dst_src v0));
ins_cost(VEC_COST);
format %{ "vcpop_v $dst, $src, $v0\t# vcpop_v with mask" %}
format %{ "vcpop_v $dst_src, $dst_src, $v0\t# vcpop_v with mask" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
uint vlen = Matcher::vector_length(this);
__ vsetvli_helper(bt, vlen);
__ vcpop_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), Assembler::v0_t);
__ vcpop_v(as_VectorRegister($dst_src$$reg), as_VectorRegister($dst_src$$reg), Assembler::v0_t);
%}
ins_pipe(pipe_slow);
%}
@ -3845,6 +3847,62 @@ instruct vpopcount(vReg dst, vReg src) %{
ins_pipe(pipe_slow);
%}
// ------------------------------ CountLeadingZerosV --------------------------
instruct vcountLeadingZeros_masked(vReg dst_src, vRegMask_V0 v0) %{
match(Set dst_src (CountLeadingZerosV dst_src v0));
ins_cost(VEC_COST);
format %{ "vcount_leading_zeros_masked $dst_src, $dst_src, v0" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
uint vlen = Matcher::vector_length(this);
__ vsetvli_helper(bt, vlen);
__ vclz_v(as_VectorRegister($dst_src$$reg), as_VectorRegister($dst_src$$reg), Assembler::v0_t);
%}
ins_pipe(pipe_slow);
%}
instruct vcountLeadingZeros(vReg dst, vReg src) %{
match(Set dst (CountLeadingZerosV src));
ins_cost(VEC_COST);
format %{ "vcount_leading_zeros $dst, $src" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
uint vlen = Matcher::vector_length(this);
__ vsetvli_helper(bt, vlen);
__ vclz_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
%}
ins_pipe(pipe_slow);
%}
// ------------------------------ CountTrailingZerosV --------------------------
instruct vcountTrailingZeros_masked(vReg dst_src, vRegMask_V0 v0) %{
match(Set dst_src (CountTrailingZerosV dst_src v0));
ins_cost(VEC_COST);
format %{ "vcount_trailing_zeros_masked $dst_src, $dst_src, v0" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
uint vlen = Matcher::vector_length(this);
__ vsetvli_helper(bt, vlen);
__ vctz_v(as_VectorRegister($dst_src$$reg), as_VectorRegister($dst_src$$reg), Assembler::v0_t);
%}
ins_pipe(pipe_slow);
%}
instruct vcountTrailingZeros(vReg dst, vReg src) %{
match(Set dst (CountTrailingZerosV src));
ins_cost(VEC_COST);
format %{ "vcount_trailing_zeros $dst, $src" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
uint vlen = Matcher::vector_length(this);
__ vsetvli_helper(bt, vlen);
__ vctz_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
%}
ins_pipe(pipe_slow);
%}
// ------------------------------ Vector Load Gather ---------------------------
instruct gather_load(vReg dst, indirect mem, vReg idx) %{

3
test/hotspot/jtreg/compiler/vectorization/TestNumberOfContinuousZeros.java
View File

@ -27,7 +27,8 @@
* @summary Test vectorization of numberOfTrailingZeros/numberOfLeadingZeros for Long
* @requires vm.compiler2.enabled
* @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx2.*") |
* (os.simpleArch == "aarch64" & vm.cpu.features ~= ".*sve.*")
* (os.simpleArch == "aarch64" & vm.cpu.features ~= ".*sve.*") |
* (os.simpleArch == "riscv64" & vm.cpu.features ~= ".*zvbb.*")
* @library /test/lib /
* @run driver compiler.vectorization.TestNumberOfContinuousZeros
*/