8284949: riscv: Add Zero support for the 32-bit RISC-V architecture
Co-authored-by: Junfeng Xie <xiejunfeng3@huawei.com> Reviewed-by: erikj, stuefe, ihse, yadongwang
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@ -144,7 +144,8 @@ AC_DEFUN_ONCE([LIB_SETUP_LIBRARIES],
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test "x$OPENJDK_TARGET_CPU" = xmips ||
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test "x$OPENJDK_TARGET_CPU" = xmipsel ||
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test "x$OPENJDK_TARGET_CPU" = xppc ||
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test "x$OPENJDK_TARGET_CPU" = xsh); then
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test "x$OPENJDK_TARGET_CPU" = xsh ||
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test "x$OPENJDK_TARGET_CPU" = xriscv32); then
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BASIC_JVM_LIBS="$BASIC_JVM_LIBS -latomic"
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fi
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fi
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@ -126,6 +126,12 @@ AC_DEFUN([PLATFORM_EXTRACT_VARS_FROM_CPU],
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VAR_CPU_BITS=64
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VAR_CPU_ENDIAN=little
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;;
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riscv32)
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VAR_CPU=riscv32
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VAR_CPU_ARCH=riscv
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VAR_CPU_BITS=32
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VAR_CPU_ENDIAN=little
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;;
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riscv64)
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VAR_CPU=riscv64
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VAR_CPU_ARCH=riscv
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@ -561,6 +567,8 @@ AC_DEFUN([PLATFORM_SETUP_LEGACY_VARS_HELPER],
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HOTSPOT_$1_CPU_DEFINE=PPC64
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elif test "x$OPENJDK_$1_CPU" = xppc64le; then
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HOTSPOT_$1_CPU_DEFINE=PPC64
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elif test "x$OPENJDK_$1_CPU" = xriscv32; then
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HOTSPOT_$1_CPU_DEFINE=RISCV32
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elif test "x$OPENJDK_$1_CPU" = xriscv64; then
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HOTSPOT_$1_CPU_DEFINE=RISCV64
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@ -1628,7 +1628,11 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
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{EM_PARISC, EM_PARISC, ELFCLASS32, ELFDATA2MSB, (char*)"PARISC"},
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{EM_68K, EM_68K, ELFCLASS32, ELFDATA2MSB, (char*)"M68k"},
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{EM_AARCH64, EM_AARCH64, ELFCLASS64, ELFDATA2LSB, (char*)"AARCH64"},
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{EM_RISCV, EM_RISCV, ELFCLASS64, ELFDATA2LSB, (char*)"RISC-V"},
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#ifdef _LP64
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{EM_RISCV, EM_RISCV, ELFCLASS64, ELFDATA2LSB, (char*)"RISCV64"},
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#else
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{EM_RISCV, EM_RISCV, ELFCLASS32, ELFDATA2LSB, (char*)"RISCV32"},
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#endif
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{EM_LOONGARCH, EM_LOONGARCH, ELFCLASS64, ELFDATA2LSB, (char*)"LoongArch"},
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};
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@ -2476,7 +2480,7 @@ void os::get_summary_cpu_info(char* cpuinfo, size_t length) {
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#elif defined(PPC)
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strncpy(cpuinfo, "PPC64", length);
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#elif defined(RISCV)
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strncpy(cpuinfo, "RISCV64", length);
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strncpy(cpuinfo, LP64_ONLY("RISCV64") NOT_LP64("RISCV32"), length);
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#elif defined(S390)
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strncpy(cpuinfo, "S390", length);
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#elif defined(SPARC)
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@ -38,6 +38,13 @@
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#define guarantee_with_errno(cond, msg) check_with_errno(guarantee, cond, msg)
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// 32-bit RISC-V has no SYS_futex syscall.
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#ifdef RISCV32
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#if !defined(SYS_futex) && defined(SYS_futex_time64)
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#define SYS_futex SYS_futex_time64
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#endif
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#endif
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static int futex(volatile int *addr, int futex_op, int op_arg) {
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return syscall(SYS_futex, addr, futex_op, op_arg, NULL, NULL, 0);
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}
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