8185975: PPC64: Fix vsldoi interface according to the ISA
Reviewed-by: mdoerr
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7009b948bb
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fd3d8a1997
@ -2027,7 +2027,7 @@ class Assembler : public AbstractAssembler {
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inline void vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
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inline void vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
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inline void vsl( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int si4);
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inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int ui4);
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inline void vslo( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vsr( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vsro( VectorRegister d, VectorRegister a, VectorRegister b);
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@ -800,7 +800,7 @@ inline void Assembler::vspltisw(VectorRegister d, int si5)
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inline void Assembler::vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c){ emit_int32( VPERM_OPCODE | vrt(d) | vra(a) | vrb(b) | vrc(c)); }
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inline void Assembler::vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c){ emit_int32( VSEL_OPCODE | vrt(d) | vra(a) | vrb(b) | vrc(c)); }
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inline void Assembler::vsl( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSL_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int si4) { emit_int32( VSLDOI_OPCODE| vrt(d) | vra(a) | vrb(b) | vsldoi_shb(simm(si4,4))); }
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inline void Assembler::vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int ui4) { emit_int32( VSLDOI_OPCODE| vrt(d) | vra(a) | vrb(b) | vsldoi_shb(uimm(ui4,4))); }
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inline void Assembler::vslo( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSLO_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vsr( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSR_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vsro( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSRO_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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@ -4576,12 +4576,12 @@ void MacroAssembler::kernel_crc32_1word_aligned(Register crc, Register buf, Regi
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vspltisw(VR0, -1);
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vsldoi(mask_32bit, zeroes, VR0, 4);
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vsldoi(mask_64bit, zeroes, VR0, -8);
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vsldoi(mask_64bit, zeroes, VR0, 8);
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// Get the initial value into v8
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vxor(VR8, VR8, VR8);
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mtvrd(VR8, crc);
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vsldoi(VR8, zeroes, VR8, -8); // shift into bottom 32 bits
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vsldoi(VR8, zeroes, VR8, 8); // shift into bottom 32 bits
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li (rLoaded, 0);
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@ -4930,7 +4930,7 @@ void MacroAssembler::kernel_crc32_1word_aligned(Register crc, Register buf, Regi
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addi(barretConstants, barretConstants, 16);
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lvx(const2, barretConstants);
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vsldoi(VR1, VR0, VR0, -8);
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vsldoi(VR1, VR0, VR0, 8);
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vxor(VR0, VR0, VR1); // xor two 64 bit results together
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// shift left one bit
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@ -2729,7 +2729,7 @@ class StubGenerator: public StubCodeGenerator {
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__ vspltisb (vTmp2, -16);
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__ vrld (keyPerm, keyPerm, vTmp2);
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__ vrld (keyPerm, keyPerm, vTmp2);
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__ vsldoi (keyPerm, keyPerm, keyPerm, -8);
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__ vsldoi (keyPerm, keyPerm, keyPerm, 8);
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// load the 1st round key to vKey1
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__ li (keypos, 0);
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@ -2929,7 +2929,7 @@ class StubGenerator: public StubCodeGenerator {
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__ vspltisb (vTmp2, -16);
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__ vrld (keyPerm, keyPerm, vTmp2);
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__ vrld (keyPerm, keyPerm, vTmp2);
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__ vsldoi (keyPerm, keyPerm, keyPerm, -8);
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__ vsldoi (keyPerm, keyPerm, keyPerm, 8);
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__ cmpwi (CCR0, keylen, 44);
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__ beq (CCR0, L_do44);
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