8296515: RISC-V: Small refactoring for MaxReductionV/MinReductionV/AddReductionV node implementation
Reviewed-by: luhenry, dzhang, yzhu, fyang
This commit is contained in:
parent
82cbfb5fb0
commit
fef68bbaf6
@ -1690,27 +1690,36 @@ bool C2_MacroAssembler::in_scratch_emit_size() {
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return MacroAssembler::in_scratch_emit_size();
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}
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void C2_MacroAssembler::reduce_operation(Register dst, VectorRegister tmp,
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Register src1, VectorRegister src2,
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BasicType bt, REDUCTION_OP op) {
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void C2_MacroAssembler::rvv_reduce_integral(Register dst, VectorRegister tmp,
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Register src1, VectorRegister src2,
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BasicType bt, int opc) {
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assert(bt == T_BYTE || bt == T_SHORT || bt == T_INT || bt == T_LONG, "unsupported element type");
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Assembler::SEW sew = Assembler::elemtype_to_sew(bt);
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vsetvli(t0, x0, sew);
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vmv_s_x(tmp, src1);
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switch (op) {
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case REDUCTION_OP::ADD:
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switch (opc) {
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case Op_AddReductionVI:
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case Op_AddReductionVL:
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vredsum_vs(tmp, src2, tmp);
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break;
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case REDUCTION_OP::AND:
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case Op_AndReductionV:
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vredand_vs(tmp, src2, tmp);
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break;
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case REDUCTION_OP::OR:
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case Op_OrReductionV:
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vredor_vs(tmp, src2, tmp);
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break;
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case REDUCTION_OP::XOR:
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case Op_XorReductionV:
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vredxor_vs(tmp, src2, tmp);
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break;
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case Op_MaxReductionV:
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vredmax_vs(tmp, src2, tmp);
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break;
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case Op_MinReductionV:
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vredmin_vs(tmp, src2, tmp);
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break;
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default:
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ShouldNotReachHere();
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}
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@ -195,8 +195,8 @@
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VectorRegister tmp1, VectorRegister tmp2,
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bool is_double, bool is_min);
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void reduce_operation(Register dst, VectorRegister tmp,
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Register src1, VectorRegister src2,
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BasicType bt, REDUCTION_OP op);
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void rvv_reduce_integral(Register dst, VectorRegister tmp,
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Register src1, VectorRegister src2,
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BasicType bt, int opc);
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#endif // CPU_RISCV_C2_MACROASSEMBLER_RISCV_HPP
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@ -1300,7 +1300,4 @@ class SkipIfEqual {
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~SkipIfEqual();
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};
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// reduction related operations
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enum REDUCTION_OP {ADD, AND, OR, XOR};
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#endif // CPU_RISCV_MACROASSEMBLER_RISCV_HPP
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@ -809,7 +809,9 @@ instruct vnegD(vReg dst, vReg src) %{
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// vector and reduction
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instruct reduce_andI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
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predicate(Matcher::vector_element_basic_type(n->in(2)) != T_LONG);
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predicate(Matcher::vector_element_basic_type(n->in(2)) == T_BYTE ||
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Matcher::vector_element_basic_type(n->in(2)) == T_SHORT ||
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Matcher::vector_element_basic_type(n->in(2)) == T_INT);
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match(Set dst (AndReductionV src1 src2));
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effect(TEMP tmp);
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ins_cost(VEC_COST);
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@ -818,8 +820,8 @@ instruct reduce_andI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
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"vmv.x.s $dst, $tmp" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this, $src2);
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__ reduce_operation($dst$$Register, as_VectorRegister($tmp$$reg),
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$src1$$Register, as_VectorRegister($src2$$reg), bt, REDUCTION_OP::AND);
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__ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg),
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$src1$$Register, as_VectorRegister($src2$$reg), bt, this->ideal_Opcode());
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%}
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ins_pipe(pipe_slow);
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%}
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@ -834,8 +836,8 @@ instruct reduce_andL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
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"vmv.x.s $dst, $tmp" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this, $src2);
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__ reduce_operation($dst$$Register, as_VectorRegister($tmp$$reg),
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$src1$$Register, as_VectorRegister($src2$$reg), bt, REDUCTION_OP::AND);
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__ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg),
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$src1$$Register, as_VectorRegister($src2$$reg), bt, this->ideal_Opcode());
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%}
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ins_pipe(pipe_slow);
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%}
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@ -843,7 +845,9 @@ instruct reduce_andL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
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// vector or reduction
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instruct reduce_orI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
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predicate(Matcher::vector_element_basic_type(n->in(2)) != T_LONG);
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predicate(Matcher::vector_element_basic_type(n->in(2)) == T_BYTE ||
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Matcher::vector_element_basic_type(n->in(2)) == T_SHORT ||
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Matcher::vector_element_basic_type(n->in(2)) == T_INT);
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match(Set dst (OrReductionV src1 src2));
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effect(TEMP tmp);
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ins_cost(VEC_COST);
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@ -852,8 +856,8 @@ instruct reduce_orI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
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"vmv.x.s $dst, $tmp" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this, $src2);
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__ reduce_operation($dst$$Register, as_VectorRegister($tmp$$reg),
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$src1$$Register, as_VectorRegister($src2$$reg), bt, REDUCTION_OP::OR);
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__ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg),
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$src1$$Register, as_VectorRegister($src2$$reg), bt, this->ideal_Opcode());
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%}
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ins_pipe(pipe_slow);
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%}
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@ -868,8 +872,8 @@ instruct reduce_orL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
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"vmv.x.s $dst, $tmp" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this, $src2);
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__ reduce_operation($dst$$Register, as_VectorRegister($tmp$$reg),
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$src1$$Register, as_VectorRegister($src2$$reg), bt, REDUCTION_OP::OR);
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__ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg),
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$src1$$Register, as_VectorRegister($src2$$reg), bt, this->ideal_Opcode());
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%}
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ins_pipe(pipe_slow);
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%}
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@ -877,7 +881,9 @@ instruct reduce_orL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
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// vector xor reduction
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instruct reduce_xorI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
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predicate(Matcher::vector_element_basic_type(n->in(2)) != T_LONG);
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predicate(Matcher::vector_element_basic_type(n->in(2)) == T_BYTE ||
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Matcher::vector_element_basic_type(n->in(2)) == T_SHORT ||
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Matcher::vector_element_basic_type(n->in(2)) == T_INT);
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match(Set dst (XorReductionV src1 src2));
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effect(TEMP tmp);
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ins_cost(VEC_COST);
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@ -886,8 +892,8 @@ instruct reduce_xorI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
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"vmv.x.s $dst, $tmp" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this, $src2);
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__ reduce_operation($dst$$Register, as_VectorRegister($tmp$$reg),
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$src1$$Register, as_VectorRegister($src2$$reg), bt, REDUCTION_OP::XOR);
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__ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg),
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$src1$$Register, as_VectorRegister($src2$$reg), bt, this->ideal_Opcode());
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%}
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ins_pipe(pipe_slow);
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%}
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@ -902,82 +908,44 @@ instruct reduce_xorL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
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"vmv.x.s $dst, $tmp" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this, $src2);
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__ reduce_operation($dst$$Register, as_VectorRegister($tmp$$reg),
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$src1$$Register, as_VectorRegister($src2$$reg), bt, REDUCTION_OP::XOR);
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__ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg),
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$src1$$Register, as_VectorRegister($src2$$reg), bt, this->ideal_Opcode());
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%}
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ins_pipe(pipe_slow);
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%}
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// vector add reduction
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instruct reduce_addB(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
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predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
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match(Set dst (AddReductionVI src1 src2));
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effect(TEMP tmp);
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ins_cost(VEC_COST);
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format %{ "vmv.s.x $tmp, $src1\t#@reduce_addB\n\t"
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"vredsum.vs $tmp, $src2, $tmp\n\t"
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"vmv.x.s $dst, $tmp" %}
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ins_encode %{
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__ vsetvli(t0, x0, Assembler::e8);
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__ vmv_s_x(as_VectorRegister($tmp$$reg), $src1$$Register);
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__ vredsum_vs(as_VectorRegister($tmp$$reg), as_VectorRegister($src2$$reg),
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as_VectorRegister($tmp$$reg));
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__ vmv_x_s($dst$$Register, as_VectorRegister($tmp$$reg));
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%}
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ins_pipe(pipe_slow);
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%}
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instruct reduce_addS(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
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predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
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match(Set dst (AddReductionVI src1 src2));
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effect(TEMP tmp);
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ins_cost(VEC_COST);
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format %{ "vmv.s.x $tmp, $src1\t#@reduce_addS\n\t"
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"vredsum.vs $tmp, $src2, $tmp\n\t"
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"vmv.x.s $dst, $tmp" %}
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ins_encode %{
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__ vsetvli(t0, x0, Assembler::e16);
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__ vmv_s_x(as_VectorRegister($tmp$$reg), $src1$$Register);
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__ vredsum_vs(as_VectorRegister($tmp$$reg), as_VectorRegister($src2$$reg),
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as_VectorRegister($tmp$$reg));
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__ vmv_x_s($dst$$Register, as_VectorRegister($tmp$$reg));
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%}
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ins_pipe(pipe_slow);
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%}
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instruct reduce_addI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
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predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
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predicate(Matcher::vector_element_basic_type(n->in(2)) == T_BYTE ||
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Matcher::vector_element_basic_type(n->in(2)) == T_SHORT ||
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Matcher::vector_element_basic_type(n->in(2)) == T_INT);
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match(Set dst (AddReductionVI src1 src2));
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effect(TEMP tmp);
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ins_cost(VEC_COST);
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format %{ "vmv.s.x $tmp, $src1\t#@reduce_addI\n\t"
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"vredsum.vs $tmp, $src2, $tmp\n\t"
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"vmv.x.s $dst, $tmp" %}
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"vmv.x.s $dst, $tmp" %}
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ins_encode %{
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__ vsetvli(t0, x0, Assembler::e32);
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__ vmv_s_x(as_VectorRegister($tmp$$reg), $src1$$Register);
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__ vredsum_vs(as_VectorRegister($tmp$$reg), as_VectorRegister($src2$$reg),
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as_VectorRegister($tmp$$reg));
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__ vmv_x_s($dst$$Register, as_VectorRegister($tmp$$reg));
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BasicType bt = Matcher::vector_element_basic_type(this, $src2);
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__ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg),
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$src1$$Register, as_VectorRegister($src2$$reg), bt, this->ideal_Opcode());
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%}
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ins_pipe(pipe_slow);
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%}
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instruct reduce_addL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
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predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
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predicate(Matcher::vector_element_basic_type(n->in(2)) == T_LONG);
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match(Set dst (AddReductionVL src1 src2));
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effect(TEMP tmp);
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ins_cost(VEC_COST);
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format %{ "vmv.s.x $tmp, $src1\t#@reduce_addL\n\t"
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"vredsum.vs $tmp, $src2, $tmp\n\t"
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"vmv.x.s $dst, $tmp" %}
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"vmv.x.s $dst, $tmp" %}
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ins_encode %{
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__ vsetvli(t0, x0, Assembler::e64);
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__ vmv_s_x(as_VectorRegister($tmp$$reg), $src1$$Register);
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__ vredsum_vs(as_VectorRegister($tmp$$reg), as_VectorRegister($src2$$reg),
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as_VectorRegister($tmp$$reg));
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__ vmv_x_s($dst$$Register, as_VectorRegister($tmp$$reg));
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BasicType bt = Matcher::vector_element_basic_type(this, $src2);
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__ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg),
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$src1$$Register, as_VectorRegister($src2$$reg), bt, this->ideal_Opcode());
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%}
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ins_pipe(pipe_slow);
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%}
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@ -1017,135 +985,65 @@ instruct reduce_addD(fRegD src1_dst, vReg src2, vReg tmp) %{
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%}
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// vector integer max reduction
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instruct vreduce_maxB(iRegINoSp dst, iRegI src1, vReg src2, vReg tmp) %{
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predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
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match(Set dst (MaxReductionV src1 src2));
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ins_cost(VEC_COST);
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effect(TEMP tmp);
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format %{ "vreduce_maxB $dst, $src1, $src2, $tmp" %}
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ins_encode %{
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__ vsetvli(t0, x0, Assembler::e8);
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__ vredmax_vs(as_VectorRegister($tmp$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($src2$$reg));
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__ vmv_x_s($dst$$Register, as_VectorRegister($tmp$$reg));
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Label Ldone;
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__ ble(as_Register($src1$$reg), as_Register($dst$$reg), Ldone);
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__ mv(as_Register($dst$$reg), as_Register($src1$$reg));
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__ bind(Ldone);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct vreduce_maxS(iRegINoSp dst, iRegI src1, vReg src2, vReg tmp) %{
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predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
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match(Set dst (MaxReductionV src1 src2));
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ins_cost(VEC_COST);
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effect(TEMP tmp);
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format %{ "vreduce_maxS $dst, $src1, $src2, $tmp" %}
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ins_encode %{
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__ vsetvli(t0, x0, Assembler::e16);
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__ vredmax_vs(as_VectorRegister($tmp$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($src2$$reg));
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__ vmv_x_s($dst$$Register, as_VectorRegister($tmp$$reg));
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Label Ldone;
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__ ble(as_Register($src1$$reg), as_Register($dst$$reg), Ldone);
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__ mv(as_Register($dst$$reg), as_Register($src1$$reg));
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__ bind(Ldone);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct vreduce_maxI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
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predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
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predicate(Matcher::vector_element_basic_type(n->in(2)) == T_BYTE ||
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Matcher::vector_element_basic_type(n->in(2)) == T_SHORT ||
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Matcher::vector_element_basic_type(n->in(2)) == T_INT);
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match(Set dst (MaxReductionV src1 src2));
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ins_cost(VEC_COST);
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effect(TEMP tmp);
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format %{ "vreduce_maxI $dst, $src1, $src2, $tmp" %}
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ins_encode %{
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__ vsetvli(t0, x0, Assembler::e32);
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__ vmv_s_x(as_VectorRegister($tmp$$reg), $src1$$Register);
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__ vredmax_vs(as_VectorRegister($tmp$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($tmp$$reg));
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__ vmv_x_s($dst$$Register, as_VectorRegister($tmp$$reg));
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BasicType bt = Matcher::vector_element_basic_type(this, $src2);
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__ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg),
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$src1$$Register, as_VectorRegister($src2$$reg), bt, this->ideal_Opcode());
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%}
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ins_pipe(pipe_slow);
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%}
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instruct vreduce_maxL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
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predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
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predicate(Matcher::vector_element_basic_type(n->in(2)) == T_LONG);
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match(Set dst (MaxReductionV src1 src2));
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ins_cost(VEC_COST);
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effect(TEMP tmp);
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format %{ "vreduce_maxL $dst, $src1, $src2, $tmp" %}
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ins_encode %{
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__ vsetvli(t0, x0, Assembler::e64);
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__ vmv_s_x(as_VectorRegister($tmp$$reg), $src1$$Register);
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__ vredmax_vs(as_VectorRegister($tmp$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($tmp$$reg));
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__ vmv_x_s($dst$$Register, as_VectorRegister($tmp$$reg));
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BasicType bt = Matcher::vector_element_basic_type(this, $src2);
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__ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg),
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$src1$$Register, as_VectorRegister($src2$$reg), bt, this->ideal_Opcode());
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%}
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ins_pipe(pipe_slow);
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%}
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// vector integer min reduction
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instruct vreduce_minB(iRegINoSp dst, iRegI src1, vReg src2, vReg tmp) %{
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predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
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match(Set dst (MinReductionV src1 src2));
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ins_cost(VEC_COST);
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effect(TEMP tmp);
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format %{ "vreduce_minB $dst, $src1, $src2, $tmp" %}
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ins_encode %{
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__ vsetvli(t0, x0, Assembler::e8);
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__ vredmin_vs(as_VectorRegister($tmp$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($src2$$reg));
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__ vmv_x_s($dst$$Register, as_VectorRegister($tmp$$reg));
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Label Ldone;
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__ bge(as_Register($src1$$reg), as_Register($dst$$reg), Ldone);
|
||||
__ mv(as_Register($dst$$reg), as_Register($src1$$reg));
|
||||
__ bind(Ldone);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct vreduce_minS(iRegINoSp dst, iRegI src1, vReg src2, vReg tmp) %{
|
||||
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
|
||||
match(Set dst (MinReductionV src1 src2));
|
||||
ins_cost(VEC_COST);
|
||||
effect(TEMP tmp);
|
||||
format %{ "vreduce_minS $dst, $src1, $src2, $tmp" %}
|
||||
ins_encode %{
|
||||
__ vsetvli(t0, x0, Assembler::e16);
|
||||
__ vredmin_vs(as_VectorRegister($tmp$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($src2$$reg));
|
||||
__ vmv_x_s($dst$$Register, as_VectorRegister($tmp$$reg));
|
||||
Label Ldone;
|
||||
__ bge(as_Register($src1$$reg), as_Register($dst$$reg), Ldone);
|
||||
__ mv(as_Register($dst$$reg), as_Register($src1$$reg));
|
||||
__ bind(Ldone);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct vreduce_minI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
|
||||
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
|
||||
predicate(Matcher::vector_element_basic_type(n->in(2)) == T_BYTE ||
|
||||
Matcher::vector_element_basic_type(n->in(2)) == T_SHORT ||
|
||||
Matcher::vector_element_basic_type(n->in(2)) == T_INT);
|
||||
match(Set dst (MinReductionV src1 src2));
|
||||
ins_cost(VEC_COST);
|
||||
effect(TEMP tmp);
|
||||
format %{ "vreduce_minI $dst, $src1, $src2, $tmp" %}
|
||||
ins_encode %{
|
||||
__ vsetvli(t0, x0, Assembler::e32);
|
||||
__ vmv_s_x(as_VectorRegister($tmp$$reg), $src1$$Register);
|
||||
__ vredmin_vs(as_VectorRegister($tmp$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($tmp$$reg));
|
||||
__ vmv_x_s($dst$$Register, as_VectorRegister($tmp$$reg));
|
||||
BasicType bt = Matcher::vector_element_basic_type(this, $src2);
|
||||
__ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg),
|
||||
$src1$$Register, as_VectorRegister($src2$$reg), bt, this->ideal_Opcode());
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct vreduce_minL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
|
||||
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
|
||||
predicate(Matcher::vector_element_basic_type(n->in(2)) == T_LONG);
|
||||
match(Set dst (MinReductionV src1 src2));
|
||||
ins_cost(VEC_COST);
|
||||
effect(TEMP tmp);
|
||||
format %{ "vreduce_minL $dst, $src1, $src2, $tmp" %}
|
||||
ins_encode %{
|
||||
__ vsetvli(t0, x0, Assembler::e64);
|
||||
__ vmv_s_x(as_VectorRegister($tmp$$reg), $src1$$Register);
|
||||
__ vredmin_vs(as_VectorRegister($tmp$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($tmp$$reg));
|
||||
__ vmv_x_s($dst$$Register, as_VectorRegister($tmp$$reg));
|
||||
BasicType bt = Matcher::vector_element_basic_type(this, $src2);
|
||||
__ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg),
|
||||
$src1$$Register, as_VectorRegister($src2$$reg), bt, this->ideal_Opcode());
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
Loading…
x
Reference in New Issue
Block a user