399 lines
12 KiB
C++
399 lines
12 KiB
C++
/*
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* Copyright (c) 1999, 2019, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2012, 2019 SAP SE. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#include "precompiled.hpp"
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#include "c1/c1_FrameMap.hpp"
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#include "c1/c1_LIR.hpp"
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#include "runtime/sharedRuntime.hpp"
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#include "vmreg_ppc.inline.hpp"
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const int FrameMap::pd_c_runtime_reserved_arg_size = 7;
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LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool outgoing) {
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LIR_Opr opr = LIR_OprFact::illegalOpr;
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VMReg r_1 = reg->first();
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VMReg r_2 = reg->second();
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if (r_1->is_stack()) {
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// Convert stack slot to an SP offset.
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// The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value
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// so we must add it in here.
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int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
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opr = LIR_OprFact::address(new LIR_Address(SP_opr, st_off + STACK_BIAS, type));
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} else if (r_1->is_Register()) {
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Register reg = r_1->as_Register();
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//if (outgoing) {
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// assert(!reg->is_in(), "should be using I regs");
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//} else {
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// assert(!reg->is_out(), "should be using O regs");
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//}
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if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
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opr = as_long_opr(reg);
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} else if (is_reference_type(type)) {
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opr = as_oop_opr(reg);
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} else if (type == T_METADATA) {
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opr = as_metadata_opr(reg);
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} else if (type == T_ADDRESS) {
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opr = as_address_opr(reg);
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} else {
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opr = as_opr(reg);
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}
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} else if (r_1->is_FloatRegister()) {
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assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
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FloatRegister f = r_1->as_FloatRegister();
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if (type == T_DOUBLE) {
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opr = as_double_opr(f);
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} else {
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opr = as_float_opr(f);
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}
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}
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return opr;
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}
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// FrameMap
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//--------------------------------------------------------
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FloatRegister FrameMap::_fpu_regs [FrameMap::nof_fpu_regs];
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LIR_Opr FrameMap::R0_opr;
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LIR_Opr FrameMap::R1_opr;
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LIR_Opr FrameMap::R2_opr;
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LIR_Opr FrameMap::R3_opr;
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LIR_Opr FrameMap::R4_opr;
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LIR_Opr FrameMap::R5_opr;
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LIR_Opr FrameMap::R6_opr;
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LIR_Opr FrameMap::R7_opr;
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LIR_Opr FrameMap::R8_opr;
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LIR_Opr FrameMap::R9_opr;
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LIR_Opr FrameMap::R10_opr;
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LIR_Opr FrameMap::R11_opr;
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LIR_Opr FrameMap::R12_opr;
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LIR_Opr FrameMap::R13_opr;
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LIR_Opr FrameMap::R14_opr;
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LIR_Opr FrameMap::R15_opr;
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LIR_Opr FrameMap::R16_opr;
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LIR_Opr FrameMap::R17_opr;
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LIR_Opr FrameMap::R18_opr;
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LIR_Opr FrameMap::R19_opr;
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LIR_Opr FrameMap::R20_opr;
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LIR_Opr FrameMap::R21_opr;
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LIR_Opr FrameMap::R22_opr;
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LIR_Opr FrameMap::R23_opr;
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LIR_Opr FrameMap::R24_opr;
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LIR_Opr FrameMap::R25_opr;
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LIR_Opr FrameMap::R26_opr;
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LIR_Opr FrameMap::R27_opr;
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LIR_Opr FrameMap::R28_opr;
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LIR_Opr FrameMap::R29_opr;
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LIR_Opr FrameMap::R30_opr;
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LIR_Opr FrameMap::R31_opr;
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LIR_Opr FrameMap::R0_oop_opr;
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//LIR_Opr FrameMap::R1_oop_opr;
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LIR_Opr FrameMap::R2_oop_opr;
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LIR_Opr FrameMap::R3_oop_opr;
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LIR_Opr FrameMap::R4_oop_opr;
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LIR_Opr FrameMap::R5_oop_opr;
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LIR_Opr FrameMap::R6_oop_opr;
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LIR_Opr FrameMap::R7_oop_opr;
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LIR_Opr FrameMap::R8_oop_opr;
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LIR_Opr FrameMap::R9_oop_opr;
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LIR_Opr FrameMap::R10_oop_opr;
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LIR_Opr FrameMap::R11_oop_opr;
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LIR_Opr FrameMap::R12_oop_opr;
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//LIR_Opr FrameMap::R13_oop_opr;
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LIR_Opr FrameMap::R14_oop_opr;
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LIR_Opr FrameMap::R15_oop_opr;
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//LIR_Opr FrameMap::R16_oop_opr;
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LIR_Opr FrameMap::R17_oop_opr;
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LIR_Opr FrameMap::R18_oop_opr;
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LIR_Opr FrameMap::R19_oop_opr;
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LIR_Opr FrameMap::R20_oop_opr;
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LIR_Opr FrameMap::R21_oop_opr;
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LIR_Opr FrameMap::R22_oop_opr;
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LIR_Opr FrameMap::R23_oop_opr;
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LIR_Opr FrameMap::R24_oop_opr;
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LIR_Opr FrameMap::R25_oop_opr;
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LIR_Opr FrameMap::R26_oop_opr;
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LIR_Opr FrameMap::R27_oop_opr;
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LIR_Opr FrameMap::R28_oop_opr;
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//LIR_Opr FrameMap::R29_oop_opr;
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LIR_Opr FrameMap::R30_oop_opr;
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LIR_Opr FrameMap::R31_oop_opr;
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LIR_Opr FrameMap::R0_metadata_opr;
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//LIR_Opr FrameMap::R1_metadata_opr;
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LIR_Opr FrameMap::R2_metadata_opr;
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LIR_Opr FrameMap::R3_metadata_opr;
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LIR_Opr FrameMap::R4_metadata_opr;
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LIR_Opr FrameMap::R5_metadata_opr;
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LIR_Opr FrameMap::R6_metadata_opr;
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LIR_Opr FrameMap::R7_metadata_opr;
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LIR_Opr FrameMap::R8_metadata_opr;
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LIR_Opr FrameMap::R9_metadata_opr;
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LIR_Opr FrameMap::R10_metadata_opr;
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LIR_Opr FrameMap::R11_metadata_opr;
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LIR_Opr FrameMap::R12_metadata_opr;
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//LIR_Opr FrameMap::R13_metadata_opr;
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LIR_Opr FrameMap::R14_metadata_opr;
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LIR_Opr FrameMap::R15_metadata_opr;
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//LIR_Opr FrameMap::R16_metadata_opr;
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LIR_Opr FrameMap::R17_metadata_opr;
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LIR_Opr FrameMap::R18_metadata_opr;
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LIR_Opr FrameMap::R19_metadata_opr;
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LIR_Opr FrameMap::R20_metadata_opr;
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LIR_Opr FrameMap::R21_metadata_opr;
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LIR_Opr FrameMap::R22_metadata_opr;
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LIR_Opr FrameMap::R23_metadata_opr;
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LIR_Opr FrameMap::R24_metadata_opr;
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LIR_Opr FrameMap::R25_metadata_opr;
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LIR_Opr FrameMap::R26_metadata_opr;
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LIR_Opr FrameMap::R27_metadata_opr;
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LIR_Opr FrameMap::R28_metadata_opr;
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//LIR_Opr FrameMap::R29_metadata_opr;
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LIR_Opr FrameMap::R30_metadata_opr;
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LIR_Opr FrameMap::R31_metadata_opr;
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LIR_Opr FrameMap::SP_opr;
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LIR_Opr FrameMap::R0_long_opr;
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LIR_Opr FrameMap::R3_long_opr;
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LIR_Opr FrameMap::F1_opr;
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LIR_Opr FrameMap::F1_double_opr;
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LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
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LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
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FloatRegister FrameMap::nr2floatreg (int rnr) {
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assert(_init_done, "tables not initialized");
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debug_only(fpu_range_check(rnr);)
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return _fpu_regs[rnr];
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}
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// Returns true if reg could be smashed by a callee.
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bool FrameMap::is_caller_save_register (LIR_Opr reg) {
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if (reg->is_single_fpu() || reg->is_double_fpu()) { return true; }
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if (reg->is_double_cpu()) {
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return is_caller_save_register(reg->as_register_lo()) ||
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is_caller_save_register(reg->as_register_hi());
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}
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return is_caller_save_register(reg->as_register());
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}
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bool FrameMap::is_caller_save_register (Register r) {
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// not visible to allocator: R0: scratch, R1: SP
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// r->encoding() < 2 + nof_caller_save_cpu_regs();
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return true; // Currently all regs are caller save.
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}
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void FrameMap::initialize() {
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assert(!_init_done, "once");
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int i = 0;
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// Put generally available registers at the beginning (allocated, saved for GC).
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for (int j = 0; j < nof_cpu_regs; ++j) {
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Register rj = as_Register(j);
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if (reg_needs_save(rj)) {
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map_register(i++, rj);
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}
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}
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assert(i == nof_cpu_regs_reg_alloc, "number of allocated registers");
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// The following registers are not normally available.
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for (int j = 0; j < nof_cpu_regs; ++j) {
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Register rj = as_Register(j);
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if (!reg_needs_save(rj)) {
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map_register(i++, rj);
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}
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}
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assert(i == nof_cpu_regs, "number of CPU registers");
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for (i = 0; i < nof_fpu_regs; i++) {
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_fpu_regs[i] = as_FloatRegister(i);
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}
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_init_done = true;
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R0_opr = as_opr(R0);
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R1_opr = as_opr(R1);
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R2_opr = as_opr(R2);
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R3_opr = as_opr(R3);
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R4_opr = as_opr(R4);
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R5_opr = as_opr(R5);
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R6_opr = as_opr(R6);
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R7_opr = as_opr(R7);
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R8_opr = as_opr(R8);
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R9_opr = as_opr(R9);
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R10_opr = as_opr(R10);
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R11_opr = as_opr(R11);
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R12_opr = as_opr(R12);
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R13_opr = as_opr(R13);
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R14_opr = as_opr(R14);
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R15_opr = as_opr(R15);
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R16_opr = as_opr(R16);
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R17_opr = as_opr(R17);
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R18_opr = as_opr(R18);
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R19_opr = as_opr(R19);
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R20_opr = as_opr(R20);
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R21_opr = as_opr(R21);
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R22_opr = as_opr(R22);
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R23_opr = as_opr(R23);
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R24_opr = as_opr(R24);
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R25_opr = as_opr(R25);
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R26_opr = as_opr(R26);
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R27_opr = as_opr(R27);
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R28_opr = as_opr(R28);
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R29_opr = as_opr(R29);
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R30_opr = as_opr(R30);
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R31_opr = as_opr(R31);
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R0_oop_opr = as_oop_opr(R0);
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//R1_oop_opr = as_oop_opr(R1);
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R2_oop_opr = as_oop_opr(R2);
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R3_oop_opr = as_oop_opr(R3);
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R4_oop_opr = as_oop_opr(R4);
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R5_oop_opr = as_oop_opr(R5);
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R6_oop_opr = as_oop_opr(R6);
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R7_oop_opr = as_oop_opr(R7);
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R8_oop_opr = as_oop_opr(R8);
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R9_oop_opr = as_oop_opr(R9);
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R10_oop_opr = as_oop_opr(R10);
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R11_oop_opr = as_oop_opr(R11);
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R12_oop_opr = as_oop_opr(R12);
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//R13_oop_opr = as_oop_opr(R13);
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R14_oop_opr = as_oop_opr(R14);
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R15_oop_opr = as_oop_opr(R15);
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//R16_oop_opr = as_oop_opr(R16);
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R17_oop_opr = as_oop_opr(R17);
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R18_oop_opr = as_oop_opr(R18);
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R19_oop_opr = as_oop_opr(R19);
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R20_oop_opr = as_oop_opr(R20);
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R21_oop_opr = as_oop_opr(R21);
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R22_oop_opr = as_oop_opr(R22);
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R23_oop_opr = as_oop_opr(R23);
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R24_oop_opr = as_oop_opr(R24);
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R25_oop_opr = as_oop_opr(R25);
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R26_oop_opr = as_oop_opr(R26);
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R27_oop_opr = as_oop_opr(R27);
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R28_oop_opr = as_oop_opr(R28);
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//R29_oop_opr = as_oop_opr(R29);
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R30_oop_opr = as_oop_opr(R30);
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R31_oop_opr = as_oop_opr(R31);
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R0_metadata_opr = as_metadata_opr(R0);
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//R1_metadata_opr = as_metadata_opr(R1);
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R2_metadata_opr = as_metadata_opr(R2);
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R3_metadata_opr = as_metadata_opr(R3);
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R4_metadata_opr = as_metadata_opr(R4);
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R5_metadata_opr = as_metadata_opr(R5);
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R6_metadata_opr = as_metadata_opr(R6);
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R7_metadata_opr = as_metadata_opr(R7);
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R8_metadata_opr = as_metadata_opr(R8);
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R9_metadata_opr = as_metadata_opr(R9);
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R10_metadata_opr = as_metadata_opr(R10);
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R11_metadata_opr = as_metadata_opr(R11);
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R12_metadata_opr = as_metadata_opr(R12);
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//R13_metadata_opr = as_metadata_opr(R13);
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R14_metadata_opr = as_metadata_opr(R14);
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R15_metadata_opr = as_metadata_opr(R15);
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//R16_metadata_opr = as_metadata_opr(R16);
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R17_metadata_opr = as_metadata_opr(R17);
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R18_metadata_opr = as_metadata_opr(R18);
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R19_metadata_opr = as_metadata_opr(R19);
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R20_metadata_opr = as_metadata_opr(R20);
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R21_metadata_opr = as_metadata_opr(R21);
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R22_metadata_opr = as_metadata_opr(R22);
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R23_metadata_opr = as_metadata_opr(R23);
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R24_metadata_opr = as_metadata_opr(R24);
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R25_metadata_opr = as_metadata_opr(R25);
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R26_metadata_opr = as_metadata_opr(R26);
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R27_metadata_opr = as_metadata_opr(R27);
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R28_metadata_opr = as_metadata_opr(R28);
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//R29_metadata_opr = as_metadata_opr(R29);
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R30_metadata_opr = as_metadata_opr(R30);
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R31_metadata_opr = as_metadata_opr(R31);
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SP_opr = as_pointer_opr(R1_SP);
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R0_long_opr = LIR_OprFact::double_cpu(cpu_reg2rnr(R0), cpu_reg2rnr(R0));
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R3_long_opr = LIR_OprFact::double_cpu(cpu_reg2rnr(R3), cpu_reg2rnr(R3));
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F1_opr = as_float_opr(F1);
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F1_double_opr = as_double_opr(F1);
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// All the allocated cpu regs are caller saved.
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for (int i = 0; i < max_nof_caller_save_cpu_regs; i++) {
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_caller_save_cpu_regs[i] = LIR_OprFact::single_cpu(i);
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}
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// All the fpu regs are caller saved.
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for (int i = 0; i < nof_caller_save_fpu_regs; i++) {
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_caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
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}
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}
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Address FrameMap::make_new_address(ByteSize sp_offset) const {
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return Address(R1_SP, STACK_BIAS + in_bytes(sp_offset));
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}
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VMReg FrameMap::fpu_regname (int n) {
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return as_FloatRegister(n)->as_VMReg();
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}
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LIR_Opr FrameMap::stack_pointer() {
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return SP_opr;
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}
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// JSR 292
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// On PPC64, there is no need to save the SP, because neither
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// method handle intrinsics, nor compiled lambda forms modify it.
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LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() {
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return LIR_OprFact::illegalOpr;
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}
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bool FrameMap::validate_frame() {
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int max_offset = in_bytes(framesize_in_bytes());
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int java_index = 0;
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for (int i = 0; i < _incoming_arguments->length(); i++) {
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LIR_Opr opr = _incoming_arguments->at(i);
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if (opr->is_stack()) {
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max_offset = MAX2(_argument_locations->at(java_index), max_offset);
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}
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java_index += type2size[opr->type()];
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}
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return Assembler::is_simm16(max_offset + STACK_BIAS);
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|
}
|