442 lines
14 KiB
C++
442 lines
14 KiB
C++
/*
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* Copyright 1997-2006 Sun Microsystems, Inc. All Rights Reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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* CA 95054 USA or visit www.sun.com if you need additional information or
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* have any questions.
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*
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*/
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class VM_Version: public Abstract_VM_Version {
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public:
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// cpuid result register layouts. These are all unions of a uint32_t
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// (in case anyone wants access to the register as a whole) and a bitfield.
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union StdCpuid1Eax {
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uint32_t value;
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struct {
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uint32_t stepping : 4,
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model : 4,
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family : 4,
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proc_type : 2,
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: 2,
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ext_model : 4,
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ext_family : 8,
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: 4;
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} bits;
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};
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union StdCpuid1Ebx { // example, unused
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uint32_t value;
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struct {
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uint32_t brand_id : 8,
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clflush_size : 8,
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threads_per_cpu : 8,
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apic_id : 8;
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} bits;
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};
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union StdCpuid1Ecx {
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uint32_t value;
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struct {
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uint32_t sse3 : 1,
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: 2,
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monitor : 1,
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: 1,
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vmx : 1,
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: 1,
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est : 1,
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: 1,
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ssse3 : 1,
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cid : 1,
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: 2,
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cmpxchg16: 1,
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: 4,
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dca : 1,
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: 4,
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popcnt : 1,
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: 8;
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} bits;
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};
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union StdCpuid1Edx {
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uint32_t value;
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struct {
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uint32_t : 4,
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tsc : 1,
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: 3,
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cmpxchg8 : 1,
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: 6,
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cmov : 1,
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: 7,
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mmx : 1,
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fxsr : 1,
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sse : 1,
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sse2 : 1,
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: 1,
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ht : 1,
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: 3;
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} bits;
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};
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union DcpCpuid4Eax {
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uint32_t value;
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struct {
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uint32_t cache_type : 5,
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: 21,
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cores_per_cpu : 6;
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} bits;
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};
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union DcpCpuid4Ebx {
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uint32_t value;
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struct {
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uint32_t L1_line_size : 12,
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partitions : 10,
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associativity : 10;
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} bits;
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};
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union ExtCpuid1Ecx {
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uint32_t value;
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struct {
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uint32_t LahfSahf : 1,
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CmpLegacy : 1,
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: 4,
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abm : 1,
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sse4a : 1,
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misalignsse : 1,
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prefetchw : 1,
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: 22;
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} bits;
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};
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union ExtCpuid1Edx {
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uint32_t value;
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struct {
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uint32_t : 22,
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mmx_amd : 1,
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mmx : 1,
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fxsr : 1,
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: 4,
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long_mode : 1,
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tdnow2 : 1,
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tdnow : 1;
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} bits;
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};
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union ExtCpuid5Ex {
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uint32_t value;
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struct {
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uint32_t L1_line_size : 8,
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L1_tag_lines : 8,
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L1_assoc : 8,
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L1_size : 8;
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} bits;
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};
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union ExtCpuid8Ecx {
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uint32_t value;
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struct {
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uint32_t cores_per_cpu : 8,
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: 24;
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} bits;
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};
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protected:
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static int _cpu;
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static int _model;
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static int _stepping;
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static int _cpuFeatures; // features returned by the "cpuid" instruction
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// 0 if this instruction is not available
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static const char* _features_str;
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enum {
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CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX)
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CPU_CMOV = (1 << 1),
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CPU_FXSR = (1 << 2),
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CPU_HT = (1 << 3),
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CPU_MMX = (1 << 4),
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CPU_3DNOW= (1 << 5), // 3DNow comes from cpuid 0x80000001 (EDX)
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CPU_SSE = (1 << 6),
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CPU_SSE2 = (1 << 7),
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CPU_SSE3 = (1 << 8), // sse3 comes from cpuid 1 (ECX)
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CPU_SSSE3= (1 << 9),
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CPU_SSE4 = (1 <<10),
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CPU_SSE4A= (1 <<11)
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} cpuFeatureFlags;
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// cpuid information block. All info derived from executing cpuid with
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// various function numbers is stored here. Intel and AMD info is
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// merged in this block: accessor methods disentangle it.
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//
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// The info block is laid out in subblocks of 4 dwords corresponding to
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// rax, rbx, rcx and rdx, whether or not they contain anything useful.
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struct CpuidInfo {
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// cpuid function 0
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uint32_t std_max_function;
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uint32_t std_vendor_name_0;
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uint32_t std_vendor_name_1;
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uint32_t std_vendor_name_2;
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// cpuid function 1
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StdCpuid1Eax std_cpuid1_rax;
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StdCpuid1Ebx std_cpuid1_rbx;
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StdCpuid1Ecx std_cpuid1_rcx;
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StdCpuid1Edx std_cpuid1_rdx;
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// cpuid function 4 (deterministic cache parameters)
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DcpCpuid4Eax dcp_cpuid4_rax;
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DcpCpuid4Ebx dcp_cpuid4_rbx;
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uint32_t dcp_cpuid4_rcx; // unused currently
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uint32_t dcp_cpuid4_rdx; // unused currently
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// cpuid function 0x80000000 // example, unused
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uint32_t ext_max_function;
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uint32_t ext_vendor_name_0;
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uint32_t ext_vendor_name_1;
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uint32_t ext_vendor_name_2;
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// cpuid function 0x80000001
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uint32_t ext_cpuid1_rax; // reserved
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uint32_t ext_cpuid1_rbx; // reserved
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ExtCpuid1Ecx ext_cpuid1_rcx;
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ExtCpuid1Edx ext_cpuid1_rdx;
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// cpuid functions 0x80000002 thru 0x80000004: example, unused
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uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
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uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
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uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
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// cpuid function 0x80000005 //AMD L1, Intel reserved
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uint32_t ext_cpuid5_rax; // unused currently
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uint32_t ext_cpuid5_rbx; // reserved
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ExtCpuid5Ex ext_cpuid5_rcx; // L1 data cache info (AMD)
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ExtCpuid5Ex ext_cpuid5_rdx; // L1 instruction cache info (AMD)
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// cpuid function 0x80000008
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uint32_t ext_cpuid8_rax; // unused currently
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uint32_t ext_cpuid8_rbx; // reserved
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ExtCpuid8Ecx ext_cpuid8_rcx;
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uint32_t ext_cpuid8_rdx; // reserved
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};
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// The actual cpuid info block
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static CpuidInfo _cpuid_info;
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// Extractors and predicates
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static bool is_extended_cpu_family() {
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const uint32_t Extended_Cpu_Family = 0xf;
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return _cpuid_info.std_cpuid1_rax.bits.family == Extended_Cpu_Family;
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}
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static uint32_t extended_cpu_family() {
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uint32_t result = _cpuid_info.std_cpuid1_rax.bits.family;
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if (is_extended_cpu_family()) {
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result += _cpuid_info.std_cpuid1_rax.bits.ext_family;
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}
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return result;
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}
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static uint32_t extended_cpu_model() {
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uint32_t result = _cpuid_info.std_cpuid1_rax.bits.model;
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if (is_extended_cpu_family()) {
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result |= _cpuid_info.std_cpuid1_rax.bits.ext_model << 4;
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}
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return result;
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}
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static uint32_t cpu_stepping() {
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uint32_t result = _cpuid_info.std_cpuid1_rax.bits.stepping;
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return result;
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}
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static uint logical_processor_count() {
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uint result = threads_per_core();
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return result;
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}
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static uint32_t feature_flags() {
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uint32_t result = 0;
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if (_cpuid_info.std_cpuid1_rdx.bits.cmpxchg8 != 0)
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result |= CPU_CX8;
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if (_cpuid_info.std_cpuid1_rdx.bits.cmov != 0)
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result |= CPU_CMOV;
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if (_cpuid_info.std_cpuid1_rdx.bits.fxsr != 0 || is_amd() &&
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_cpuid_info.ext_cpuid1_rdx.bits.fxsr != 0)
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result |= CPU_FXSR;
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// HT flag is set for multi-core processors also.
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if (threads_per_core() > 1)
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result |= CPU_HT;
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if (_cpuid_info.std_cpuid1_rdx.bits.mmx != 0 || is_amd() &&
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_cpuid_info.ext_cpuid1_rdx.bits.mmx != 0)
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result |= CPU_MMX;
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if (is_amd() && _cpuid_info.ext_cpuid1_rdx.bits.tdnow != 0)
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result |= CPU_3DNOW;
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if (_cpuid_info.std_cpuid1_rdx.bits.sse != 0)
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result |= CPU_SSE;
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if (_cpuid_info.std_cpuid1_rdx.bits.sse2 != 0)
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result |= CPU_SSE2;
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if (_cpuid_info.std_cpuid1_rcx.bits.sse3 != 0)
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result |= CPU_SSE3;
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if (_cpuid_info.std_cpuid1_rcx.bits.ssse3 != 0)
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result |= CPU_SSSE3;
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if (is_amd() && _cpuid_info.ext_cpuid1_rcx.bits.sse4a != 0)
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result |= CPU_SSE4A;
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return result;
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}
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static void get_processor_features();
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public:
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// Offsets for cpuid asm stub
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static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
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static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_rax); }
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static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_rax); }
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static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_rax); }
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static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_rax); }
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static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_rax); }
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// Initialization
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static void initialize();
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// Asserts
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static void assert_is_initialized() {
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assert(_cpuid_info.std_cpuid1_rax.bits.family != 0, "VM_Version not initialized");
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}
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//
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// Processor family:
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// 3 - 386
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// 4 - 486
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// 5 - Pentium
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// 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
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// Pentium M, Core Solo, Core Duo, Core2 Duo
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// family 6 model: 9, 13, 14, 15
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// 0x0f - Pentium 4, Opteron
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//
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// Note: The cpu family should be used to select between
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// instruction sequences which are valid on all Intel
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// processors. Use the feature test functions below to
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// determine whether a particular instruction is supported.
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//
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static int cpu_family() { return _cpu;}
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static bool is_P6() { return cpu_family() >= 6; }
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static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
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static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
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static uint cores_per_cpu() {
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uint result = 1;
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if (is_intel()) {
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result = (_cpuid_info.dcp_cpuid4_rax.bits.cores_per_cpu + 1);
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} else if (is_amd()) {
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result = (_cpuid_info.ext_cpuid8_rcx.bits.cores_per_cpu + 1);
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}
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return result;
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}
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static uint threads_per_core() {
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uint result = 1;
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if (_cpuid_info.std_cpuid1_rdx.bits.ht != 0) {
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result = _cpuid_info.std_cpuid1_rbx.bits.threads_per_cpu /
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cores_per_cpu();
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}
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return result;
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}
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static intx L1_data_cache_line_size() {
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intx result = 0;
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if (is_intel()) {
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result = (_cpuid_info.dcp_cpuid4_rbx.bits.L1_line_size + 1);
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} else if (is_amd()) {
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result = _cpuid_info.ext_cpuid5_rcx.bits.L1_line_size;
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}
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if (result < 32) // not defined ?
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result = 32; // 32 bytes by default on x86
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return result;
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}
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//
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// Feature identification
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//
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static bool supports_cpuid() { return _cpuFeatures != 0; }
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static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; }
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static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; }
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static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; }
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static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; }
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static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; }
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static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; }
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static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; }
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static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; }
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static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; }
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static bool supports_sse4() { return (_cpuFeatures & CPU_SSE4) != 0; }
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//
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// AMD features
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//
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static bool supports_3dnow() { return (_cpuFeatures & CPU_3DNOW) != 0; }
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static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_rdx.bits.mmx_amd != 0; }
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static bool supports_3dnow2() { return is_amd() && _cpuid_info.ext_cpuid1_rdx.bits.tdnow2 != 0; }
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static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; }
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static bool supports_compare_and_exchange() { return true; }
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static const char* cpu_features() { return _features_str; }
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static intx allocate_prefetch_distance() {
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// This method should be called before allocate_prefetch_style().
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//
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// Hardware prefetching (distance/size in bytes):
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// Pentium 3 - 64 / 32
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// Pentium 4 - 256 / 128
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// Athlon - 64 / 32 ????
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// Opteron - 128 / 64 only when 2 sequential cache lines accessed
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// Core - 128 / 64
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//
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// Software prefetching (distance in bytes / instruction with best score):
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// Pentium 3 - 128 / prefetchnta
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// Pentium 4 - 512 / prefetchnta
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// Athlon - 128 / prefetchnta
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// Opteron - 256 / prefetchnta
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// Core - 256 / prefetchnta
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// It will be used only when AllocatePrefetchStyle > 0
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intx count = AllocatePrefetchDistance;
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if (count < 0) { // default ?
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if (is_amd()) { // AMD
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if (supports_sse2())
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count = 256; // Opteron
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else
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count = 128; // Athlon
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} else { // Intel
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if (supports_sse2())
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if (cpu_family() == 6) {
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count = 256; // Pentium M, Core, Core2
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} else {
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count = 512; // Pentium 4
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}
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else
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count = 128; // Pentium 3 (and all other old CPUs)
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}
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}
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return count;
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}
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static intx allocate_prefetch_style() {
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assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
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// Return 0 if AllocatePrefetchDistance was not defined or
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// prefetch instruction is not supported.
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return (AllocatePrefetchDistance > 0 &&
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(supports_3dnow() || supports_sse())) ? AllocatePrefetchStyle : 0;
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}
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};
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