488 lines
18 KiB
C++
488 lines
18 KiB
C++
/*
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* Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#include "precompiled.hpp"
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#include "asm/macroAssembler.inline.hpp"
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#include "memory/resourceArea.hpp"
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#include "runtime/java.hpp"
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#include "runtime/os.hpp"
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#include "runtime/stubCodeGenerator.hpp"
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#include "vm_version_sparc.hpp"
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int VM_Version::_features = VM_Version::unknown_m;
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const char* VM_Version::_features_str = "";
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unsigned int VM_Version::_L2_data_cache_line_size = 0;
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void VM_Version::initialize() {
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_features = determine_features();
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PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
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PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
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PrefetchFieldsAhead = prefetch_fields_ahead();
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assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value");
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if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
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if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0;
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// Allocation prefetch settings
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intx cache_line_size = prefetch_data_size();
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if( cache_line_size > AllocatePrefetchStepSize )
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AllocatePrefetchStepSize = cache_line_size;
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assert(AllocatePrefetchLines > 0, "invalid value");
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if( AllocatePrefetchLines < 1 ) // set valid value in product VM
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AllocatePrefetchLines = 3;
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assert(AllocateInstancePrefetchLines > 0, "invalid value");
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if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
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AllocateInstancePrefetchLines = 1;
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AllocatePrefetchDistance = allocate_prefetch_distance();
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AllocatePrefetchStyle = allocate_prefetch_style();
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assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 &&
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(AllocatePrefetchDistance > 0), "invalid value");
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if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 ||
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(AllocatePrefetchDistance <= 0)) {
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AllocatePrefetchDistance = AllocatePrefetchStepSize;
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}
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if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
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warning("BIS instructions are not available on this CPU");
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FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
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}
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guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
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assert(ArraycopySrcPrefetchDistance < 4096, "invalid value");
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if (ArraycopySrcPrefetchDistance >= 4096)
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ArraycopySrcPrefetchDistance = 4064;
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assert(ArraycopyDstPrefetchDistance < 4096, "invalid value");
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if (ArraycopyDstPrefetchDistance >= 4096)
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ArraycopyDstPrefetchDistance = 4064;
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UseSSE = 0; // Only on x86 and x64
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_supports_cx8 = has_v9();
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_supports_atomic_getset4 = true; // swap instruction
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// There are Fujitsu Sparc64 CPUs which support blk_init as well so
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// we have to take this check out of the 'is_niagara()' block below.
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if (has_blk_init()) {
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// When using CMS or G1, we cannot use memset() in BOT updates
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// because the sun4v/CMT version in libc_psr uses BIS which
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// exposes "phantom zeros" to concurrent readers. See 6948537.
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if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) {
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FLAG_SET_DEFAULT(UseMemSetInBOT, false);
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}
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// Issue a stern warning if the user has explicitly set
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// UseMemSetInBOT (it is known to cause issues), but allow
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// use for experimentation and debugging.
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if (UseConcMarkSweepGC || UseG1GC) {
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if (UseMemSetInBOT) {
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assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error");
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warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability"
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" on sun4v; please understand that you are using at your own risk!");
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}
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}
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}
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if (is_niagara()) {
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// Indirect branch is the same cost as direct
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if (FLAG_IS_DEFAULT(UseInlineCaches)) {
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FLAG_SET_DEFAULT(UseInlineCaches, false);
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}
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// Align loops on a single instruction boundary.
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if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
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FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
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}
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#ifdef _LP64
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// 32-bit oops don't make sense for the 64-bit VM on sparc
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// since the 32-bit VM has the same registers and smaller objects.
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Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
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Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
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#endif // _LP64
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#ifdef COMPILER2
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// Indirect branch is the same cost as direct
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if (FLAG_IS_DEFAULT(UseJumpTables)) {
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FLAG_SET_DEFAULT(UseJumpTables, true);
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}
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// Single-issue, so entry and loop tops are
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// aligned on a single instruction boundary
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if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
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FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
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}
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if (is_niagara_plus()) {
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if (has_blk_init() && UseTLAB &&
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FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
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// Use BIS instruction for TLAB allocation prefetch.
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FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
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if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
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FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
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}
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if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
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// Use smaller prefetch distance with BIS
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FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
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}
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}
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if (is_T4()) {
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// Double number of prefetched cache lines on T4
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// since L2 cache line size is smaller (32 bytes).
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if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
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FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
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}
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if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
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FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
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}
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}
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if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
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// Use different prefetch distance without BIS
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FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
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}
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if (AllocatePrefetchInstr == 1) {
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// Need a space at the end of TLAB for BIS since it
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// will fault when accessing memory outside of heap.
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// +1 for rounding up to next cache line, +1 to be safe
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int lines = AllocatePrefetchLines + 2;
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int step_size = AllocatePrefetchStepSize;
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int distance = AllocatePrefetchDistance;
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_reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
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}
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}
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#endif
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}
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// Use hardware population count instruction if available.
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if (has_hardware_popc()) {
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if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
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FLAG_SET_DEFAULT(UsePopCountInstruction, true);
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}
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} else if (UsePopCountInstruction) {
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warning("POPC instruction is not available on this CPU");
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FLAG_SET_DEFAULT(UsePopCountInstruction, false);
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}
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// T4 and newer Sparc cpus have new compare and branch instruction.
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if (has_cbcond()) {
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if (FLAG_IS_DEFAULT(UseCBCond)) {
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FLAG_SET_DEFAULT(UseCBCond, true);
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}
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} else if (UseCBCond) {
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warning("CBCOND instruction is not available on this CPU");
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FLAG_SET_DEFAULT(UseCBCond, false);
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}
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assert(BlockZeroingLowLimit > 0, "invalid value");
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if (has_block_zeroing() && cache_line_size > 0) {
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if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
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FLAG_SET_DEFAULT(UseBlockZeroing, true);
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}
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} else if (UseBlockZeroing) {
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warning("BIS zeroing instructions are not available on this CPU");
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FLAG_SET_DEFAULT(UseBlockZeroing, false);
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}
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assert(BlockCopyLowLimit > 0, "invalid value");
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if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
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if (FLAG_IS_DEFAULT(UseBlockCopy)) {
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FLAG_SET_DEFAULT(UseBlockCopy, true);
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}
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} else if (UseBlockCopy) {
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warning("BIS instructions are not available or expensive on this CPU");
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FLAG_SET_DEFAULT(UseBlockCopy, false);
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}
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#ifdef COMPILER2
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// T4 and newer Sparc cpus have fast RDPC.
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if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
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FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
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}
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// Currently not supported anywhere.
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FLAG_SET_DEFAULT(UseFPUForSpilling, false);
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MaxVectorSize = 8;
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assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
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#endif
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assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
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assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
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char buf[512];
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jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
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(has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
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(has_hardware_popc() ? ", popc" : ""),
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(has_vis1() ? ", vis1" : ""),
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(has_vis2() ? ", vis2" : ""),
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(has_vis3() ? ", vis3" : ""),
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(has_blk_init() ? ", blk_init" : ""),
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(has_cbcond() ? ", cbcond" : ""),
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(has_aes() ? ", aes" : ""),
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(has_sha1() ? ", sha1" : ""),
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(has_sha256() ? ", sha256" : ""),
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(has_sha512() ? ", sha512" : ""),
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(has_crc32c() ? ", crc32c" : ""),
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(is_ultra3() ? ", ultra3" : ""),
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(is_sun4v() ? ", sun4v" : ""),
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(is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
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(is_sparc64() ? ", sparc64" : ""),
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(!has_hardware_mul32() ? ", no-mul32" : ""),
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(!has_hardware_div32() ? ", no-div32" : ""),
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(!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
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// buf is started with ", " or is empty
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_features_str = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);
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// UseVIS is set to the smallest of what hardware supports and what
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// the command line requires. I.e., you cannot set UseVIS to 3 on
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// older UltraSparc which do not support it.
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if (UseVIS > 3) UseVIS=3;
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if (UseVIS < 0) UseVIS=0;
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if (!has_vis3()) // Drop to 2 if no VIS3 support
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UseVIS = MIN2((intx)2,UseVIS);
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if (!has_vis2()) // Drop to 1 if no VIS2 support
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UseVIS = MIN2((intx)1,UseVIS);
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if (!has_vis1()) // Drop to 0 if no VIS1 support
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UseVIS = 0;
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// SPARC T4 and above should have support for AES instructions
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if (has_aes()) {
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if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3
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if (FLAG_IS_DEFAULT(UseAES)) {
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FLAG_SET_DEFAULT(UseAES, true);
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}
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if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
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FLAG_SET_DEFAULT(UseAESIntrinsics, true);
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}
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// we disable both the AES flags if either of them is disabled on the command line
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if (!UseAES || !UseAESIntrinsics) {
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FLAG_SET_DEFAULT(UseAES, false);
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FLAG_SET_DEFAULT(UseAESIntrinsics, false);
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}
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} else {
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if (UseAES || UseAESIntrinsics) {
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warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
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if (UseAES) {
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FLAG_SET_DEFAULT(UseAES, false);
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}
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if (UseAESIntrinsics) {
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FLAG_SET_DEFAULT(UseAESIntrinsics, false);
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}
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}
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}
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} else if (UseAES || UseAESIntrinsics) {
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warning("AES instructions are not available on this CPU");
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if (UseAES) {
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FLAG_SET_DEFAULT(UseAES, false);
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}
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if (UseAESIntrinsics) {
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FLAG_SET_DEFAULT(UseAESIntrinsics, false);
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}
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}
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// GHASH/GCM intrinsics
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if (has_vis3() && (UseVIS > 2)) {
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if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
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UseGHASHIntrinsics = true;
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}
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} else if (UseGHASHIntrinsics) {
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if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
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warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
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FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
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}
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// SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
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if (has_sha1() || has_sha256() || has_sha512()) {
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if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
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if (FLAG_IS_DEFAULT(UseSHA)) {
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FLAG_SET_DEFAULT(UseSHA, true);
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}
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} else {
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if (UseSHA) {
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warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
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FLAG_SET_DEFAULT(UseSHA, false);
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}
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}
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} else if (UseSHA) {
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warning("SHA instructions are not available on this CPU");
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FLAG_SET_DEFAULT(UseSHA, false);
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}
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if (UseSHA && has_sha1()) {
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if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
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FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
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}
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} else if (UseSHA1Intrinsics) {
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warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
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FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
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}
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if (UseSHA && has_sha256()) {
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if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
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FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
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}
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} else if (UseSHA256Intrinsics) {
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warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
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FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
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}
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if (UseSHA && has_sha512()) {
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if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
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FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
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}
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} else if (UseSHA512Intrinsics) {
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warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
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FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
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}
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if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
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FLAG_SET_DEFAULT(UseSHA, false);
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}
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// SPARC T4 and above should have support for CRC32C instruction
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if (has_crc32c()) {
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if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
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if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
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FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
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}
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} else {
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if (UseCRC32CIntrinsics) {
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warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
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FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
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}
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}
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} else if (UseCRC32CIntrinsics) {
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warning("CRC32C instruction is not available on this CPU");
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FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
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}
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if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
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(cache_line_size > ContendedPaddingWidth))
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ContendedPaddingWidth = cache_line_size;
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// This machine does not allow unaligned memory accesses
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if (UseUnalignedAccesses) {
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if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
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warning("Unaligned memory access is not available on this CPU");
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FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
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}
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#ifndef PRODUCT
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if (PrintMiscellaneous && Verbose) {
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tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
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tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
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tty->print("Allocation");
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if (AllocatePrefetchStyle <= 0) {
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tty->print_cr(": no prefetching");
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} else {
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tty->print(" prefetching: ");
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if (AllocatePrefetchInstr == 0) {
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tty->print("PREFETCH");
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} else if (AllocatePrefetchInstr == 1) {
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tty->print("BIS");
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}
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if (AllocatePrefetchLines > 1) {
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tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
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} else {
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tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
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}
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}
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if (PrefetchCopyIntervalInBytes > 0) {
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tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
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}
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if (PrefetchScanIntervalInBytes > 0) {
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tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
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}
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if (PrefetchFieldsAhead > 0) {
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tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
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}
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if (ContendedPaddingWidth > 0) {
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tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
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}
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}
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#endif // PRODUCT
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}
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void VM_Version::print_features() {
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tty->print_cr("Version:%s", cpu_features());
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}
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int VM_Version::determine_features() {
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if (UseV8InstrsOnly) {
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NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");)
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return generic_v8_m;
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}
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int features = platform_features(unknown_m); // platform_features() is os_arch specific
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if (features == unknown_m) {
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features = generic_v9_m;
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warning("Cannot recognize SPARC version. Default to V9");
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}
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assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
|
|
if (UseNiagaraInstrs) { // Force code generation for Niagara
|
|
if (is_T_family(features)) {
|
|
// Happy to accomodate...
|
|
} else {
|
|
NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");)
|
|
features |= T_family_m;
|
|
}
|
|
} else {
|
|
if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
|
|
NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");)
|
|
features &= ~(T_family_m | T1_model_m);
|
|
} else {
|
|
// Happy to accomodate...
|
|
}
|
|
}
|
|
|
|
return features;
|
|
}
|
|
|
|
static int saved_features = 0;
|
|
|
|
void VM_Version::allow_all() {
|
|
saved_features = _features;
|
|
_features = all_features_m;
|
|
}
|
|
|
|
void VM_Version::revert() {
|
|
_features = saved_features;
|
|
}
|
|
|
|
unsigned int VM_Version::calc_parallel_worker_threads() {
|
|
unsigned int result;
|
|
if (is_M_series()) {
|
|
// for now, use same gc thread calculation for M-series as for niagara-plus
|
|
// in future, we may want to tweak parameters for nof_parallel_worker_thread
|
|
result = nof_parallel_worker_threads(5, 16, 8);
|
|
} else if (is_niagara_plus()) {
|
|
result = nof_parallel_worker_threads(5, 16, 8);
|
|
} else {
|
|
result = nof_parallel_worker_threads(5, 8, 8);
|
|
}
|
|
return result;
|
|
}
|