8006fe8f75
Replaced MakeDeps and the includeDB files with more standardized solutions. Reviewed-by: coleenp, kvn, kamg
372 lines
11 KiB
C++
372 lines
11 KiB
C++
/*
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* Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#include "precompiled.hpp"
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#include "c1/c1_FrameMap.hpp"
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#include "c1/c1_LIR.hpp"
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#include "runtime/sharedRuntime.hpp"
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#include "vmreg_sparc.inline.hpp"
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const int FrameMap::pd_c_runtime_reserved_arg_size = 7;
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LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool outgoing) {
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LIR_Opr opr = LIR_OprFact::illegalOpr;
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VMReg r_1 = reg->first();
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VMReg r_2 = reg->second();
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if (r_1->is_stack()) {
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// Convert stack slot to an SP offset
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// The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value
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// so we must add it in here.
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int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
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opr = LIR_OprFact::address(new LIR_Address(SP_opr, st_off + STACK_BIAS, type));
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} else if (r_1->is_Register()) {
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Register reg = r_1->as_Register();
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if (outgoing) {
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assert(!reg->is_in(), "should be using I regs");
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} else {
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assert(!reg->is_out(), "should be using O regs");
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}
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if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
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opr = as_long_opr(reg);
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} else if (type == T_OBJECT || type == T_ARRAY) {
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opr = as_oop_opr(reg);
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} else {
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opr = as_opr(reg);
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}
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} else if (r_1->is_FloatRegister()) {
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assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
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FloatRegister f = r_1->as_FloatRegister();
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if (type == T_DOUBLE) {
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opr = as_double_opr(f);
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} else {
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opr = as_float_opr(f);
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}
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}
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return opr;
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}
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// FrameMap
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//--------------------------------------------------------
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FloatRegister FrameMap::_fpu_regs [FrameMap::nof_fpu_regs];
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// some useful constant RInfo's:
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LIR_Opr FrameMap::in_long_opr;
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LIR_Opr FrameMap::out_long_opr;
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LIR_Opr FrameMap::g1_long_single_opr;
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LIR_Opr FrameMap::F0_opr;
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LIR_Opr FrameMap::F0_double_opr;
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LIR_Opr FrameMap::G0_opr;
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LIR_Opr FrameMap::G1_opr;
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LIR_Opr FrameMap::G2_opr;
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LIR_Opr FrameMap::G3_opr;
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LIR_Opr FrameMap::G4_opr;
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LIR_Opr FrameMap::G5_opr;
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LIR_Opr FrameMap::G6_opr;
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LIR_Opr FrameMap::G7_opr;
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LIR_Opr FrameMap::O0_opr;
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LIR_Opr FrameMap::O1_opr;
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LIR_Opr FrameMap::O2_opr;
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LIR_Opr FrameMap::O3_opr;
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LIR_Opr FrameMap::O4_opr;
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LIR_Opr FrameMap::O5_opr;
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LIR_Opr FrameMap::O6_opr;
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LIR_Opr FrameMap::O7_opr;
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LIR_Opr FrameMap::L0_opr;
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LIR_Opr FrameMap::L1_opr;
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LIR_Opr FrameMap::L2_opr;
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LIR_Opr FrameMap::L3_opr;
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LIR_Opr FrameMap::L4_opr;
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LIR_Opr FrameMap::L5_opr;
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LIR_Opr FrameMap::L6_opr;
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LIR_Opr FrameMap::L7_opr;
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LIR_Opr FrameMap::I0_opr;
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LIR_Opr FrameMap::I1_opr;
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LIR_Opr FrameMap::I2_opr;
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LIR_Opr FrameMap::I3_opr;
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LIR_Opr FrameMap::I4_opr;
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LIR_Opr FrameMap::I5_opr;
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LIR_Opr FrameMap::I6_opr;
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LIR_Opr FrameMap::I7_opr;
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LIR_Opr FrameMap::G0_oop_opr;
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LIR_Opr FrameMap::G1_oop_opr;
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LIR_Opr FrameMap::G2_oop_opr;
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LIR_Opr FrameMap::G3_oop_opr;
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LIR_Opr FrameMap::G4_oop_opr;
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LIR_Opr FrameMap::G5_oop_opr;
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LIR_Opr FrameMap::G6_oop_opr;
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LIR_Opr FrameMap::G7_oop_opr;
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LIR_Opr FrameMap::O0_oop_opr;
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LIR_Opr FrameMap::O1_oop_opr;
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LIR_Opr FrameMap::O2_oop_opr;
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LIR_Opr FrameMap::O3_oop_opr;
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LIR_Opr FrameMap::O4_oop_opr;
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LIR_Opr FrameMap::O5_oop_opr;
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LIR_Opr FrameMap::O6_oop_opr;
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LIR_Opr FrameMap::O7_oop_opr;
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LIR_Opr FrameMap::L0_oop_opr;
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LIR_Opr FrameMap::L1_oop_opr;
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LIR_Opr FrameMap::L2_oop_opr;
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LIR_Opr FrameMap::L3_oop_opr;
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LIR_Opr FrameMap::L4_oop_opr;
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LIR_Opr FrameMap::L5_oop_opr;
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LIR_Opr FrameMap::L6_oop_opr;
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LIR_Opr FrameMap::L7_oop_opr;
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LIR_Opr FrameMap::I0_oop_opr;
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LIR_Opr FrameMap::I1_oop_opr;
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LIR_Opr FrameMap::I2_oop_opr;
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LIR_Opr FrameMap::I3_oop_opr;
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LIR_Opr FrameMap::I4_oop_opr;
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LIR_Opr FrameMap::I5_oop_opr;
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LIR_Opr FrameMap::I6_oop_opr;
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LIR_Opr FrameMap::I7_oop_opr;
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LIR_Opr FrameMap::SP_opr;
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LIR_Opr FrameMap::FP_opr;
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LIR_Opr FrameMap::Oexception_opr;
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LIR_Opr FrameMap::Oissuing_pc_opr;
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LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
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LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
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FloatRegister FrameMap::nr2floatreg (int rnr) {
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assert(_init_done, "tables not initialized");
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debug_only(fpu_range_check(rnr);)
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return _fpu_regs[rnr];
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}
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// returns true if reg could be smashed by a callee.
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bool FrameMap::is_caller_save_register (LIR_Opr reg) {
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if (reg->is_single_fpu() || reg->is_double_fpu()) { return true; }
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if (reg->is_double_cpu()) {
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return is_caller_save_register(reg->as_register_lo()) ||
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is_caller_save_register(reg->as_register_hi());
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}
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return is_caller_save_register(reg->as_register());
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}
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NEEDS_CLEANUP // once the new calling convention is enabled, we no
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// longer need to treat I5, I4 and L0 specially
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// Because the interpreter destroys caller's I5, I4 and L0,
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// we must spill them before doing a Java call as we may land in
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// interpreter.
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bool FrameMap::is_caller_save_register (Register r) {
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return (r->is_global() && (r != G0)) || r->is_out();
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}
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void FrameMap::initialize() {
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assert(!_init_done, "once");
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int i=0;
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// Register usage:
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// O6: sp
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// I6: fp
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// I7: return address
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// G0: zero
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// G2: thread
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// G7: not available
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// G6: not available
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/* 0 */ map_register(i++, L0);
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/* 1 */ map_register(i++, L1);
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/* 2 */ map_register(i++, L2);
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/* 3 */ map_register(i++, L3);
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/* 4 */ map_register(i++, L4);
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/* 5 */ map_register(i++, L5);
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/* 6 */ map_register(i++, L6);
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/* 7 */ map_register(i++, L7);
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/* 8 */ map_register(i++, I0);
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/* 9 */ map_register(i++, I1);
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/* 10 */ map_register(i++, I2);
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/* 11 */ map_register(i++, I3);
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/* 12 */ map_register(i++, I4);
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/* 13 */ map_register(i++, I5);
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/* 14 */ map_register(i++, O0);
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/* 15 */ map_register(i++, O1);
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/* 16 */ map_register(i++, O2);
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/* 17 */ map_register(i++, O3);
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/* 18 */ map_register(i++, O4);
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/* 19 */ map_register(i++, O5); // <- last register visible in RegAlloc (RegAlloc::nof+cpu_regs)
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/* 20 */ map_register(i++, G1);
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/* 21 */ map_register(i++, G3);
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/* 22 */ map_register(i++, G4);
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/* 23 */ map_register(i++, G5);
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/* 24 */ map_register(i++, G0);
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// the following registers are not normally available
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/* 25 */ map_register(i++, O7);
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/* 26 */ map_register(i++, G2);
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/* 27 */ map_register(i++, O6);
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/* 28 */ map_register(i++, I6);
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/* 29 */ map_register(i++, I7);
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/* 30 */ map_register(i++, G6);
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/* 31 */ map_register(i++, G7);
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assert(i == nof_cpu_regs, "number of CPU registers");
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for (i = 0; i < nof_fpu_regs; i++) {
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_fpu_regs[i] = as_FloatRegister(i);
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}
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_init_done = true;
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in_long_opr = as_long_opr(I0);
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out_long_opr = as_long_opr(O0);
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g1_long_single_opr = as_long_single_opr(G1);
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G0_opr = as_opr(G0);
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G1_opr = as_opr(G1);
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G2_opr = as_opr(G2);
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G3_opr = as_opr(G3);
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G4_opr = as_opr(G4);
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G5_opr = as_opr(G5);
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G6_opr = as_opr(G6);
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G7_opr = as_opr(G7);
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O0_opr = as_opr(O0);
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O1_opr = as_opr(O1);
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O2_opr = as_opr(O2);
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O3_opr = as_opr(O3);
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O4_opr = as_opr(O4);
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O5_opr = as_opr(O5);
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O6_opr = as_opr(O6);
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O7_opr = as_opr(O7);
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L0_opr = as_opr(L0);
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L1_opr = as_opr(L1);
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L2_opr = as_opr(L2);
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L3_opr = as_opr(L3);
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L4_opr = as_opr(L4);
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L5_opr = as_opr(L5);
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L6_opr = as_opr(L6);
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L7_opr = as_opr(L7);
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I0_opr = as_opr(I0);
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I1_opr = as_opr(I1);
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I2_opr = as_opr(I2);
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I3_opr = as_opr(I3);
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I4_opr = as_opr(I4);
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I5_opr = as_opr(I5);
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I6_opr = as_opr(I6);
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I7_opr = as_opr(I7);
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G0_oop_opr = as_oop_opr(G0);
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G1_oop_opr = as_oop_opr(G1);
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G2_oop_opr = as_oop_opr(G2);
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G3_oop_opr = as_oop_opr(G3);
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G4_oop_opr = as_oop_opr(G4);
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G5_oop_opr = as_oop_opr(G5);
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G6_oop_opr = as_oop_opr(G6);
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G7_oop_opr = as_oop_opr(G7);
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O0_oop_opr = as_oop_opr(O0);
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O1_oop_opr = as_oop_opr(O1);
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O2_oop_opr = as_oop_opr(O2);
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O3_oop_opr = as_oop_opr(O3);
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O4_oop_opr = as_oop_opr(O4);
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O5_oop_opr = as_oop_opr(O5);
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O6_oop_opr = as_oop_opr(O6);
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O7_oop_opr = as_oop_opr(O7);
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L0_oop_opr = as_oop_opr(L0);
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L1_oop_opr = as_oop_opr(L1);
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L2_oop_opr = as_oop_opr(L2);
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L3_oop_opr = as_oop_opr(L3);
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L4_oop_opr = as_oop_opr(L4);
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L5_oop_opr = as_oop_opr(L5);
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L6_oop_opr = as_oop_opr(L6);
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L7_oop_opr = as_oop_opr(L7);
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I0_oop_opr = as_oop_opr(I0);
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I1_oop_opr = as_oop_opr(I1);
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I2_oop_opr = as_oop_opr(I2);
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I3_oop_opr = as_oop_opr(I3);
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I4_oop_opr = as_oop_opr(I4);
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I5_oop_opr = as_oop_opr(I5);
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I6_oop_opr = as_oop_opr(I6);
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I7_oop_opr = as_oop_opr(I7);
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FP_opr = as_pointer_opr(FP);
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SP_opr = as_pointer_opr(SP);
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F0_opr = as_float_opr(F0);
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F0_double_opr = as_double_opr(F0);
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Oexception_opr = as_oop_opr(Oexception);
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Oissuing_pc_opr = as_opr(Oissuing_pc);
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_caller_save_cpu_regs[0] = FrameMap::O0_opr;
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_caller_save_cpu_regs[1] = FrameMap::O1_opr;
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_caller_save_cpu_regs[2] = FrameMap::O2_opr;
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_caller_save_cpu_regs[3] = FrameMap::O3_opr;
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_caller_save_cpu_regs[4] = FrameMap::O4_opr;
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_caller_save_cpu_regs[5] = FrameMap::O5_opr;
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_caller_save_cpu_regs[6] = FrameMap::G1_opr;
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_caller_save_cpu_regs[7] = FrameMap::G3_opr;
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_caller_save_cpu_regs[8] = FrameMap::G4_opr;
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_caller_save_cpu_regs[9] = FrameMap::G5_opr;
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for (int i = 0; i < nof_caller_save_fpu_regs; i++) {
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_caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
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}
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}
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Address FrameMap::make_new_address(ByteSize sp_offset) const {
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return Address(SP, STACK_BIAS + in_bytes(sp_offset));
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}
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VMReg FrameMap::fpu_regname (int n) {
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return as_FloatRegister(n)->as_VMReg();
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}
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LIR_Opr FrameMap::stack_pointer() {
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return SP_opr;
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}
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// JSR 292
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LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() {
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assert(L7 == L7_mh_SP_save, "must be same register");
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return L7_opr;
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}
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bool FrameMap::validate_frame() {
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int max_offset = in_bytes(framesize_in_bytes());
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int java_index = 0;
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for (int i = 0; i < _incoming_arguments->length(); i++) {
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LIR_Opr opr = _incoming_arguments->at(i);
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if (opr->is_stack()) {
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max_offset = MAX2(_argument_locations->at(java_index), max_offset);
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}
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java_index += type2size[opr->type()];
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}
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return Assembler::is_simm13(max_offset + STACK_BIAS);
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}
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