928 lines
33 KiB
C++
928 lines
33 KiB
C++
/*
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* Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#ifndef CPU_SPARC_VM_NATIVEINST_SPARC_HPP
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#define CPU_SPARC_VM_NATIVEINST_SPARC_HPP
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#include "asm/assembler.hpp"
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#include "memory/allocation.hpp"
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#include "runtime/icache.hpp"
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#include "runtime/os.hpp"
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#include "utilities/top.hpp"
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// We have interface for the following instructions:
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// - NativeInstruction
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// - - NativeCall
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// - - NativeFarCall
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// - - NativeMovConstReg
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// - - NativeMovConstRegPatching
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// - - NativeMovRegMem
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// - - NativeMovRegMemPatching
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// - - NativeJump
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// - - NativeGeneralJump
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// - - NativeIllegalInstruction
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// The base class for different kinds of native instruction abstractions.
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// Provides the primitive operations to manipulate code relative to this.
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class NativeInstruction VALUE_OBJ_CLASS_SPEC {
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friend class Relocation;
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public:
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enum Sparc_specific_constants {
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nop_instruction_size = 4
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};
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bool is_dtrace_trap();
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bool is_nop() { return long_at(0) == nop_instruction(); }
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bool is_call() { return is_op(long_at(0), Assembler::call_op); }
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bool is_sethi() { return (is_op2(long_at(0), Assembler::sethi_op2)
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&& inv_rd(long_at(0)) != G0); }
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bool sets_cc() {
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// conservative (returns true for some instructions that do not set the
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// the condition code, such as, "save".
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// Does not return true for the deprecated tagged instructions, such as, TADDcc
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int x = long_at(0);
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return (is_op(x, Assembler::arith_op) &&
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(inv_op3(x) & Assembler::cc_bit_op3) == Assembler::cc_bit_op3);
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}
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bool is_illegal();
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bool is_zombie() {
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int x = long_at(0);
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return is_op3(x,
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VM_Version::v9_instructions_work() ?
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Assembler::ldsw_op3 : Assembler::lduw_op3,
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Assembler::ldst_op)
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&& Assembler::inv_rs1(x) == G0
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&& Assembler::inv_rd(x) == O7;
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}
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bool is_ic_miss_trap(); // Inline-cache uses a trap to detect a miss
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bool is_return() {
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// is it the output of MacroAssembler::ret or MacroAssembler::retl?
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int x = long_at(0);
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const int pc_return_offset = 8; // see frame_sparc.hpp
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return is_op3(x, Assembler::jmpl_op3, Assembler::arith_op)
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&& (inv_rs1(x) == I7 || inv_rs1(x) == O7)
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&& inv_immed(x) && inv_simm(x, 13) == pc_return_offset
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&& inv_rd(x) == G0;
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}
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bool is_int_jump() {
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// is it the output of MacroAssembler::b?
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int x = long_at(0);
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return is_op2(x, Assembler::bp_op2) || is_op2(x, Assembler::br_op2);
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}
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bool is_float_jump() {
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// is it the output of MacroAssembler::fb?
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int x = long_at(0);
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return is_op2(x, Assembler::fbp_op2) || is_op2(x, Assembler::fb_op2);
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}
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bool is_jump() {
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return is_int_jump() || is_float_jump();
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}
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bool is_cond_jump() {
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int x = long_at(0);
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return (is_int_jump() && Assembler::inv_cond(x) != Assembler::always) ||
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(is_float_jump() && Assembler::inv_cond(x) != Assembler::f_always);
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}
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bool is_stack_bang() {
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int x = long_at(0);
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return is_op3(x, Assembler::stw_op3, Assembler::ldst_op) &&
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(inv_rd(x) == G0) && (inv_rs1(x) == SP) && (inv_rs2(x) == G3_scratch);
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}
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bool is_prefetch() {
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int x = long_at(0);
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return is_op3(x, Assembler::prefetch_op3, Assembler::ldst_op);
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}
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bool is_membar() {
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int x = long_at(0);
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return is_op3(x, Assembler::membar_op3, Assembler::arith_op) &&
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(inv_rd(x) == G0) && (inv_rs1(x) == O7);
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}
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bool is_safepoint_poll() {
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int x = long_at(0);
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#ifdef _LP64
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return is_op3(x, Assembler::ldx_op3, Assembler::ldst_op) &&
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#else
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return is_op3(x, Assembler::lduw_op3, Assembler::ldst_op) &&
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#endif
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(inv_rd(x) == G0) && (inv_immed(x) ? Assembler::inv_simm13(x) == 0 : inv_rs2(x) == G0);
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}
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bool is_zero_test(Register ®);
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bool is_load_store_with_small_offset(Register reg);
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public:
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#ifdef ASSERT
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static int rdpc_instruction() { return Assembler::op(Assembler::arith_op ) | Assembler::op3(Assembler::rdreg_op3) | Assembler::u_field(5, 18, 14) | Assembler::rd(O7); }
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#else
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// Temporary fix: in optimized mode, u_field is a macro for efficiency reasons (see Assembler::u_field) - needs to be fixed
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static int rdpc_instruction() { return Assembler::op(Assembler::arith_op ) | Assembler::op3(Assembler::rdreg_op3) | u_field(5, 18, 14) | Assembler::rd(O7); }
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#endif
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static int nop_instruction() { return Assembler::op(Assembler::branch_op) | Assembler::op2(Assembler::sethi_op2); }
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static int illegal_instruction(); // the output of __ breakpoint_trap()
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static int call_instruction(address destination, address pc) { return Assembler::op(Assembler::call_op) | Assembler::wdisp((intptr_t)destination, (intptr_t)pc, 30); }
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static int branch_instruction(Assembler::op2s op2val, Assembler::Condition c, bool a) {
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return Assembler::op(Assembler::branch_op) | Assembler::op2(op2val) | Assembler::annul(a) | Assembler::cond(c);
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}
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static int op3_instruction(Assembler::ops opval, Register rd, Assembler::op3s op3val, Register rs1, int simm13a) {
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return Assembler::op(opval) | Assembler::rd(rd) | Assembler::op3(op3val) | Assembler::rs1(rs1) | Assembler::immed(true) | Assembler::simm(simm13a, 13);
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}
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static int sethi_instruction(Register rd, int imm22a) {
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return Assembler::op(Assembler::branch_op) | Assembler::rd(rd) | Assembler::op2(Assembler::sethi_op2) | Assembler::hi22(imm22a);
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}
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protected:
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address addr_at(int offset) const { return address(this) + offset; }
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int long_at(int offset) const { return *(int*)addr_at(offset); }
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void set_long_at(int offset, int i); /* deals with I-cache */
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void set_jlong_at(int offset, jlong i); /* deals with I-cache */
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void set_addr_at(int offset, address x); /* deals with I-cache */
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address instruction_address() const { return addr_at(0); }
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address next_instruction_address() const { return addr_at(BytesPerInstWord); }
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static bool is_op( int x, Assembler::ops opval) {
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return Assembler::inv_op(x) == opval;
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}
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static bool is_op2(int x, Assembler::op2s op2val) {
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return Assembler::inv_op(x) == Assembler::branch_op && Assembler::inv_op2(x) == op2val;
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}
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static bool is_op3(int x, Assembler::op3s op3val, Assembler::ops opval) {
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return Assembler::inv_op(x) == opval && Assembler::inv_op3(x) == op3val;
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}
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// utilities to help subclasses decode:
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static Register inv_rd( int x ) { return Assembler::inv_rd( x); }
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static Register inv_rs1( int x ) { return Assembler::inv_rs1(x); }
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static Register inv_rs2( int x ) { return Assembler::inv_rs2(x); }
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static bool inv_immed( int x ) { return Assembler::inv_immed(x); }
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static bool inv_annul( int x ) { return (Assembler::annul(true) & x) != 0; }
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static int inv_cond( int x ) { return Assembler::inv_cond(x); }
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static int inv_op( int x ) { return Assembler::inv_op( x); }
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static int inv_op2( int x ) { return Assembler::inv_op2(x); }
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static int inv_op3( int x ) { return Assembler::inv_op3(x); }
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static int inv_simm( int x, int nbits ) { return Assembler::inv_simm(x, nbits); }
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static intptr_t inv_wdisp( int x, int nbits ) { return Assembler::inv_wdisp( x, 0, nbits); }
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static intptr_t inv_wdisp16( int x ) { return Assembler::inv_wdisp16(x, 0); }
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static int branch_destination_offset(int x) { return Assembler::branch_destination(x, 0); }
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static int patch_branch_destination_offset(int dest_offset, int x) {
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return Assembler::patched_branch(dest_offset, x, 0);
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}
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void set_annul_bit() { set_long_at(0, long_at(0) | Assembler::annul(true)); }
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// utility for checking if x is either of 2 small constants
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static bool is_either(int x, int k1, int k2) {
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// return x == k1 || x == k2;
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return (1 << x) & (1 << k1 | 1 << k2);
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}
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// utility for checking overflow of signed instruction fields
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static bool fits_in_simm(int x, int nbits) {
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// cf. Assembler::assert_signed_range()
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// return -(1 << nbits-1) <= x && x < ( 1 << nbits-1),
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return (unsigned)(x + (1 << nbits-1)) < (unsigned)(1 << nbits);
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}
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// set a signed immediate field
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static int set_simm(int insn, int imm, int nbits) {
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return (insn &~ Assembler::simm(-1, nbits)) | Assembler::simm(imm, nbits);
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}
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// set a wdisp field (disp should be the difference of two addresses)
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static int set_wdisp(int insn, intptr_t disp, int nbits) {
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return (insn &~ Assembler::wdisp((intptr_t)-4, (intptr_t)0, nbits)) | Assembler::wdisp(disp, 0, nbits);
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}
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static int set_wdisp16(int insn, intptr_t disp) {
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return (insn &~ Assembler::wdisp16((intptr_t)-4, 0)) | Assembler::wdisp16(disp, 0);
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}
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// get a simm13 field from an arithmetic or memory instruction
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static int get_simm13(int insn) {
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assert(is_either(Assembler::inv_op(insn),
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Assembler::arith_op, Assembler::ldst_op) &&
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(insn & Assembler::immed(true)), "must have a simm13 field");
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return Assembler::inv_simm(insn, 13);
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}
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// set the simm13 field of an arithmetic or memory instruction
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static bool set_simm13(int insn, int imm) {
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get_simm13(insn); // tickle the assertion check
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return set_simm(insn, imm, 13);
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}
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// combine the fields of a sethi stream (7 instructions ) and an add, jmp or ld/st
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static intptr_t data64( address pc, int arith_insn ) {
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assert(is_op2(*(unsigned int *)pc, Assembler::sethi_op2), "must be sethi");
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intptr_t hi = (intptr_t)gethi( (unsigned int *)pc );
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intptr_t lo = (intptr_t)get_simm13(arith_insn);
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assert((unsigned)lo < (1 << 10), "offset field of set_oop must be 10 bits");
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return hi | lo;
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}
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// Regenerate the instruction sequence that performs the 64 bit
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// sethi. This only does the sethi. The disp field (bottom 10 bits)
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// must be handled separately.
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static void set_data64_sethi(address instaddr, intptr_t x);
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static void verify_data64_sethi(address instaddr, intptr_t x);
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// combine the fields of a sethi/simm13 pair (simm13 = or, add, jmpl, ld/st)
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static int data32(int sethi_insn, int arith_insn) {
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assert(is_op2(sethi_insn, Assembler::sethi_op2), "must be sethi");
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int hi = Assembler::inv_hi22(sethi_insn);
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int lo = get_simm13(arith_insn);
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assert((unsigned)lo < (1 << 10), "offset field of set_oop must be 10 bits");
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return hi | lo;
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}
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static int set_data32_sethi(int sethi_insn, int imm) {
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// note that Assembler::hi22 clips the low 10 bits for us
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assert(is_op2(sethi_insn, Assembler::sethi_op2), "must be sethi");
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return (sethi_insn &~ Assembler::hi22(-1)) | Assembler::hi22(imm);
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}
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static int set_data32_simm13(int arith_insn, int imm) {
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get_simm13(arith_insn); // tickle the assertion check
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int imm10 = Assembler::low10(imm);
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return (arith_insn &~ Assembler::simm(-1, 13)) | Assembler::simm(imm10, 13);
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}
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static int low10(int imm) {
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return Assembler::low10(imm);
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}
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// Perform the inverse of the LP64 Macroassembler::sethi
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// routine. Extracts the 54 bits of address from the instruction
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// stream. This routine must agree with the sethi routine in
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// assembler_inline_sparc.hpp
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static address gethi( unsigned int *pc ) {
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int i = 0;
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uintptr_t adr;
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// We first start out with the real sethi instruction
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assert(is_op2(*pc, Assembler::sethi_op2), "in gethi - must be sethi");
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adr = (unsigned int)Assembler::inv_hi22( *(pc++) );
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i++;
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while ( i < 7 ) {
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// We're done if we hit a nop
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if ( (int)*pc == nop_instruction() ) break;
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assert ( Assembler::inv_op(*pc) == Assembler::arith_op, "in gethi - must be arith_op" );
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switch ( Assembler::inv_op3(*pc) ) {
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case Assembler::xor_op3:
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adr ^= (intptr_t)get_simm13( *pc );
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return ( (address)adr );
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break;
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case Assembler::sll_op3:
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adr <<= ( *pc & 0x3f );
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break;
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case Assembler::or_op3:
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adr |= (intptr_t)get_simm13( *pc );
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break;
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default:
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assert ( 0, "in gethi - Should not reach here" );
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break;
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}
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pc++;
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i++;
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}
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return ( (address)adr );
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}
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public:
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void verify();
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void print();
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// unit test stuff
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static void test() {} // override for testing
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inline friend NativeInstruction* nativeInstruction_at(address address);
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};
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inline NativeInstruction* nativeInstruction_at(address address) {
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NativeInstruction* inst = (NativeInstruction*)address;
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#ifdef ASSERT
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inst->verify();
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#endif
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return inst;
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}
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//-----------------------------------------------------------------------------
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// The NativeCall is an abstraction for accessing/manipulating native call imm32 instructions.
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// (used to manipulate inline caches, primitive & dll calls, etc.)
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inline NativeCall* nativeCall_at(address instr);
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inline NativeCall* nativeCall_overwriting_at(address instr,
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address destination);
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inline NativeCall* nativeCall_before(address return_address);
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class NativeCall: public NativeInstruction {
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public:
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enum Sparc_specific_constants {
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instruction_size = 8,
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return_address_offset = 8,
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call_displacement_width = 30,
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displacement_offset = 0,
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instruction_offset = 0
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};
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address instruction_address() const { return addr_at(0); }
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address next_instruction_address() const { return addr_at(instruction_size); }
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address return_address() const { return addr_at(return_address_offset); }
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address destination() const { return inv_wdisp(long_at(0), call_displacement_width) + instruction_address(); }
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address displacement_address() const { return addr_at(displacement_offset); }
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void set_destination(address dest) { set_long_at(0, set_wdisp(long_at(0), dest - instruction_address(), call_displacement_width)); }
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void set_destination_mt_safe(address dest);
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void verify_alignment() {} // do nothing on sparc
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void verify();
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void print();
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// unit test stuff
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static void test();
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// Creation
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friend inline NativeCall* nativeCall_at(address instr);
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friend NativeCall* nativeCall_overwriting_at(address instr, address destination = NULL) {
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// insert a "blank" call:
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NativeCall* call = (NativeCall*)instr;
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call->set_long_at(0 * BytesPerInstWord, call_instruction(destination, instr));
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call->set_long_at(1 * BytesPerInstWord, nop_instruction());
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assert(call->addr_at(2 * BytesPerInstWord) - instr == instruction_size, "instruction size");
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// check its structure now:
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assert(nativeCall_at(instr)->destination() == destination, "correct call destination");
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return call;
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}
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friend inline NativeCall* nativeCall_before(address return_address) {
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NativeCall* call = (NativeCall*)(return_address - return_address_offset);
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#ifdef ASSERT
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call->verify();
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#endif
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return call;
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}
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static bool is_call_at(address instr) {
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return nativeInstruction_at(instr)->is_call();
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}
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static bool is_call_before(address instr) {
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return nativeInstruction_at(instr - return_address_offset)->is_call();
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}
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static bool is_call_to(address instr, address target) {
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return nativeInstruction_at(instr)->is_call() &&
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nativeCall_at(instr)->destination() == target;
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}
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// MT-safe patching of a call instruction.
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static void insert(address code_pos, address entry) {
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(void)nativeCall_overwriting_at(code_pos, entry);
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}
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|
static void replace_mt_safe(address instr_addr, address code_buffer);
|
|
};
|
|
inline NativeCall* nativeCall_at(address instr) {
|
|
NativeCall* call = (NativeCall*)instr;
|
|
#ifdef ASSERT
|
|
call->verify();
|
|
#endif
|
|
return call;
|
|
}
|
|
|
|
// The NativeFarCall is an abstraction for accessing/manipulating native call-anywhere
|
|
// instructions in the sparcv9 vm. Used to call native methods which may be loaded
|
|
// anywhere in the address space, possibly out of reach of a call instruction.
|
|
|
|
#ifndef _LP64
|
|
|
|
// On 32-bit systems, a far call is the same as a near one.
|
|
class NativeFarCall;
|
|
inline NativeFarCall* nativeFarCall_at(address instr);
|
|
class NativeFarCall : public NativeCall {
|
|
public:
|
|
friend inline NativeFarCall* nativeFarCall_at(address instr) { return (NativeFarCall*)nativeCall_at(instr); }
|
|
friend NativeFarCall* nativeFarCall_overwriting_at(address instr, address destination = NULL)
|
|
{ return (NativeFarCall*)nativeCall_overwriting_at(instr, destination); }
|
|
friend NativeFarCall* nativeFarCall_before(address return_address)
|
|
{ return (NativeFarCall*)nativeCall_before(return_address); }
|
|
};
|
|
|
|
#else
|
|
|
|
// The format of this extended-range call is:
|
|
// jumpl_to addr, lreg
|
|
// == sethi %hi54(addr), O7 ; jumpl O7, %lo10(addr), O7 ; <delay>
|
|
// That is, it is essentially the same as a NativeJump.
|
|
class NativeFarCall;
|
|
inline NativeFarCall* nativeFarCall_overwriting_at(address instr, address destination);
|
|
inline NativeFarCall* nativeFarCall_at(address instr);
|
|
class NativeFarCall: public NativeInstruction {
|
|
public:
|
|
enum Sparc_specific_constants {
|
|
// instruction_size includes the delay slot instruction.
|
|
instruction_size = 9 * BytesPerInstWord,
|
|
return_address_offset = 9 * BytesPerInstWord,
|
|
jmpl_offset = 7 * BytesPerInstWord,
|
|
displacement_offset = 0,
|
|
instruction_offset = 0
|
|
};
|
|
address instruction_address() const { return addr_at(0); }
|
|
address next_instruction_address() const { return addr_at(instruction_size); }
|
|
address return_address() const { return addr_at(return_address_offset); }
|
|
|
|
address destination() const {
|
|
return (address) data64(addr_at(0), long_at(jmpl_offset));
|
|
}
|
|
address displacement_address() const { return addr_at(displacement_offset); }
|
|
void set_destination(address dest);
|
|
|
|
bool destination_is_compiled_verified_entry_point();
|
|
|
|
void verify();
|
|
void print();
|
|
|
|
// unit test stuff
|
|
static void test();
|
|
|
|
// Creation
|
|
friend inline NativeFarCall* nativeFarCall_at(address instr) {
|
|
NativeFarCall* call = (NativeFarCall*)instr;
|
|
#ifdef ASSERT
|
|
call->verify();
|
|
#endif
|
|
return call;
|
|
}
|
|
|
|
friend inline NativeFarCall* nativeFarCall_overwriting_at(address instr, address destination = NULL) {
|
|
Unimplemented();
|
|
NativeFarCall* call = (NativeFarCall*)instr;
|
|
return call;
|
|
}
|
|
|
|
friend NativeFarCall* nativeFarCall_before(address return_address) {
|
|
NativeFarCall* call = (NativeFarCall*)(return_address - return_address_offset);
|
|
#ifdef ASSERT
|
|
call->verify();
|
|
#endif
|
|
return call;
|
|
}
|
|
|
|
static bool is_call_at(address instr);
|
|
|
|
// MT-safe patching of a call instruction.
|
|
static void insert(address code_pos, address entry) {
|
|
(void)nativeFarCall_overwriting_at(code_pos, entry);
|
|
}
|
|
static void replace_mt_safe(address instr_addr, address code_buffer);
|
|
};
|
|
|
|
#endif // _LP64
|
|
|
|
// An interface for accessing/manipulating native set_oop imm, reg instructions.
|
|
// (used to manipulate inlined data references, etc.)
|
|
// set_oop imm, reg
|
|
// == sethi %hi22(imm), reg ; add reg, %lo10(imm), reg
|
|
class NativeMovConstReg;
|
|
inline NativeMovConstReg* nativeMovConstReg_at(address address);
|
|
class NativeMovConstReg: public NativeInstruction {
|
|
public:
|
|
enum Sparc_specific_constants {
|
|
sethi_offset = 0,
|
|
#ifdef _LP64
|
|
add_offset = 7 * BytesPerInstWord,
|
|
instruction_size = 8 * BytesPerInstWord
|
|
#else
|
|
add_offset = 4,
|
|
instruction_size = 8
|
|
#endif
|
|
};
|
|
|
|
address instruction_address() const { return addr_at(0); }
|
|
address next_instruction_address() const { return addr_at(instruction_size); }
|
|
|
|
// (The [set_]data accessor respects oop_type relocs also.)
|
|
intptr_t data() const;
|
|
void set_data(intptr_t x);
|
|
|
|
// report the destination register
|
|
Register destination() { return inv_rd(long_at(sethi_offset)); }
|
|
|
|
void verify();
|
|
void print();
|
|
|
|
// unit test stuff
|
|
static void test();
|
|
|
|
// Creation
|
|
friend inline NativeMovConstReg* nativeMovConstReg_at(address address) {
|
|
NativeMovConstReg* test = (NativeMovConstReg*)address;
|
|
#ifdef ASSERT
|
|
test->verify();
|
|
#endif
|
|
return test;
|
|
}
|
|
|
|
|
|
friend NativeMovConstReg* nativeMovConstReg_before(address address) {
|
|
NativeMovConstReg* test = (NativeMovConstReg*)(address - instruction_size);
|
|
#ifdef ASSERT
|
|
test->verify();
|
|
#endif
|
|
return test;
|
|
}
|
|
|
|
};
|
|
|
|
|
|
// An interface for accessing/manipulating native set_oop imm, reg instructions.
|
|
// (used to manipulate inlined data references, etc.)
|
|
// set_oop imm, reg
|
|
// == sethi %hi22(imm), reg; nop; add reg, %lo10(imm), reg
|
|
//
|
|
// Note that it is identical to NativeMovConstReg with the exception of a nop between the
|
|
// sethi and the add. The nop is required to be in the delay slot of the call instruction
|
|
// which overwrites the sethi during patching.
|
|
class NativeMovConstRegPatching;
|
|
inline NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address);class NativeMovConstRegPatching: public NativeInstruction {
|
|
public:
|
|
enum Sparc_specific_constants {
|
|
sethi_offset = 0,
|
|
#ifdef _LP64
|
|
nop_offset = 7 * BytesPerInstWord,
|
|
#else
|
|
nop_offset = sethi_offset + BytesPerInstWord,
|
|
#endif
|
|
add_offset = nop_offset + BytesPerInstWord,
|
|
instruction_size = add_offset + BytesPerInstWord
|
|
};
|
|
|
|
address instruction_address() const { return addr_at(0); }
|
|
address next_instruction_address() const { return addr_at(instruction_size); }
|
|
|
|
// (The [set_]data accessor respects oop_type relocs also.)
|
|
int data() const;
|
|
void set_data(int x);
|
|
|
|
// report the destination register
|
|
Register destination() { return inv_rd(long_at(sethi_offset)); }
|
|
|
|
void verify();
|
|
void print();
|
|
|
|
// unit test stuff
|
|
static void test();
|
|
|
|
// Creation
|
|
friend inline NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) {
|
|
NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)address;
|
|
#ifdef ASSERT
|
|
test->verify();
|
|
#endif
|
|
return test;
|
|
}
|
|
|
|
|
|
friend NativeMovConstRegPatching* nativeMovConstRegPatching_before(address address) {
|
|
NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_size);
|
|
#ifdef ASSERT
|
|
test->verify();
|
|
#endif
|
|
return test;
|
|
}
|
|
|
|
};
|
|
|
|
|
|
// An interface for accessing/manipulating native memory ops
|
|
// ld* [reg + offset], reg
|
|
// st* reg, [reg + offset]
|
|
// sethi %hi(imm), reg; add reg, %lo(imm), reg; ld* [reg1 + reg], reg2
|
|
// sethi %hi(imm), reg; add reg, %lo(imm), reg; st* reg2, [reg1 + reg]
|
|
// Ops covered: {lds,ldu,st}{w,b,h}, {ld,st}{d,x}
|
|
//
|
|
class NativeMovRegMem;
|
|
inline NativeMovRegMem* nativeMovRegMem_at (address address);
|
|
class NativeMovRegMem: public NativeInstruction {
|
|
public:
|
|
enum Sparc_specific_constants {
|
|
op3_mask_ld = 1 << Assembler::lduw_op3 |
|
|
1 << Assembler::ldub_op3 |
|
|
1 << Assembler::lduh_op3 |
|
|
1 << Assembler::ldd_op3 |
|
|
1 << Assembler::ldsw_op3 |
|
|
1 << Assembler::ldsb_op3 |
|
|
1 << Assembler::ldsh_op3 |
|
|
1 << Assembler::ldx_op3,
|
|
op3_mask_st = 1 << Assembler::stw_op3 |
|
|
1 << Assembler::stb_op3 |
|
|
1 << Assembler::sth_op3 |
|
|
1 << Assembler::std_op3 |
|
|
1 << Assembler::stx_op3,
|
|
op3_ldst_int_limit = Assembler::ldf_op3,
|
|
op3_mask_ldf = 1 << (Assembler::ldf_op3 - op3_ldst_int_limit) |
|
|
1 << (Assembler::lddf_op3 - op3_ldst_int_limit),
|
|
op3_mask_stf = 1 << (Assembler::stf_op3 - op3_ldst_int_limit) |
|
|
1 << (Assembler::stdf_op3 - op3_ldst_int_limit),
|
|
|
|
offset_width = 13,
|
|
sethi_offset = 0,
|
|
#ifdef _LP64
|
|
add_offset = 7 * BytesPerInstWord,
|
|
#else
|
|
add_offset = 4,
|
|
#endif
|
|
ldst_offset = add_offset + BytesPerInstWord
|
|
};
|
|
bool is_immediate() const {
|
|
// check if instruction is ld* [reg + offset], reg or st* reg, [reg + offset]
|
|
int i0 = long_at(0);
|
|
return (is_op(i0, Assembler::ldst_op));
|
|
}
|
|
|
|
address instruction_address() const { return addr_at(0); }
|
|
address next_instruction_address() const {
|
|
#ifdef _LP64
|
|
return addr_at(is_immediate() ? 4 : (7 * BytesPerInstWord));
|
|
#else
|
|
return addr_at(is_immediate() ? 4 : 12);
|
|
#endif
|
|
}
|
|
intptr_t offset() const {
|
|
return is_immediate()? inv_simm(long_at(0), offset_width) :
|
|
nativeMovConstReg_at(addr_at(0))->data();
|
|
}
|
|
void set_offset(intptr_t x) {
|
|
if (is_immediate()) {
|
|
guarantee(fits_in_simm(x, offset_width), "data block offset overflow");
|
|
set_long_at(0, set_simm(long_at(0), x, offset_width));
|
|
} else
|
|
nativeMovConstReg_at(addr_at(0))->set_data(x);
|
|
}
|
|
|
|
void add_offset_in_bytes(intptr_t radd_offset) {
|
|
set_offset (offset() + radd_offset);
|
|
}
|
|
|
|
void copy_instruction_to(address new_instruction_address);
|
|
|
|
void verify();
|
|
void print ();
|
|
|
|
// unit test stuff
|
|
static void test();
|
|
|
|
private:
|
|
friend inline NativeMovRegMem* nativeMovRegMem_at (address address) {
|
|
NativeMovRegMem* test = (NativeMovRegMem*)address;
|
|
#ifdef ASSERT
|
|
test->verify();
|
|
#endif
|
|
return test;
|
|
}
|
|
};
|
|
|
|
|
|
// An interface for accessing/manipulating native memory ops
|
|
// ld* [reg + offset], reg
|
|
// st* reg, [reg + offset]
|
|
// sethi %hi(imm), reg; nop; add reg, %lo(imm), reg; ld* [reg1 + reg], reg2
|
|
// sethi %hi(imm), reg; nop; add reg, %lo(imm), reg; st* reg2, [reg1 + reg]
|
|
// Ops covered: {lds,ldu,st}{w,b,h}, {ld,st}{d,x}
|
|
//
|
|
// Note that it is identical to NativeMovRegMem with the exception of a nop between the
|
|
// sethi and the add. The nop is required to be in the delay slot of the call instruction
|
|
// which overwrites the sethi during patching.
|
|
class NativeMovRegMemPatching;
|
|
inline NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address);
|
|
class NativeMovRegMemPatching: public NativeInstruction {
|
|
public:
|
|
enum Sparc_specific_constants {
|
|
op3_mask_ld = 1 << Assembler::lduw_op3 |
|
|
1 << Assembler::ldub_op3 |
|
|
1 << Assembler::lduh_op3 |
|
|
1 << Assembler::ldd_op3 |
|
|
1 << Assembler::ldsw_op3 |
|
|
1 << Assembler::ldsb_op3 |
|
|
1 << Assembler::ldsh_op3 |
|
|
1 << Assembler::ldx_op3,
|
|
op3_mask_st = 1 << Assembler::stw_op3 |
|
|
1 << Assembler::stb_op3 |
|
|
1 << Assembler::sth_op3 |
|
|
1 << Assembler::std_op3 |
|
|
1 << Assembler::stx_op3,
|
|
op3_ldst_int_limit = Assembler::ldf_op3,
|
|
op3_mask_ldf = 1 << (Assembler::ldf_op3 - op3_ldst_int_limit) |
|
|
1 << (Assembler::lddf_op3 - op3_ldst_int_limit),
|
|
op3_mask_stf = 1 << (Assembler::stf_op3 - op3_ldst_int_limit) |
|
|
1 << (Assembler::stdf_op3 - op3_ldst_int_limit),
|
|
|
|
offset_width = 13,
|
|
sethi_offset = 0,
|
|
#ifdef _LP64
|
|
nop_offset = 7 * BytesPerInstWord,
|
|
#else
|
|
nop_offset = 4,
|
|
#endif
|
|
add_offset = nop_offset + BytesPerInstWord,
|
|
ldst_offset = add_offset + BytesPerInstWord
|
|
};
|
|
bool is_immediate() const {
|
|
// check if instruction is ld* [reg + offset], reg or st* reg, [reg + offset]
|
|
int i0 = long_at(0);
|
|
return (is_op(i0, Assembler::ldst_op));
|
|
}
|
|
|
|
address instruction_address() const { return addr_at(0); }
|
|
address next_instruction_address() const {
|
|
return addr_at(is_immediate()? 4 : 16);
|
|
}
|
|
int offset() const {
|
|
return is_immediate()? inv_simm(long_at(0), offset_width) :
|
|
nativeMovConstRegPatching_at(addr_at(0))->data();
|
|
}
|
|
void set_offset(int x) {
|
|
if (is_immediate()) {
|
|
guarantee(fits_in_simm(x, offset_width), "data block offset overflow");
|
|
set_long_at(0, set_simm(long_at(0), x, offset_width));
|
|
}
|
|
else
|
|
nativeMovConstRegPatching_at(addr_at(0))->set_data(x);
|
|
}
|
|
|
|
void add_offset_in_bytes(intptr_t radd_offset) {
|
|
set_offset (offset() + radd_offset);
|
|
}
|
|
|
|
void copy_instruction_to(address new_instruction_address);
|
|
|
|
void verify();
|
|
void print ();
|
|
|
|
// unit test stuff
|
|
static void test();
|
|
|
|
private:
|
|
friend inline NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) {
|
|
NativeMovRegMemPatching* test = (NativeMovRegMemPatching*)address;
|
|
#ifdef ASSERT
|
|
test->verify();
|
|
#endif
|
|
return test;
|
|
}
|
|
};
|
|
|
|
|
|
// An interface for accessing/manipulating native jumps
|
|
// jump_to addr
|
|
// == sethi %hi22(addr), temp ; jumpl reg, %lo10(addr), G0 ; <delay>
|
|
// jumpl_to addr, lreg
|
|
// == sethi %hi22(addr), temp ; jumpl reg, %lo10(addr), lreg ; <delay>
|
|
class NativeJump;
|
|
inline NativeJump* nativeJump_at(address address);
|
|
class NativeJump: public NativeInstruction {
|
|
private:
|
|
void guarantee_displacement(int disp, int width) {
|
|
guarantee(fits_in_simm(disp, width + 2), "branch displacement overflow");
|
|
}
|
|
|
|
public:
|
|
enum Sparc_specific_constants {
|
|
sethi_offset = 0,
|
|
#ifdef _LP64
|
|
jmpl_offset = 7 * BytesPerInstWord,
|
|
instruction_size = 9 * BytesPerInstWord // includes delay slot
|
|
#else
|
|
jmpl_offset = 1 * BytesPerInstWord,
|
|
instruction_size = 3 * BytesPerInstWord // includes delay slot
|
|
#endif
|
|
};
|
|
|
|
address instruction_address() const { return addr_at(0); }
|
|
address next_instruction_address() const { return addr_at(instruction_size); }
|
|
|
|
#ifdef _LP64
|
|
address jump_destination() const {
|
|
return (address) data64(instruction_address(), long_at(jmpl_offset));
|
|
}
|
|
void set_jump_destination(address dest) {
|
|
set_data64_sethi( instruction_address(), (intptr_t)dest);
|
|
set_long_at(jmpl_offset, set_data32_simm13( long_at(jmpl_offset), (intptr_t)dest));
|
|
}
|
|
#else
|
|
address jump_destination() const {
|
|
return (address) data32(long_at(sethi_offset), long_at(jmpl_offset));
|
|
}
|
|
void set_jump_destination(address dest) {
|
|
set_long_at(sethi_offset, set_data32_sethi( long_at(sethi_offset), (intptr_t)dest));
|
|
set_long_at(jmpl_offset, set_data32_simm13( long_at(jmpl_offset), (intptr_t)dest));
|
|
}
|
|
#endif
|
|
|
|
// Creation
|
|
friend inline NativeJump* nativeJump_at(address address) {
|
|
NativeJump* jump = (NativeJump*)address;
|
|
#ifdef ASSERT
|
|
jump->verify();
|
|
#endif
|
|
return jump;
|
|
}
|
|
|
|
void verify();
|
|
void print();
|
|
|
|
// Unit testing stuff
|
|
static void test();
|
|
|
|
// Insertion of native jump instruction
|
|
static void insert(address code_pos, address entry);
|
|
// MT-safe insertion of native jump at verified method entry
|
|
static void check_verified_entry_alignment(address entry, address verified_entry) {
|
|
// nothing to do for sparc.
|
|
}
|
|
static void patch_verified_entry(address entry, address verified_entry, address dest);
|
|
};
|
|
|
|
|
|
|
|
// Despite the name, handles only simple branches.
|
|
class NativeGeneralJump;
|
|
inline NativeGeneralJump* nativeGeneralJump_at(address address);
|
|
class NativeGeneralJump: public NativeInstruction {
|
|
public:
|
|
enum Sparc_specific_constants {
|
|
instruction_size = 8
|
|
};
|
|
|
|
address instruction_address() const { return addr_at(0); }
|
|
address jump_destination() const { return addr_at(0) + branch_destination_offset(long_at(0)); }
|
|
void set_jump_destination(address dest) {
|
|
int patched_instr = patch_branch_destination_offset(dest - addr_at(0), long_at(0));
|
|
set_long_at(0, patched_instr);
|
|
}
|
|
void set_annul() { set_annul_bit(); }
|
|
NativeInstruction *delay_slot_instr() { return nativeInstruction_at(addr_at(4));}
|
|
void fill_delay_slot(int instr) { set_long_at(4, instr);}
|
|
Assembler::Condition condition() {
|
|
int x = long_at(0);
|
|
return (Assembler::Condition) Assembler::inv_cond(x);
|
|
}
|
|
|
|
// Creation
|
|
friend inline NativeGeneralJump* nativeGeneralJump_at(address address) {
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NativeGeneralJump* jump = (NativeGeneralJump*)(address);
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#ifdef ASSERT
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jump->verify();
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#endif
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return jump;
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}
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// Insertion of native general jump instruction
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static void insert_unconditional(address code_pos, address entry);
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static void replace_mt_safe(address instr_addr, address code_buffer);
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void verify();
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};
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class NativeIllegalInstruction: public NativeInstruction {
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public:
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enum Sparc_specific_constants {
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instruction_size = 4
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};
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// Insert illegal opcode as specific address
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static void insert(address code_pos);
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};
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#endif // CPU_SPARC_VM_NATIVEINST_SPARC_HPP
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