1330 lines
44 KiB
C++
1330 lines
44 KiB
C++
/*
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* Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
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#define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
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#include "asm/register.hpp"
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// The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
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// level; i.e., what you write is what you get. The Assembler is generating code
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// into a CodeBuffer.
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class Assembler : public AbstractAssembler {
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friend class AbstractAssembler;
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friend class AddressLiteral;
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// code patchers need various routines like inv_wdisp()
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friend class NativeInstruction;
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friend class NativeGeneralJump;
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friend class Relocation;
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friend class Label;
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public:
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// op carries format info; see page 62 & 267
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enum ops {
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call_op = 1, // fmt 1
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branch_op = 0, // also sethi (fmt2)
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arith_op = 2, // fmt 3, arith & misc
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ldst_op = 3 // fmt 3, load/store
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};
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enum op2s {
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bpr_op2 = 3,
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fb_op2 = 6,
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fbp_op2 = 5,
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br_op2 = 2,
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bp_op2 = 1,
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sethi_op2 = 4
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};
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enum op3s {
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// selected op3s
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add_op3 = 0x00,
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and_op3 = 0x01,
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or_op3 = 0x02,
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xor_op3 = 0x03,
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sub_op3 = 0x04,
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andn_op3 = 0x05,
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orn_op3 = 0x06,
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xnor_op3 = 0x07,
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addc_op3 = 0x08,
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mulx_op3 = 0x09,
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umul_op3 = 0x0a,
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smul_op3 = 0x0b,
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subc_op3 = 0x0c,
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udivx_op3 = 0x0d,
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udiv_op3 = 0x0e,
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sdiv_op3 = 0x0f,
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addcc_op3 = 0x10,
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andcc_op3 = 0x11,
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orcc_op3 = 0x12,
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xorcc_op3 = 0x13,
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subcc_op3 = 0x14,
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andncc_op3 = 0x15,
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orncc_op3 = 0x16,
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xnorcc_op3 = 0x17,
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addccc_op3 = 0x18,
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aes4_op3 = 0x19,
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umulcc_op3 = 0x1a,
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smulcc_op3 = 0x1b,
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subccc_op3 = 0x1c,
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udivcc_op3 = 0x1e,
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sdivcc_op3 = 0x1f,
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taddcc_op3 = 0x20,
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tsubcc_op3 = 0x21,
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taddcctv_op3 = 0x22,
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tsubcctv_op3 = 0x23,
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mulscc_op3 = 0x24,
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sll_op3 = 0x25,
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sllx_op3 = 0x25,
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srl_op3 = 0x26,
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srlx_op3 = 0x26,
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sra_op3 = 0x27,
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srax_op3 = 0x27,
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rdreg_op3 = 0x28,
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membar_op3 = 0x28,
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flushw_op3 = 0x2b,
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movcc_op3 = 0x2c,
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sdivx_op3 = 0x2d,
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popc_op3 = 0x2e,
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movr_op3 = 0x2f,
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sir_op3 = 0x30,
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wrreg_op3 = 0x30,
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saved_op3 = 0x31,
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fpop1_op3 = 0x34,
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fpop2_op3 = 0x35,
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impdep1_op3 = 0x36,
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addx_op3 = 0x36,
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aes3_op3 = 0x36,
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sha_op3 = 0x36,
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bmask_op3 = 0x36,
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bshuffle_op3 = 0x36,
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alignaddr_op3 = 0x36,
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faligndata_op3 = 0x36,
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flog3_op3 = 0x36,
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edge_op3 = 0x36,
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fzero_op3 = 0x36,
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fsrc_op3 = 0x36,
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fnot_op3 = 0x36,
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mpmul_op3 = 0x36,
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umulx_op3 = 0x36,
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xmulx_op3 = 0x36,
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crc32c_op3 = 0x36,
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impdep2_op3 = 0x37,
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stpartialf_op3 = 0x37,
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jmpl_op3 = 0x38,
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rett_op3 = 0x39,
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trap_op3 = 0x3a,
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flush_op3 = 0x3b,
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save_op3 = 0x3c,
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restore_op3 = 0x3d,
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done_op3 = 0x3e,
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retry_op3 = 0x3e,
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lduw_op3 = 0x00,
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ldub_op3 = 0x01,
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lduh_op3 = 0x02,
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ldd_op3 = 0x03,
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stw_op3 = 0x04,
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stb_op3 = 0x05,
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sth_op3 = 0x06,
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std_op3 = 0x07,
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ldsw_op3 = 0x08,
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ldsb_op3 = 0x09,
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ldsh_op3 = 0x0a,
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ldx_op3 = 0x0b,
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stx_op3 = 0x0e,
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swap_op3 = 0x0f,
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stwa_op3 = 0x14,
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stxa_op3 = 0x1e,
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ldf_op3 = 0x20,
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ldfsr_op3 = 0x21,
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ldqf_op3 = 0x22,
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lddf_op3 = 0x23,
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stf_op3 = 0x24,
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stfsr_op3 = 0x25,
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stqf_op3 = 0x26,
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stdf_op3 = 0x27,
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prefetch_op3 = 0x2d,
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casa_op3 = 0x3c,
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casxa_op3 = 0x3e,
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mftoi_op3 = 0x36,
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alt_bit_op3 = 0x10,
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cc_bit_op3 = 0x10
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};
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enum opfs {
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// selected opfs
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edge8n_opf = 0x01,
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fmovs_opf = 0x01,
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fmovd_opf = 0x02,
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fnegs_opf = 0x05,
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fnegd_opf = 0x06,
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addxc_opf = 0x11,
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addxccc_opf = 0x13,
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umulxhi_opf = 0x16,
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alignaddr_opf = 0x18,
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bmask_opf = 0x19,
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fadds_opf = 0x41,
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faddd_opf = 0x42,
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fsubs_opf = 0x45,
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fsubd_opf = 0x46,
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faligndata_opf = 0x48,
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fmuls_opf = 0x49,
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fmuld_opf = 0x4a,
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bshuffle_opf = 0x4c,
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fdivs_opf = 0x4d,
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fdivd_opf = 0x4e,
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fcmps_opf = 0x51,
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fcmpd_opf = 0x52,
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fstox_opf = 0x81,
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fdtox_opf = 0x82,
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fxtos_opf = 0x84,
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fxtod_opf = 0x88,
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fitos_opf = 0xc4,
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fdtos_opf = 0xc6,
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fitod_opf = 0xc8,
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fstod_opf = 0xc9,
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fstoi_opf = 0xd1,
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fdtoi_opf = 0xd2,
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mdtox_opf = 0x110,
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mstouw_opf = 0x111,
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mstosw_opf = 0x113,
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xmulx_opf = 0x115,
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xmulxhi_opf = 0x116,
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mxtod_opf = 0x118,
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mwtos_opf = 0x119,
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aes_kexpand0_opf = 0x130,
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aes_kexpand2_opf = 0x131,
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sha1_opf = 0x141,
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sha256_opf = 0x142,
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sha512_opf = 0x143,
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crc32c_opf = 0x147,
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mpmul_opf = 0x148
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};
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enum op5s {
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aes_eround01_op5 = 0x00,
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aes_eround23_op5 = 0x01,
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aes_dround01_op5 = 0x02,
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aes_dround23_op5 = 0x03,
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aes_eround01_l_op5 = 0x04,
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aes_eround23_l_op5 = 0x05,
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aes_dround01_l_op5 = 0x06,
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aes_dround23_l_op5 = 0x07,
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aes_kexpand1_op5 = 0x08
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};
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enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
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enum Condition {
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// for FBfcc & FBPfcc instruction
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f_never = 0,
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f_notEqual = 1,
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f_notZero = 1,
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f_lessOrGreater = 2,
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f_unorderedOrLess = 3,
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f_less = 4,
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f_unorderedOrGreater = 5,
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f_greater = 6,
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f_unordered = 7,
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f_always = 8,
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f_equal = 9,
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f_zero = 9,
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f_unorderedOrEqual = 10,
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f_greaterOrEqual = 11,
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f_unorderedOrGreaterOrEqual = 12,
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f_lessOrEqual = 13,
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f_unorderedOrLessOrEqual = 14,
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f_ordered = 15,
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// for integers
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never = 0,
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equal = 1,
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zero = 1,
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lessEqual = 2,
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less = 3,
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lessEqualUnsigned = 4,
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lessUnsigned = 5,
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carrySet = 5,
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negative = 6,
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overflowSet = 7,
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always = 8,
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notEqual = 9,
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notZero = 9,
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greater = 10,
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greaterEqual = 11,
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greaterUnsigned = 12,
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greaterEqualUnsigned = 13,
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carryClear = 13,
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positive = 14,
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overflowClear = 15
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};
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enum CC {
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// ptr_cc is the correct condition code for a pointer or intptr_t:
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icc = 0, xcc = 2, ptr_cc = xcc,
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fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3
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};
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enum PrefetchFcn {
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severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
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};
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public:
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// Helper functions for groups of instructions
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enum Predict { pt = 1, pn = 0 }; // pt = predict taken
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enum Membar_mask_bits { // page 184, v9
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StoreStore = 1 << 3,
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LoadStore = 1 << 2,
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StoreLoad = 1 << 1,
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LoadLoad = 1 << 0,
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Sync = 1 << 6,
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MemIssue = 1 << 5,
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Lookaside = 1 << 4
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};
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static bool is_in_wdisp_range(address a, address b, int nbits) {
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intptr_t d = intptr_t(b) - intptr_t(a);
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return is_simm(d, nbits + 2);
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}
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address target_distance(Label &L) {
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// Assembler::target(L) should be called only when
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// a branch instruction is emitted since non-bound
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// labels record current pc() as a branch address.
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if (L.is_bound()) return target(L);
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// Return current address for non-bound labels.
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return pc();
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}
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// test if label is in simm16 range in words (wdisp16).
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bool is_in_wdisp16_range(Label &L) {
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return is_in_wdisp_range(target_distance(L), pc(), 16);
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}
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// test if the distance between two addresses fits in simm30 range in words
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static bool is_in_wdisp30_range(address a, address b) {
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return is_in_wdisp_range(a, b, 30);
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}
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enum ASIs { // page 72, v9
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ASI_PRIMARY = 0x80,
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ASI_PRIMARY_NOFAULT = 0x82,
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ASI_PRIMARY_LITTLE = 0x88,
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// 8x8-bit partial store
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ASI_PST8_PRIMARY = 0xC0,
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// Block initializing store
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ASI_ST_BLKINIT_PRIMARY = 0xE2,
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// Most-Recently-Used (MRU) BIS variant
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ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2
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// add more from book as needed
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};
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protected:
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// helpers
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// x is supposed to fit in a field "nbits" wide
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// and be sign-extended. Check the range.
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static void assert_signed_range(intptr_t x, int nbits) {
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assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)),
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"value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits);
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}
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static void assert_signed_word_disp_range(intptr_t x, int nbits) {
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assert((x & 3) == 0, "not word aligned");
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assert_signed_range(x, nbits + 2);
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}
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static void assert_unsigned_range(int x, int nbits) {
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assert(juint(x) < juint(1 << nbits), "unsigned constant out of range");
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}
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// fields: note bits numbered from LSB = 0, fields known by inclusive bit range
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static int fmask(juint hi_bit, juint lo_bit) {
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assert(hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");
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return (1 << (hi_bit-lo_bit + 1)) - 1;
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}
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// inverse of u_field
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static int inv_u_field(int x, int hi_bit, int lo_bit) {
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juint r = juint(x) >> lo_bit;
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r &= fmask(hi_bit, lo_bit);
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return int(r);
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}
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// signed version: extract from field and sign-extend
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static int inv_s_field(int x, int hi_bit, int lo_bit) {
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int sign_shift = 31 - hi_bit;
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return inv_u_field(((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
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}
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// given a field that ranges from hi_bit to lo_bit (inclusive,
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// LSB = 0), and an unsigned value for the field,
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// shift it into the field
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#ifdef ASSERT
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static int u_field(int x, int hi_bit, int lo_bit) {
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assert((x & ~fmask(hi_bit, lo_bit)) == 0,
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"value out of range");
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int r = x << lo_bit;
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assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
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return r;
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}
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#else
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// make sure this is inlined as it will reduce code size significantly
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#define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))
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#endif
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static int inv_op(int x) { return inv_u_field(x, 31, 30); }
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static int inv_op2(int x) { return inv_u_field(x, 24, 22); }
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static int inv_op3(int x) { return inv_u_field(x, 24, 19); }
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static int inv_cond(int x) { return inv_u_field(x, 28, 25); }
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static bool inv_immed(int x) { return (x & Assembler::immed(true)) != 0; }
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static Register inv_rd(int x) { return as_Register(inv_u_field(x, 29, 25)); }
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static Register inv_rs1(int x) { return as_Register(inv_u_field(x, 18, 14)); }
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static Register inv_rs2(int x) { return as_Register(inv_u_field(x, 4, 0)); }
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static int op(int x) { return u_field(x, 31, 30); }
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static int rd(Register r) { return u_field(r->encoding(), 29, 25); }
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static int fcn(int x) { return u_field(x, 29, 25); }
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static int op3(int x) { return u_field(x, 24, 19); }
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static int rs1(Register r) { return u_field(r->encoding(), 18, 14); }
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static int rs2(Register r) { return u_field(r->encoding(), 4, 0); }
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static int annul(bool a) { return u_field(a ? 1 : 0, 29, 29); }
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static int cond(int x) { return u_field(x, 28, 25); }
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static int cond_mov(int x) { return u_field(x, 17, 14); }
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static int rcond(RCondition x) { return u_field(x, 12, 10); }
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static int op2(int x) { return u_field(x, 24, 22); }
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static int predict(bool p) { return u_field(p ? 1 : 0, 19, 19); }
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static int branchcc(CC fcca) { return u_field(fcca, 21, 20); }
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static int cmpcc(CC fcca) { return u_field(fcca, 26, 25); }
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static int imm_asi(int x) { return u_field(x, 12, 5); }
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static int immed(bool i) { return u_field(i ? 1 : 0, 13, 13); }
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static int opf_low6(int w) { return u_field(w, 10, 5); }
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static int opf_low5(int w) { return u_field(w, 9, 5); }
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static int op5(int x) { return u_field(x, 8, 5); }
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static int trapcc(CC cc) { return u_field(cc, 12, 11); }
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static int sx(int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
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static int opf(int x) { return u_field(x, 13, 5); }
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static bool is_cbcond(int x) {
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return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
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inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
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}
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static bool is_cxb(int x) {
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assert(is_cbcond(x), "wrong instruction");
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|
return (x & (1 << 21)) != 0;
|
|
}
|
|
static bool is_branch(int x) {
|
|
if (inv_op(x) != Assembler::branch_op) return false;
|
|
|
|
bool is_bpr = inv_op2(x) == Assembler::bpr_op2;
|
|
bool is_bp = inv_op2(x) == Assembler::bp_op2;
|
|
bool is_br = inv_op2(x) == Assembler::br_op2;
|
|
bool is_fp = inv_op2(x) == Assembler::fb_op2;
|
|
bool is_fbp = inv_op2(x) == Assembler::fbp_op2;
|
|
|
|
return is_bpr || is_bp || is_br || is_fp || is_fbp;
|
|
}
|
|
static bool is_call(int x) {
|
|
return inv_op(x) == Assembler::call_op;
|
|
}
|
|
static bool is_jump(int x) {
|
|
if (inv_op(x) != Assembler::arith_op) return false;
|
|
|
|
bool is_jmpl = inv_op3(x) == Assembler::jmpl_op3;
|
|
bool is_rett = inv_op3(x) == Assembler::rett_op3;
|
|
|
|
return is_jmpl || is_rett;
|
|
}
|
|
static bool is_rdpc(int x) {
|
|
return (inv_op(x) == Assembler::arith_op && inv_op3(x) == Assembler::rdreg_op3 &&
|
|
inv_u_field(x, 18, 14) == 5);
|
|
}
|
|
static bool is_cti(int x) {
|
|
return is_branch(x) || is_call(x) || is_jump(x); // Ignoring done/retry
|
|
}
|
|
|
|
static int cond_cbcond(int x) { return u_field((((x & 8) << 1) + 8 + (x & 7)), 29, 25); }
|
|
static int inv_cond_cbcond(int x) {
|
|
assert(is_cbcond(x), "wrong instruction");
|
|
return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29) << 3);
|
|
}
|
|
|
|
static int opf_cc(CC c, bool useFloat) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
|
|
static int mov_cc(CC c, bool useFloat) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
|
|
|
|
static int fd(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
|
|
static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
|
|
static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
|
|
static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); };
|
|
|
|
// some float instructions use this encoding on the op3 field
|
|
static int alt_op3(int op, FloatRegisterImpl::Width w) {
|
|
int r;
|
|
switch(w) {
|
|
case FloatRegisterImpl::S: r = op + 0; break;
|
|
case FloatRegisterImpl::D: r = op + 3; break;
|
|
case FloatRegisterImpl::Q: r = op + 2; break;
|
|
default: ShouldNotReachHere(); break;
|
|
}
|
|
return op3(r);
|
|
}
|
|
|
|
// compute inverse of simm
|
|
static int inv_simm(int x, int nbits) {
|
|
return (int)(x << (32 - nbits)) >> (32 - nbits);
|
|
}
|
|
|
|
static int inv_simm13(int x) { return inv_simm(x, 13); }
|
|
|
|
// signed immediate, in low bits, nbits long
|
|
static int simm(int x, int nbits) {
|
|
assert_signed_range(x, nbits);
|
|
return x & ((1 << nbits) - 1);
|
|
}
|
|
|
|
// unsigned immediate, in low bits, at most nbits long.
|
|
static int uimm(int x, int nbits) {
|
|
assert_unsigned_range(x, nbits);
|
|
return x & ((1 << nbits) - 1);
|
|
}
|
|
|
|
// compute inverse of wdisp16
|
|
static intptr_t inv_wdisp16(int x, intptr_t pos) {
|
|
int lo = x & ((1 << 14) - 1);
|
|
int hi = (x >> 20) & 3;
|
|
if (hi >= 2) hi |= ~1;
|
|
return (((hi << 14) | lo) << 2) + pos;
|
|
}
|
|
|
|
// word offset, 14 bits at LSend, 2 bits at B21, B20
|
|
static int wdisp16(intptr_t x, intptr_t off) {
|
|
intptr_t xx = x - off;
|
|
assert_signed_word_disp_range(xx, 16);
|
|
int r = (xx >> 2) & ((1 << 14) - 1) | (((xx >> (2+14)) & 3) << 20);
|
|
assert(inv_wdisp16(r, off) == x, "inverse is not inverse");
|
|
return r;
|
|
}
|
|
|
|
// compute inverse of wdisp10
|
|
static intptr_t inv_wdisp10(int x, intptr_t pos) {
|
|
assert(is_cbcond(x), "wrong instruction");
|
|
int lo = inv_u_field(x, 12, 5);
|
|
int hi = (x >> 19) & 3;
|
|
if (hi >= 2) hi |= ~1;
|
|
return (((hi << 8) | lo) << 2) + pos;
|
|
}
|
|
|
|
// word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19]
|
|
static int wdisp10(intptr_t x, intptr_t off) {
|
|
assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction");
|
|
intptr_t xx = x - off;
|
|
assert_signed_word_disp_range(xx, 10);
|
|
int r = (((xx >> 2) & ((1 << 8) - 1)) << 5) | (((xx >> (2+8)) & 3) << 19);
|
|
// Have to fake cbcond instruction to pass assert in inv_wdisp10()
|
|
assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse");
|
|
return r;
|
|
}
|
|
|
|
// word displacement in low-order nbits bits
|
|
|
|
static intptr_t inv_wdisp(int x, intptr_t pos, int nbits) {
|
|
int pre_sign_extend = x & ((1 << nbits) - 1);
|
|
int r = (pre_sign_extend >= (1 << (nbits - 1)) ?
|
|
pre_sign_extend | ~((1 << nbits) - 1) : pre_sign_extend);
|
|
return (r << 2) + pos;
|
|
}
|
|
|
|
static int wdisp(intptr_t x, intptr_t off, int nbits) {
|
|
intptr_t xx = x - off;
|
|
assert_signed_word_disp_range(xx, nbits);
|
|
int r = (xx >> 2) & ((1 << nbits) - 1);
|
|
assert(inv_wdisp(r, off, nbits) == x, "inverse not inverse");
|
|
return r;
|
|
}
|
|
|
|
|
|
// Extract the top 32 bits in a 64 bit word
|
|
static int32_t hi32(int64_t x) {
|
|
int32_t r = int32_t((uint64_t)x >> 32);
|
|
return r;
|
|
}
|
|
|
|
// given a sethi instruction, extract the constant, left-justified
|
|
static int inv_hi22(int x) {
|
|
return x << 10;
|
|
}
|
|
|
|
// create an imm22 field, given a 32-bit left-justified constant
|
|
static int hi22(int x) {
|
|
int r = int(juint(x) >> 10);
|
|
assert((r & ~((1 << 22) - 1)) == 0, "just checkin'");
|
|
return r;
|
|
}
|
|
|
|
// create a low10 __value__ (not a field) for a given a 32-bit constant
|
|
static int low10(int x) {
|
|
return x & ((1 << 10) - 1);
|
|
}
|
|
|
|
// create a low12 __value__ (not a field) for a given a 32-bit constant
|
|
static int low12(int x) {
|
|
return x & ((1 << 12) - 1);
|
|
}
|
|
|
|
// AES crypto instructions supported only on certain processors
|
|
static void aes_only() { assert(VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
|
|
|
|
// SHA crypto instructions supported only on certain processors
|
|
static void sha1_only() { assert(VM_Version::has_sha1(), "This instruction only works on SPARC with SHA1"); }
|
|
static void sha256_only() { assert(VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); }
|
|
static void sha512_only() { assert(VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); }
|
|
|
|
// CRC32C instruction supported only on certain processors
|
|
static void crc32c_only() { assert(VM_Version::has_crc32c(), "This instruction only works on SPARC with CRC32C"); }
|
|
|
|
// FMAf instructions supported only on certain processors
|
|
static void fmaf_only() { assert(VM_Version::has_fmaf(), "This instruction only works on SPARC with FMAf"); }
|
|
|
|
// MPMUL instruction supported only on certain processors
|
|
static void mpmul_only() { assert(VM_Version::has_mpmul(), "This instruction only works on SPARC with MPMUL"); }
|
|
|
|
// instruction only in VIS1
|
|
static void vis1_only() { assert(VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
|
|
|
|
// instruction only in VIS2
|
|
static void vis2_only() { assert(VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }
|
|
|
|
// instruction only in VIS3
|
|
static void vis3_only() { assert(VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
|
|
|
|
// instruction deprecated in v9
|
|
static void v9_dep() { } // do nothing for now
|
|
|
|
protected:
|
|
#ifdef ASSERT
|
|
#define VALIDATE_PIPELINE
|
|
#endif
|
|
|
|
#ifdef VALIDATE_PIPELINE
|
|
// A simple delay-slot scheme:
|
|
// In order to check the programmer, the assembler keeps track of delay-slots.
|
|
// It forbids CTIs in delay-slots (conservative, but should be OK). Also, when
|
|
// emitting an instruction into a delay-slot, you must do so using delayed(),
|
|
// e.g. asm->delayed()->add(...), in order to check that you do not omit the
|
|
// delay-slot instruction. To implement this, we use a simple FSA.
|
|
enum { NoDelay, AtDelay, FillDelay } _delay_state;
|
|
|
|
// A simple hazard scheme:
|
|
// In order to avoid pipeline stalls, due to single cycle pipeline hazards, we
|
|
// adopt a simplistic state tracking mechanism that will enforce an additional
|
|
// 'nop' instruction to be inserted prior to emitting an instruction that can
|
|
// expose a given hazard (currently, PC-related hazards only).
|
|
enum { NoHazard, PcHazard } _hazard_state;
|
|
#endif
|
|
|
|
public:
|
|
// Tell the assembler that the next instruction must NOT be in delay-slot.
|
|
// Use at start of multi-instruction macros.
|
|
void assert_not_delayed() {
|
|
// This is a separate entry to avoid the creation of string constants in
|
|
// non-asserted code, with some compilers this pollutes the object code.
|
|
#ifdef VALIDATE_PIPELINE
|
|
assert_no_delay("Next instruction should not be in a delay-slot.");
|
|
#endif
|
|
}
|
|
|
|
protected:
|
|
void assert_no_delay(const char* msg) {
|
|
#ifdef VALIDATE_PIPELINE
|
|
assert(_delay_state == NoDelay, msg);
|
|
#endif
|
|
}
|
|
|
|
void assert_no_hazard() {
|
|
#ifdef VALIDATE_PIPELINE
|
|
assert(_hazard_state == NoHazard, "Unsolicited pipeline hazard.");
|
|
#endif
|
|
}
|
|
|
|
private:
|
|
inline int32_t prev_insn() {
|
|
assert(offset() > 0, "Interface violation.");
|
|
int32_t* addr = (int32_t*)pc() - 1;
|
|
return *addr;
|
|
}
|
|
|
|
#ifdef VALIDATE_PIPELINE
|
|
void validate_no_pipeline_hazards();
|
|
#endif
|
|
|
|
protected:
|
|
// Avoid possible pipeline stall by inserting an additional 'nop' instruction,
|
|
// if the previous instruction is a 'cbcond' or a 'rdpc'.
|
|
inline void avoid_pipeline_stall();
|
|
|
|
// A call to cti() is made before emitting a control-transfer instruction (CTI)
|
|
// in order to assert a CTI is not emitted right after a 'cbcond', nor in the
|
|
// delay-slot of another CTI. Only effective when assertions are enabled.
|
|
void cti() {
|
|
// A 'cbcond' or 'rdpc' instruction immediately followed by a CTI introduces
|
|
// a pipeline stall, which we make sure to prohibit.
|
|
assert_no_cbcond_before();
|
|
assert_no_rdpc_before();
|
|
#ifdef VALIDATE_PIPELINE
|
|
assert_no_hazard();
|
|
assert_no_delay("CTI in delay-slot.");
|
|
#endif
|
|
}
|
|
|
|
// Called when emitting CTI with a delay-slot, AFTER emitting.
|
|
inline void induce_delay_slot() {
|
|
#ifdef VALIDATE_PIPELINE
|
|
assert_no_delay("Already in delay-slot.");
|
|
_delay_state = AtDelay;
|
|
#endif
|
|
}
|
|
|
|
inline void induce_pc_hazard() {
|
|
#ifdef VALIDATE_PIPELINE
|
|
assert_no_hazard();
|
|
_hazard_state = PcHazard;
|
|
#endif
|
|
}
|
|
|
|
bool is_cbcond_before() { return offset() > 0 ? is_cbcond(prev_insn()) : false; }
|
|
|
|
bool is_rdpc_before() { return offset() > 0 ? is_rdpc(prev_insn()) : false; }
|
|
|
|
void assert_no_cbcond_before() {
|
|
assert(offset() == 0 || !is_cbcond_before(), "CBCOND should not be followed by CTI.");
|
|
}
|
|
|
|
void assert_no_rdpc_before() {
|
|
assert(offset() == 0 || !is_rdpc_before(), "RDPC should not be followed by CTI.");
|
|
}
|
|
|
|
public:
|
|
|
|
bool use_cbcond(Label &L) {
|
|
if (!UseCBCond || is_cbcond_before()) return false;
|
|
intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
|
|
assert((x & 3) == 0, "not word aligned");
|
|
return is_simm12(x);
|
|
}
|
|
|
|
// Tells assembler you know that next instruction is delayed
|
|
Assembler* delayed() {
|
|
#ifdef VALIDATE_PIPELINE
|
|
assert(_delay_state == AtDelay, "Delayed instruction not in delay-slot.");
|
|
_delay_state = FillDelay;
|
|
#endif
|
|
return this;
|
|
}
|
|
|
|
void flush() {
|
|
#ifdef VALIDATE_PIPELINE
|
|
assert(_delay_state == NoDelay, "Ending code with a delay-slot.");
|
|
validate_no_pipeline_hazards();
|
|
#endif
|
|
AbstractAssembler::flush();
|
|
}
|
|
|
|
inline void emit_int32(int32_t); // shadows AbstractAssembler::emit_int32
|
|
inline void emit_data(int32_t);
|
|
inline void emit_data(int32_t, RelocationHolder const&);
|
|
inline void emit_data(int32_t, relocInfo::relocType rtype);
|
|
|
|
// Helper for the above functions.
|
|
inline void check_delay();
|
|
|
|
|
|
public:
|
|
// instructions, refer to page numbers in the SPARC Architecture Manual, V9
|
|
|
|
// pp 135
|
|
|
|
inline void add(Register s1, Register s2, Register d);
|
|
inline void add(Register s1, int simm13a, Register d);
|
|
|
|
inline void addcc(Register s1, Register s2, Register d);
|
|
inline void addcc(Register s1, int simm13a, Register d);
|
|
inline void addc(Register s1, Register s2, Register d);
|
|
inline void addc(Register s1, int simm13a, Register d);
|
|
inline void addccc(Register s1, Register s2, Register d);
|
|
inline void addccc(Register s1, int simm13a, Register d);
|
|
|
|
|
|
// 4-operand AES instructions
|
|
|
|
inline void aes_eround01(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
|
|
inline void aes_eround23(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
|
|
inline void aes_dround01(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
|
|
inline void aes_dround23(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
|
|
inline void aes_eround01_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
|
|
inline void aes_eround23_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
|
|
inline void aes_dround01_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
|
|
inline void aes_dround23_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
|
|
inline void aes_kexpand1(FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d);
|
|
|
|
|
|
// 3-operand AES instructions
|
|
|
|
inline void aes_kexpand0(FloatRegister s1, FloatRegister s2, FloatRegister d);
|
|
inline void aes_kexpand2(FloatRegister s1, FloatRegister s2, FloatRegister d);
|
|
|
|
// pp 136
|
|
|
|
inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
|
|
inline void bpr(RCondition c, bool a, Predict p, Register s1, Label &L);
|
|
|
|
// compare and branch
|
|
inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label &L);
|
|
inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label &L);
|
|
|
|
protected: // use MacroAssembler::br instead
|
|
|
|
// pp 138
|
|
|
|
inline void fb(Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none);
|
|
inline void fb(Condition c, bool a, Label &L);
|
|
|
|
// pp 141
|
|
|
|
inline void fbp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none);
|
|
inline void fbp(Condition c, bool a, CC cc, Predict p, Label &L);
|
|
|
|
// pp 144
|
|
|
|
inline void br(Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none);
|
|
inline void br(Condition c, bool a, Label &L);
|
|
|
|
// pp 146
|
|
|
|
inline void bp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none);
|
|
inline void bp(Condition c, bool a, CC cc, Predict p, Label &L);
|
|
|
|
// pp 149
|
|
|
|
inline void call(address d, relocInfo::relocType rt = relocInfo::runtime_call_type);
|
|
inline void call(Label &L, relocInfo::relocType rt = relocInfo::runtime_call_type);
|
|
|
|
inline void call(address d, RelocationHolder const &rspec);
|
|
|
|
public:
|
|
|
|
// pp 150
|
|
|
|
// These instructions compare the contents of s2 with the contents of
|
|
// memory at address in s1. If the values are equal, the contents of memory
|
|
// at address s1 is swapped with the data in d. If the values are not equal,
|
|
// the the contents of memory at s1 is loaded into d, without the swap.
|
|
|
|
inline void casa(Register s1, Register s2, Register d, int ia = -1);
|
|
inline void casxa(Register s1, Register s2, Register d, int ia = -1);
|
|
|
|
// pp 152
|
|
|
|
inline void udiv(Register s1, Register s2, Register d);
|
|
inline void udiv(Register s1, int simm13a, Register d);
|
|
inline void sdiv(Register s1, Register s2, Register d);
|
|
inline void sdiv(Register s1, int simm13a, Register d);
|
|
inline void udivcc(Register s1, Register s2, Register d);
|
|
inline void udivcc(Register s1, int simm13a, Register d);
|
|
inline void sdivcc(Register s1, Register s2, Register d);
|
|
inline void sdivcc(Register s1, int simm13a, Register d);
|
|
|
|
// pp 155
|
|
|
|
inline void done();
|
|
inline void retry();
|
|
|
|
// pp 156
|
|
|
|
inline void fadd(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d);
|
|
inline void fsub(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d);
|
|
|
|
// pp 157
|
|
|
|
inline void fcmp(FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2);
|
|
inline void fcmpe(FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2);
|
|
|
|
// pp 159
|
|
|
|
inline void ftox(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
|
|
inline void ftoi(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
|
|
|
|
// pp 160
|
|
|
|
inline void ftof(FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d);
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// pp 161
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inline void fxtof(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
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inline void fitof(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
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|
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// pp 162
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inline void fmov(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
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|
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inline void fneg(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
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inline void fabs(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
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// pp 163
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inline void fmul(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d);
|
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inline void fmul(FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d);
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inline void fdiv(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d);
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// FXORs/FXORd instructions
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inline void fxor(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d);
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|
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// pp 164
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inline void fsqrt(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
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// fmaf instructions.
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|
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inline void fmadd(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
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inline void fmsub(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
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inline void fnmadd(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
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inline void fnmsub(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
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// pp 165
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inline void flush(Register s1, Register s2);
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inline void flush(Register s1, int simm13a);
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// pp 167
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void flushw();
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// pp 168
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void illtrap(int const22a);
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// pp 169
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void impdep1(int id1, int const19a);
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void impdep2(int id1, int const19a);
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// pp 170
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void jmpl(Register s1, Register s2, Register d);
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void jmpl(Register s1, int simm13a, Register d,
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RelocationHolder const &rspec = RelocationHolder());
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// 171
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inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
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inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d,
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RelocationHolder const &rspec = RelocationHolder());
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inline void ldd(Register s1, Register s2, FloatRegister d);
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inline void ldd(Register s1, int simm13a, FloatRegister d);
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inline void ldfsr(Register s1, Register s2);
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inline void ldfsr(Register s1, int simm13a);
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inline void ldxfsr(Register s1, Register s2);
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inline void ldxfsr(Register s1, int simm13a);
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// 173
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inline void ldfa(FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d);
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inline void ldfa(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d);
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// pp 175
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|
inline void ldsb(Register s1, Register s2, Register d);
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inline void ldsb(Register s1, int simm13a, Register d);
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inline void ldsh(Register s1, Register s2, Register d);
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inline void ldsh(Register s1, int simm13a, Register d);
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inline void ldsw(Register s1, Register s2, Register d);
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inline void ldsw(Register s1, int simm13a, Register d);
|
|
inline void ldub(Register s1, Register s2, Register d);
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|
inline void ldub(Register s1, int simm13a, Register d);
|
|
inline void lduh(Register s1, Register s2, Register d);
|
|
inline void lduh(Register s1, int simm13a, Register d);
|
|
inline void lduw(Register s1, Register s2, Register d);
|
|
inline void lduw(Register s1, int simm13a, Register d);
|
|
inline void ldx(Register s1, Register s2, Register d);
|
|
inline void ldx(Register s1, int simm13a, Register d);
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|
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// pp 177
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|
|
|
inline void ldsba(Register s1, Register s2, int ia, Register d);
|
|
inline void ldsba(Register s1, int simm13a, Register d);
|
|
inline void ldsha(Register s1, Register s2, int ia, Register d);
|
|
inline void ldsha(Register s1, int simm13a, Register d);
|
|
inline void ldswa(Register s1, Register s2, int ia, Register d);
|
|
inline void ldswa(Register s1, int simm13a, Register d);
|
|
inline void lduba(Register s1, Register s2, int ia, Register d);
|
|
inline void lduba(Register s1, int simm13a, Register d);
|
|
inline void lduha(Register s1, Register s2, int ia, Register d);
|
|
inline void lduha(Register s1, int simm13a, Register d);
|
|
inline void lduwa(Register s1, Register s2, int ia, Register d);
|
|
inline void lduwa(Register s1, int simm13a, Register d);
|
|
inline void ldxa(Register s1, Register s2, int ia, Register d);
|
|
inline void ldxa(Register s1, int simm13a, Register d);
|
|
|
|
// pp 181
|
|
|
|
inline void and3(Register s1, Register s2, Register d);
|
|
inline void and3(Register s1, int simm13a, Register d);
|
|
inline void andcc(Register s1, Register s2, Register d);
|
|
inline void andcc(Register s1, int simm13a, Register d);
|
|
inline void andn(Register s1, Register s2, Register d);
|
|
inline void andn(Register s1, int simm13a, Register d);
|
|
inline void andncc(Register s1, Register s2, Register d);
|
|
inline void andncc(Register s1, int simm13a, Register d);
|
|
inline void or3(Register s1, Register s2, Register d);
|
|
inline void or3(Register s1, int simm13a, Register d);
|
|
inline void orcc(Register s1, Register s2, Register d);
|
|
inline void orcc(Register s1, int simm13a, Register d);
|
|
inline void orn(Register s1, Register s2, Register d);
|
|
inline void orn(Register s1, int simm13a, Register d);
|
|
inline void orncc(Register s1, Register s2, Register d);
|
|
inline void orncc(Register s1, int simm13a, Register d);
|
|
inline void xor3(Register s1, Register s2, Register d);
|
|
inline void xor3(Register s1, int simm13a, Register d);
|
|
inline void xorcc(Register s1, Register s2, Register d);
|
|
inline void xorcc(Register s1, int simm13a, Register d);
|
|
inline void xnor(Register s1, Register s2, Register d);
|
|
inline void xnor(Register s1, int simm13a, Register d);
|
|
inline void xnorcc(Register s1, Register s2, Register d);
|
|
inline void xnorcc(Register s1, int simm13a, Register d);
|
|
|
|
// pp 183
|
|
|
|
inline void membar(Membar_mask_bits const7a);
|
|
|
|
// pp 185
|
|
|
|
inline void fmov(FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d);
|
|
|
|
// pp 189
|
|
|
|
inline void fmov(FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d);
|
|
|
|
// pp 191
|
|
|
|
inline void movcc(Condition c, bool floatCC, CC cca, Register s2, Register d);
|
|
inline void movcc(Condition c, bool floatCC, CC cca, int simm11a, Register d);
|
|
|
|
// pp 195
|
|
|
|
inline void movr(RCondition c, Register s1, Register s2, Register d);
|
|
inline void movr(RCondition c, Register s1, int simm10a, Register d);
|
|
|
|
// pp 196
|
|
|
|
inline void mulx(Register s1, Register s2, Register d);
|
|
inline void mulx(Register s1, int simm13a, Register d);
|
|
inline void sdivx(Register s1, Register s2, Register d);
|
|
inline void sdivx(Register s1, int simm13a, Register d);
|
|
inline void udivx(Register s1, Register s2, Register d);
|
|
inline void udivx(Register s1, int simm13a, Register d);
|
|
|
|
// pp 197
|
|
|
|
inline void umul(Register s1, Register s2, Register d);
|
|
inline void umul(Register s1, int simm13a, Register d);
|
|
inline void smul(Register s1, Register s2, Register d);
|
|
inline void smul(Register s1, int simm13a, Register d);
|
|
inline void umulcc(Register s1, Register s2, Register d);
|
|
inline void umulcc(Register s1, int simm13a, Register d);
|
|
inline void smulcc(Register s1, Register s2, Register d);
|
|
inline void smulcc(Register s1, int simm13a, Register d);
|
|
|
|
// pp 201
|
|
|
|
inline void nop();
|
|
|
|
inline void sw_count();
|
|
|
|
// pp 202
|
|
|
|
inline void popc(Register s, Register d);
|
|
inline void popc(int simm13a, Register d);
|
|
|
|
// pp 203
|
|
|
|
inline void prefetch(Register s1, Register s2, PrefetchFcn f);
|
|
inline void prefetch(Register s1, int simm13a, PrefetchFcn f);
|
|
|
|
inline void prefetcha(Register s1, Register s2, int ia, PrefetchFcn f);
|
|
inline void prefetcha(Register s1, int simm13a, PrefetchFcn f);
|
|
|
|
// pp 208
|
|
|
|
// not implementing read privileged register
|
|
|
|
inline void rdy(Register d);
|
|
inline void rdccr(Register d);
|
|
inline void rdasi(Register d);
|
|
inline void rdtick(Register d);
|
|
inline void rdpc(Register d);
|
|
inline void rdfprs(Register d);
|
|
|
|
// pp 213
|
|
|
|
inline void rett(Register s1, Register s2);
|
|
inline void rett(Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
|
|
|
|
// pp 214
|
|
|
|
inline void save(Register s1, Register s2, Register d);
|
|
inline void save(Register s1, int simm13a, Register d);
|
|
|
|
inline void restore(Register s1 = G0, Register s2 = G0, Register d = G0);
|
|
inline void restore(Register s1, int simm13a, Register d);
|
|
|
|
// pp 216
|
|
|
|
inline void saved();
|
|
inline void restored();
|
|
|
|
// pp 217
|
|
|
|
inline void sethi(int imm22a, Register d, RelocationHolder const &rspec = RelocationHolder());
|
|
|
|
// pp 218
|
|
|
|
inline void sll(Register s1, Register s2, Register d);
|
|
inline void sll(Register s1, int imm5a, Register d);
|
|
inline void srl(Register s1, Register s2, Register d);
|
|
inline void srl(Register s1, int imm5a, Register d);
|
|
inline void sra(Register s1, Register s2, Register d);
|
|
inline void sra(Register s1, int imm5a, Register d);
|
|
|
|
inline void sllx(Register s1, Register s2, Register d);
|
|
inline void sllx(Register s1, int imm6a, Register d);
|
|
inline void srlx(Register s1, Register s2, Register d);
|
|
inline void srlx(Register s1, int imm6a, Register d);
|
|
inline void srax(Register s1, Register s2, Register d);
|
|
inline void srax(Register s1, int imm6a, Register d);
|
|
|
|
// pp 220
|
|
|
|
inline void sir(int simm13a);
|
|
|
|
// pp 221
|
|
|
|
inline void stbar();
|
|
|
|
// pp 222
|
|
|
|
inline void stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
|
|
inline void stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
|
|
|
|
inline void std(FloatRegister d, Register s1, Register s2);
|
|
inline void std(FloatRegister d, Register s1, int simm13a);
|
|
|
|
inline void stfsr(Register s1, Register s2);
|
|
inline void stfsr(Register s1, int simm13a);
|
|
inline void stxfsr(Register s1, Register s2);
|
|
inline void stxfsr(Register s1, int simm13a);
|
|
|
|
// pp 224
|
|
|
|
inline void stfa(FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia);
|
|
inline void stfa(FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
|
|
|
|
// pp 226
|
|
|
|
inline void stb(Register d, Register s1, Register s2);
|
|
inline void stb(Register d, Register s1, int simm13a);
|
|
inline void sth(Register d, Register s1, Register s2);
|
|
inline void sth(Register d, Register s1, int simm13a);
|
|
inline void stw(Register d, Register s1, Register s2);
|
|
inline void stw(Register d, Register s1, int simm13a);
|
|
inline void stx(Register d, Register s1, Register s2);
|
|
inline void stx(Register d, Register s1, int simm13a);
|
|
|
|
// pp 177
|
|
|
|
inline void stba(Register d, Register s1, Register s2, int ia);
|
|
inline void stba(Register d, Register s1, int simm13a);
|
|
inline void stha(Register d, Register s1, Register s2, int ia);
|
|
inline void stha(Register d, Register s1, int simm13a);
|
|
inline void stwa(Register d, Register s1, Register s2, int ia);
|
|
inline void stwa(Register d, Register s1, int simm13a);
|
|
inline void stxa(Register d, Register s1, Register s2, int ia);
|
|
inline void stxa(Register d, Register s1, int simm13a);
|
|
inline void stda(Register d, Register s1, Register s2, int ia);
|
|
inline void stda(Register d, Register s1, int simm13a);
|
|
|
|
// pp 230
|
|
|
|
inline void sub(Register s1, Register s2, Register d);
|
|
inline void sub(Register s1, int simm13a, Register d);
|
|
|
|
inline void subcc(Register s1, Register s2, Register d);
|
|
inline void subcc(Register s1, int simm13a, Register d);
|
|
inline void subc(Register s1, Register s2, Register d);
|
|
inline void subc(Register s1, int simm13a, Register d);
|
|
inline void subccc(Register s1, Register s2, Register d);
|
|
inline void subccc(Register s1, int simm13a, Register d);
|
|
|
|
// pp 231
|
|
|
|
inline void swap(Register s1, Register s2, Register d);
|
|
inline void swap(Register s1, int simm13a, Register d);
|
|
|
|
// pp 232
|
|
|
|
inline void swapa(Register s1, Register s2, int ia, Register d);
|
|
inline void swapa(Register s1, int simm13a, Register d);
|
|
|
|
// pp 234, note op in book is wrong, see pp 268
|
|
|
|
inline void taddcc(Register s1, Register s2, Register d);
|
|
inline void taddcc(Register s1, int simm13a, Register d);
|
|
|
|
// pp 235
|
|
|
|
inline void tsubcc(Register s1, Register s2, Register d);
|
|
inline void tsubcc(Register s1, int simm13a, Register d);
|
|
|
|
// pp 237
|
|
|
|
inline void trap(Condition c, CC cc, Register s1, Register s2);
|
|
inline void trap(Condition c, CC cc, Register s1, int trapa);
|
|
// simple uncond. trap
|
|
inline void trap(int trapa);
|
|
|
|
// pp 239 omit write priv register for now
|
|
|
|
inline void wry(Register d);
|
|
inline void wrccr(Register s);
|
|
inline void wrccr(Register s, int simm13a);
|
|
inline void wrasi(Register d);
|
|
// wrasi(d, imm) stores (d xor imm) to asi
|
|
inline void wrasi(Register d, int simm13a);
|
|
inline void wrfprs(Register d);
|
|
|
|
// VIS1 instructions
|
|
|
|
inline void alignaddr(Register s1, Register s2, Register d);
|
|
|
|
inline void faligndata(FloatRegister s1, FloatRegister s2, FloatRegister d);
|
|
|
|
inline void fzero(FloatRegisterImpl::Width w, FloatRegister d);
|
|
|
|
inline void fsrc2(FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d);
|
|
|
|
inline void fnot1(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister d);
|
|
|
|
inline void fpmerge(FloatRegister s1, FloatRegister s2, FloatRegister d);
|
|
|
|
inline void stpartialf(Register s1, Register s2, FloatRegister d, int ia = -1);
|
|
|
|
// VIS2 instructions
|
|
|
|
inline void edge8n(Register s1, Register s2, Register d);
|
|
|
|
inline void bmask(Register s1, Register s2, Register d);
|
|
inline void bshuffle(FloatRegister s1, FloatRegister s2, FloatRegister d);
|
|
|
|
// VIS3 instructions
|
|
|
|
inline void addxc(Register s1, Register s2, Register d);
|
|
inline void addxccc(Register s1, Register s2, Register d);
|
|
|
|
inline void movstosw(FloatRegister s, Register d);
|
|
inline void movstouw(FloatRegister s, Register d);
|
|
inline void movdtox(FloatRegister s, Register d);
|
|
|
|
inline void movwtos(Register s, FloatRegister d);
|
|
inline void movxtod(Register s, FloatRegister d);
|
|
|
|
inline void xmulx(Register s1, Register s2, Register d);
|
|
inline void xmulxhi(Register s1, Register s2, Register d);
|
|
inline void umulxhi(Register s1, Register s2, Register d);
|
|
|
|
// Crypto SHA instructions
|
|
|
|
inline void sha1();
|
|
inline void sha256();
|
|
inline void sha512();
|
|
|
|
// CRC32C instruction
|
|
|
|
inline void crc32c(FloatRegister s1, FloatRegister s2, FloatRegister d);
|
|
|
|
// MPMUL instruction
|
|
|
|
inline void mpmul(int uimm5);
|
|
|
|
// Creation
|
|
Assembler(CodeBuffer* code) : AbstractAssembler(code) {
|
|
#ifdef VALIDATE_PIPELINE
|
|
_delay_state = NoDelay;
|
|
_hazard_state = NoHazard;
|
|
#endif
|
|
}
|
|
};
|
|
|
|
#endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
|