d801fa5d9d
Renamed Core Sx to Core Cx (C3, C4, C5, according to name change). Reviewed-by: kvn, dholmes
123 lines
7.3 KiB
C++
123 lines
7.3 KiB
C++
/*
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* Copyright (c) 2001, 2015, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#ifndef CPU_SPARC_VM_VMSTRUCTS_SPARC_HPP
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#define CPU_SPARC_VM_VMSTRUCTS_SPARC_HPP
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// These are the CPU-specific fields, types and integer
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// constants required by the Serviceability Agent. This file is
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// referenced by vmStructs.cpp.
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#define VM_STRUCTS_CPU(nonstatic_field, static_field, unchecked_nonstatic_field, volatile_nonstatic_field, nonproduct_nonstatic_field, c2_nonstatic_field, unchecked_c1_static_field, unchecked_c2_static_field) \
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volatile_nonstatic_field(JavaFrameAnchor, _flags, int)
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#define VM_TYPES_CPU(declare_type, declare_toplevel_type, declare_oop_type, declare_integer_type, declare_unsigned_integer_type, declare_c1_toplevel_type, declare_c2_type, declare_c2_toplevel_type) \
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#define VM_INT_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant) \
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/******************************/ \
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/* Register numbers (C2 only) */ \
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/******************************/ \
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\
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declare_c2_constant(R_L0_num) \
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declare_c2_constant(R_L1_num) \
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declare_c2_constant(R_L2_num) \
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declare_c2_constant(R_L3_num) \
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declare_c2_constant(R_L4_num) \
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declare_c2_constant(R_L5_num) \
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declare_c2_constant(R_L6_num) \
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declare_c2_constant(R_L7_num) \
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declare_c2_constant(R_I0_num) \
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declare_c2_constant(R_I1_num) \
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declare_c2_constant(R_I2_num) \
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declare_c2_constant(R_I3_num) \
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declare_c2_constant(R_I4_num) \
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declare_c2_constant(R_I5_num) \
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declare_c2_constant(R_FP_num) \
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declare_c2_constant(R_I7_num) \
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declare_c2_constant(R_O0_num) \
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declare_c2_constant(R_O1_num) \
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declare_c2_constant(R_O2_num) \
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declare_c2_constant(R_O3_num) \
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declare_c2_constant(R_O4_num) \
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declare_c2_constant(R_O5_num) \
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declare_c2_constant(R_SP_num) \
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declare_c2_constant(R_O7_num) \
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declare_c2_constant(R_G0_num) \
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declare_c2_constant(R_G1_num) \
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declare_c2_constant(R_G2_num) \
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declare_c2_constant(R_G3_num) \
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declare_c2_constant(R_G4_num) \
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declare_c2_constant(R_G5_num) \
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declare_c2_constant(R_G6_num) \
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declare_c2_constant(R_G7_num) \
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declare_constant(VM_Version::ISA_V9) \
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declare_constant(VM_Version::ISA_POPC) \
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declare_constant(VM_Version::ISA_VIS1) \
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declare_constant(VM_Version::ISA_VIS2) \
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declare_constant(VM_Version::ISA_BLK_INIT) \
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declare_constant(VM_Version::ISA_FMAF) \
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declare_constant(VM_Version::ISA_VIS3) \
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declare_constant(VM_Version::ISA_HPC) \
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declare_constant(VM_Version::ISA_IMA) \
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declare_constant(VM_Version::ISA_AES) \
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declare_constant(VM_Version::ISA_DES) \
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declare_constant(VM_Version::ISA_KASUMI) \
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declare_constant(VM_Version::ISA_CAMELLIA) \
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declare_constant(VM_Version::ISA_MD5) \
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declare_constant(VM_Version::ISA_SHA1) \
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declare_constant(VM_Version::ISA_SHA256) \
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declare_constant(VM_Version::ISA_SHA512) \
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declare_constant(VM_Version::ISA_MPMUL) \
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declare_constant(VM_Version::ISA_MONT) \
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declare_constant(VM_Version::ISA_PAUSE) \
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declare_constant(VM_Version::ISA_CBCOND) \
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declare_constant(VM_Version::ISA_CRC32C) \
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declare_constant(VM_Version::ISA_VIS3B) \
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declare_constant(VM_Version::ISA_ADI) \
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declare_constant(VM_Version::ISA_SPARC5) \
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declare_constant(VM_Version::ISA_MWAIT) \
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declare_constant(VM_Version::ISA_XMPMUL) \
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declare_constant(VM_Version::ISA_XMONT) \
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declare_constant(VM_Version::ISA_PAUSE_NSEC) \
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declare_constant(VM_Version::ISA_VAMASK) \
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declare_constant(VM_Version::ISA_SPARC6) \
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declare_constant(VM_Version::ISA_DICTUNP) \
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declare_constant(VM_Version::ISA_FPCMPSHL) \
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declare_constant(VM_Version::ISA_RLE) \
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declare_constant(VM_Version::ISA_SHA3) \
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declare_constant(VM_Version::ISA_VIS3C) \
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declare_constant(VM_Version::ISA_SPARC5B) \
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declare_constant(VM_Version::ISA_MME) \
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declare_constant(VM_Version::CPU_FAST_IDIV) \
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declare_constant(VM_Version::CPU_FAST_RDPC) \
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declare_constant(VM_Version::CPU_FAST_BIS) \
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declare_constant(VM_Version::CPU_FAST_LD) \
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declare_constant(VM_Version::CPU_FAST_CMOVE) \
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declare_constant(VM_Version::CPU_FAST_IND_BR) \
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declare_constant(VM_Version::CPU_BLK_ZEROING)
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#define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant)
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#endif // CPU_SPARC_VM_VMSTRUCTS_SPARC_HPP
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