867 lines
30 KiB
C++
867 lines
30 KiB
C++
/*
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* Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#include "precompiled.hpp"
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#include "gc/shared/collectedHeap.hpp"
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#include "memory/universe.hpp"
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#include "oops/compressedOops.hpp"
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#include "opto/machnode.hpp"
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#include "opto/output.hpp"
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#include "opto/regalloc.hpp"
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#include "utilities/vmError.hpp"
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//=============================================================================
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// Return the value requested
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// result register lookup, corresponding to int_format
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int MachOper::reg(PhaseRegAlloc *ra_, const Node *node) const {
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return (int)ra_->get_encode(node);
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}
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// input register lookup, corresponding to ext_format
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int MachOper::reg(PhaseRegAlloc *ra_, const Node *node, int idx) const {
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return (int)(ra_->get_encode(node->in(idx)));
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}
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intptr_t MachOper::constant() const { return 0x00; }
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relocInfo::relocType MachOper::constant_reloc() const { return relocInfo::none; }
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jdouble MachOper::constantD() const { ShouldNotReachHere(); return 0.0; }
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jfloat MachOper::constantF() const { ShouldNotReachHere(); return 0.0; }
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jlong MachOper::constantL() const { ShouldNotReachHere(); return CONST64(0) ; }
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TypeOopPtr *MachOper::oop() const { return NULL; }
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int MachOper::ccode() const { return 0x00; }
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// A zero, default, indicates this value is not needed.
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// May need to lookup the base register, as done in int_ and ext_format
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int MachOper::base (PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; }
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int MachOper::index(PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; }
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int MachOper::scale() const { return 0x00; }
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int MachOper::disp (PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; }
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int MachOper::constant_disp() const { return 0; }
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int MachOper::base_position() const { return -1; } // no base input
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int MachOper::index_position() const { return -1; } // no index input
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// Check for PC-Relative displacement
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relocInfo::relocType MachOper::disp_reloc() const { return relocInfo::none; }
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// Return the label
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Label* MachOper::label() const { ShouldNotReachHere(); return 0; }
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intptr_t MachOper::method() const { ShouldNotReachHere(); return 0; }
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//------------------------------negate-----------------------------------------
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// Negate conditional branches. Error for non-branch operands
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void MachOper::negate() {
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ShouldNotCallThis();
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}
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//-----------------------------type--------------------------------------------
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const Type *MachOper::type() const {
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return Type::BOTTOM;
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}
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//------------------------------in_RegMask-------------------------------------
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const RegMask *MachOper::in_RegMask(int index) const {
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ShouldNotReachHere();
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return NULL;
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}
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//------------------------------dump_spec--------------------------------------
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// Print any per-operand special info
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#ifndef PRODUCT
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void MachOper::dump_spec(outputStream *st) const { }
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#endif
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//------------------------------hash-------------------------------------------
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// Print any per-operand special info
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uint MachOper::hash() const {
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ShouldNotCallThis();
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return 5;
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}
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//------------------------------cmp--------------------------------------------
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// Print any per-operand special info
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bool MachOper::cmp( const MachOper &oper ) const {
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ShouldNotCallThis();
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return opcode() == oper.opcode();
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}
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//------------------------------hash-------------------------------------------
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// Print any per-operand special info
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uint labelOper::hash() const {
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return _block_num;
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}
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//------------------------------cmp--------------------------------------------
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// Print any per-operand special info
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bool labelOper::cmp( const MachOper &oper ) const {
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return (opcode() == oper.opcode()) && (_label == oper.label());
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}
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//------------------------------hash-------------------------------------------
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// Print any per-operand special info
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uint methodOper::hash() const {
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return (uint)_method;
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}
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//------------------------------cmp--------------------------------------------
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// Print any per-operand special info
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bool methodOper::cmp( const MachOper &oper ) const {
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return (opcode() == oper.opcode()) && (_method == oper.method());
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}
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//=============================================================================
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//------------------------------MachNode---------------------------------------
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//------------------------------emit-------------------------------------------
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void MachNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
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#ifdef ASSERT
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tty->print("missing MachNode emit function: ");
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dump();
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#endif
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ShouldNotCallThis();
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}
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//---------------------------postalloc_expand----------------------------------
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// Expand node after register allocation.
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void MachNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {}
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//------------------------------size-------------------------------------------
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// Size of instruction in bytes
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uint MachNode::size(PhaseRegAlloc *ra_) const {
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// If a virtual was not defined for this specific instruction,
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// Call the helper which finds the size by emitting the bits.
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return MachNode::emit_size(ra_);
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}
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//------------------------------size-------------------------------------------
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// Helper function that computes size by emitting code
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uint MachNode::emit_size(PhaseRegAlloc *ra_) const {
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// Emit into a trash buffer and count bytes emitted.
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assert(ra_ == ra_->C->regalloc(), "sanity");
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return ra_->C->output()->scratch_emit_size(this);
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}
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//------------------------------hash-------------------------------------------
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uint MachNode::hash() const {
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uint no = num_opnds();
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uint sum = rule();
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for( uint i=0; i<no; i++ )
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sum += _opnds[i]->hash();
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return sum+Node::hash();
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}
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//-----------------------------cmp---------------------------------------------
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bool MachNode::cmp( const Node &node ) const {
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MachNode& n = *((Node&)node).as_Mach();
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uint no = num_opnds();
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if( no != n.num_opnds() ) return false;
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if( rule() != n.rule() ) return false;
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for( uint i=0; i<no; i++ ) // All operands must match
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if( !_opnds[i]->cmp( *n._opnds[i] ) )
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return false; // mis-matched operands
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return true; // match
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}
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// Return an equivalent instruction using memory for cisc_operand position
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MachNode *MachNode::cisc_version(int offset) {
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ShouldNotCallThis();
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return NULL;
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}
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void MachNode::use_cisc_RegMask() {
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ShouldNotReachHere();
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}
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//-----------------------------in_RegMask--------------------------------------
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const RegMask &MachNode::in_RegMask( uint idx ) const {
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uint numopnds = num_opnds(); // Virtual call for number of operands
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uint skipped = oper_input_base(); // Sum of leaves skipped so far
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if( idx < skipped ) {
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assert( ideal_Opcode() == Op_AddP, "expected base ptr here" );
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assert( idx == 1, "expected base ptr here" );
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// debug info can be anywhere
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return *Compile::current()->matcher()->idealreg2spillmask[Op_RegP];
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}
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uint opcnt = 1; // First operand
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uint num_edges = _opnds[1]->num_edges(); // leaves for first operand
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while( idx >= skipped+num_edges ) {
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skipped += num_edges;
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opcnt++; // Bump operand count
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assert( opcnt < numopnds, "Accessing non-existent operand" );
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num_edges = _opnds[opcnt]->num_edges(); // leaves for next operand
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}
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const RegMask *rm = cisc_RegMask();
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if( rm == NULL || (int)opcnt != cisc_operand() ) {
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rm = _opnds[opcnt]->in_RegMask(idx-skipped);
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}
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return *rm;
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}
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//-----------------------------memory_inputs--------------------------------
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const MachOper* MachNode::memory_inputs(Node* &base, Node* &index) const {
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const MachOper* oper = memory_operand();
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if (oper == (MachOper*)-1) {
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base = NodeSentinel;
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index = NodeSentinel;
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} else {
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base = NULL;
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index = NULL;
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if (oper != NULL) {
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// It has a unique memory operand. Find its index.
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int oper_idx = num_opnds();
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while (--oper_idx >= 0) {
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if (_opnds[oper_idx] == oper) break;
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}
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int oper_pos = operand_index(oper_idx);
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int base_pos = oper->base_position();
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if (base_pos >= 0) {
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base = _in[oper_pos+base_pos];
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}
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int index_pos = oper->index_position();
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if (index_pos >= 0) {
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index = _in[oper_pos+index_pos];
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}
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}
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}
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return oper;
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}
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//-----------------------------get_base_and_disp----------------------------
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const Node* MachNode::get_base_and_disp(intptr_t &offset, const TypePtr* &adr_type) const {
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// Find the memory inputs using our helper function
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Node* base;
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Node* index;
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const MachOper* oper = memory_inputs(base, index);
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if (oper == NULL) {
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// Base has been set to NULL
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offset = 0;
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} else if (oper == (MachOper*)-1) {
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// Base has been set to NodeSentinel
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// There is not a unique memory use here. We will fall to AliasIdxBot.
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offset = Type::OffsetBot;
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} else {
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// Base may be NULL, even if offset turns out to be != 0
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intptr_t disp = oper->constant_disp();
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int scale = oper->scale();
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// Now we have collected every part of the ADLC MEMORY_INTER.
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// See if it adds up to a base + offset.
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if (index != NULL) {
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const Type* t_index = index->bottom_type();
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if (t_index->isa_narrowoop() || t_index->isa_narrowklass()) { // EncodeN, LoadN, LoadConN, LoadNKlass,
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// EncodeNKlass, LoadConNklass.
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// Memory references through narrow oops have a
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// funny base so grab the type from the index:
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// [R12 + narrow_oop_reg<<3 + offset]
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assert(base == NULL, "Memory references through narrow oops have no base");
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offset = disp;
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adr_type = t_index->make_ptr()->add_offset(offset);
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return NULL;
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} else if (!index->is_Con()) {
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disp = Type::OffsetBot;
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} else if (disp != Type::OffsetBot) {
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const TypeX* ti = t_index->isa_intptr_t();
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if (ti == NULL) {
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disp = Type::OffsetBot; // a random constant??
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} else {
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disp += ti->get_con() << scale;
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}
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}
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}
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offset = disp;
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// In x86_32.ad, indOffset32X uses base==RegI and disp==RegP,
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// this will prevent alias analysis without the following support:
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// Lookup the TypePtr used by indOffset32X, a compile-time constant oop,
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// Add the offset determined by the "base", or use Type::OffsetBot.
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if( adr_type == TYPE_PTR_SENTINAL ) {
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const TypePtr *t_disp = oper->disp_as_type(); // only !NULL for indOffset32X
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if (t_disp != NULL) {
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offset = Type::OffsetBot;
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const Type* t_base = base->bottom_type();
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if (t_base->isa_intptr_t()) {
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const TypeX *t_offset = t_base->is_intptr_t();
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if( t_offset->is_con() ) {
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offset = t_offset->get_con();
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}
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}
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adr_type = t_disp->add_offset(offset);
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} else if( base == NULL && offset != 0 && offset != Type::OffsetBot ) {
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// Use ideal type if it is oop ptr.
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const TypePtr *tp = oper->type()->isa_ptr();
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if( tp != NULL) {
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adr_type = tp;
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}
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}
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}
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}
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return base;
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}
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//---------------------------------adr_type---------------------------------
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const class TypePtr *MachNode::adr_type() const {
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intptr_t offset = 0;
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const TypePtr *adr_type = TYPE_PTR_SENTINAL; // attempt computing adr_type
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const Node *base = get_base_and_disp(offset, adr_type);
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if( adr_type != TYPE_PTR_SENTINAL ) {
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return adr_type; // get_base_and_disp has the answer
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}
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// Direct addressing modes have no base node, simply an indirect
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// offset, which is always to raw memory.
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// %%%%% Someday we'd like to allow constant oop offsets which
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// would let Intel load from static globals in 1 instruction.
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// Currently Intel requires 2 instructions and a register temp.
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if (base == NULL) {
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// NULL base, zero offset means no memory at all (a null pointer!)
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if (offset == 0) {
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return NULL;
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}
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// NULL base, any offset means any pointer whatever
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if (offset == Type::OffsetBot) {
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return TypePtr::BOTTOM;
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}
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// %%% make offset be intptr_t
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assert(!Universe::heap()->is_in(cast_to_oop(offset)), "must be a raw ptr");
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return TypeRawPtr::BOTTOM;
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}
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// base of -1 with no particular offset means all of memory
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if (base == NodeSentinel) return TypePtr::BOTTOM;
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const Type* t = base->bottom_type();
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if (t->isa_narrowoop() && CompressedOops::shift() == 0) {
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// 32-bit unscaled narrow oop can be the base of any address expression
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t = t->make_ptr();
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}
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if (t->isa_narrowklass() && CompressedKlassPointers::shift() == 0) {
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// 32-bit unscaled narrow oop can be the base of any address expression
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t = t->make_ptr();
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}
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if (t->isa_intptr_t() && offset != 0 && offset != Type::OffsetBot) {
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// We cannot assert that the offset does not look oop-ish here.
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// Depending on the heap layout the cardmark base could land
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// inside some oopish region. It definitely does for Win2K.
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// The sum of cardmark-base plus shift-by-9-oop lands outside
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// the oop-ish area but we can't assert for that statically.
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return TypeRawPtr::BOTTOM;
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}
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const TypePtr *tp = t->isa_ptr();
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// be conservative if we do not recognize the type
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if (tp == NULL) {
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assert(false, "this path may produce not optimal code");
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return TypePtr::BOTTOM;
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}
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assert(tp->base() != Type::AnyPtr, "not a bare pointer");
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return tp->add_offset(offset);
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}
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//-----------------------------operand_index---------------------------------
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int MachNode::operand_index(uint operand) const {
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if (operand < 1) return -1;
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assert(operand < num_opnds(), "oob");
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if (_opnds[operand]->num_edges() == 0) return -1;
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uint skipped = oper_input_base(); // Sum of leaves skipped so far
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for (uint opcnt = 1; opcnt < operand; opcnt++) {
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uint num_edges = _opnds[opcnt]->num_edges(); // leaves for operand
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skipped += num_edges;
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}
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return skipped;
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}
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int MachNode::operand_index(const MachOper *oper) const {
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uint skipped = oper_input_base(); // Sum of leaves skipped so far
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uint opcnt;
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for (opcnt = 1; opcnt < num_opnds(); opcnt++) {
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if (_opnds[opcnt] == oper) break;
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uint num_edges = _opnds[opcnt]->num_edges(); // leaves for operand
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skipped += num_edges;
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}
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if (_opnds[opcnt] != oper) return -1;
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return skipped;
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}
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int MachNode::operand_index(Node* def) const {
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uint skipped = oper_input_base(); // Sum of leaves skipped so far
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for (uint opcnt = 1; opcnt < num_opnds(); opcnt++) {
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uint num_edges = _opnds[opcnt]->num_edges(); // leaves for operand
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for (uint i = 0; i < num_edges; i++) {
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if (in(skipped + i) == def) {
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return opcnt;
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}
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}
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skipped += num_edges;
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}
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return -1;
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}
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//------------------------------peephole---------------------------------------
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// Apply peephole rule(s) to this instruction
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MachNode *MachNode::peephole(Block *block, int block_index, PhaseRegAlloc *ra_, int &deleted) {
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return NULL;
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}
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//------------------------------add_case_label---------------------------------
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// Adds the label for the case
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void MachNode::add_case_label( int index_num, Label* blockLabel) {
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ShouldNotCallThis();
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}
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//------------------------------method_set-------------------------------------
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// Set the absolute address of a method
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void MachNode::method_set( intptr_t addr ) {
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ShouldNotCallThis();
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}
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//------------------------------rematerialize----------------------------------
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bool MachNode::rematerialize() const {
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// Temps are always rematerializable
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if (is_MachTemp()) return true;
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uint r = rule(); // Match rule
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if (r < Matcher::_begin_rematerialize ||
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r >= Matcher::_end_rematerialize) {
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return false;
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}
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// For 2-address instructions, the input live range is also the output
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// live range. Remateralizing does not make progress on the that live range.
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if (two_adr()) return false;
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// Check for rematerializing float constants, or not
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if (!Matcher::rematerialize_float_constants) {
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int op = ideal_Opcode();
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if (op == Op_ConF || op == Op_ConD) {
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return false;
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}
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}
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// Defining flags - can't spill these! Must remateralize.
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if (ideal_reg() == Op_RegFlags) {
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return true;
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}
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// Stretching lots of inputs - don't do it.
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if (req() > 2) {
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return false;
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}
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if (req() == 2 && in(1) && in(1)->ideal_reg() == Op_RegFlags) {
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// In(1) will be rematerialized, too.
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// Stretching lots of inputs - don't do it.
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if (in(1)->req() > 2) {
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return false;
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}
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}
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// Don't remateralize somebody with bound inputs - it stretches a
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// fixed register lifetime.
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uint idx = oper_input_base();
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|
if (req() > idx) {
|
|
const RegMask &rm = in_RegMask(idx);
|
|
if (rm.is_bound(ideal_reg())) {
|
|
return false;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
#ifndef PRODUCT
|
|
//------------------------------dump_spec--------------------------------------
|
|
// Print any per-operand special info
|
|
void MachNode::dump_spec(outputStream *st) const {
|
|
uint cnt = num_opnds();
|
|
for( uint i=0; i<cnt; i++ ) {
|
|
if (_opnds[i] != NULL) {
|
|
_opnds[i]->dump_spec(st);
|
|
} else {
|
|
st->print(" _");
|
|
}
|
|
}
|
|
const TypePtr *t = adr_type();
|
|
if( t ) {
|
|
Compile* C = Compile::current();
|
|
if( C->alias_type(t)->is_volatile() )
|
|
st->print(" Volatile!");
|
|
}
|
|
}
|
|
|
|
//------------------------------dump_format------------------------------------
|
|
// access to virtual
|
|
void MachNode::dump_format(PhaseRegAlloc *ra, outputStream *st) const {
|
|
format(ra, st); // access to virtual
|
|
}
|
|
#endif
|
|
|
|
//=============================================================================
|
|
#ifndef PRODUCT
|
|
void MachTypeNode::dump_spec(outputStream *st) const {
|
|
if (_bottom_type != NULL) {
|
|
_bottom_type->dump_on(st);
|
|
} else {
|
|
st->print(" NULL");
|
|
}
|
|
}
|
|
#endif
|
|
|
|
|
|
//=============================================================================
|
|
int MachConstantNode::constant_offset() {
|
|
// Bind the offset lazily.
|
|
if (_constant.offset() == -1) {
|
|
ConstantTable& constant_table = Compile::current()->output()->constant_table();
|
|
int offset = constant_table.find_offset(_constant);
|
|
// If called from Compile::scratch_emit_size return the
|
|
// pre-calculated offset.
|
|
// NOTE: If the AD file does some table base offset optimizations
|
|
// later the AD file needs to take care of this fact.
|
|
if (Compile::current()->output()->in_scratch_emit_size()) {
|
|
return constant_table.calculate_table_base_offset() + offset;
|
|
}
|
|
_constant.set_offset(constant_table.table_base_offset() + offset);
|
|
}
|
|
return _constant.offset();
|
|
}
|
|
|
|
int MachConstantNode::constant_offset_unchecked() const {
|
|
return _constant.offset();
|
|
}
|
|
|
|
//=============================================================================
|
|
#ifndef PRODUCT
|
|
void MachNullCheckNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
|
|
int reg = ra_->get_reg_first(in(1)->in(_vidx));
|
|
st->print("%s %s", Name(), Matcher::regName[reg]);
|
|
}
|
|
#endif
|
|
|
|
void MachNullCheckNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
|
|
// only emits entries in the null-pointer exception handler table
|
|
}
|
|
void MachNullCheckNode::label_set(Label* label, uint block_num) {
|
|
// Nothing to emit
|
|
}
|
|
void MachNullCheckNode::save_label( Label** label, uint* block_num ) {
|
|
// Nothing to emit
|
|
}
|
|
|
|
const RegMask &MachNullCheckNode::in_RegMask( uint idx ) const {
|
|
if( idx == 0 ) return RegMask::Empty;
|
|
else return in(1)->as_Mach()->out_RegMask();
|
|
}
|
|
|
|
//=============================================================================
|
|
const Type *MachProjNode::bottom_type() const {
|
|
if( _ideal_reg == fat_proj ) return Type::BOTTOM;
|
|
// Try the normal mechanism first
|
|
const Type *t = in(0)->bottom_type();
|
|
if( t->base() == Type::Tuple ) {
|
|
const TypeTuple *tt = t->is_tuple();
|
|
if (_con < tt->cnt())
|
|
return tt->field_at(_con);
|
|
}
|
|
// Else use generic type from ideal register set
|
|
assert((uint)_ideal_reg < (uint)_last_machine_leaf && Type::mreg2type[_ideal_reg], "in bounds");
|
|
return Type::mreg2type[_ideal_reg];
|
|
}
|
|
|
|
const TypePtr *MachProjNode::adr_type() const {
|
|
if (bottom_type() == Type::MEMORY) {
|
|
// in(0) might be a narrow MemBar; otherwise we will report TypePtr::BOTTOM
|
|
Node* ctrl = in(0);
|
|
if (ctrl == NULL) return NULL; // node is dead
|
|
const TypePtr* adr_type = ctrl->adr_type();
|
|
#ifdef ASSERT
|
|
if (!VMError::is_error_reported() && !Node::in_dump())
|
|
assert(adr_type != NULL, "source must have adr_type");
|
|
#endif
|
|
return adr_type;
|
|
}
|
|
assert(bottom_type()->base() != Type::Memory, "no other memories?");
|
|
return NULL;
|
|
}
|
|
|
|
#ifndef PRODUCT
|
|
void MachProjNode::dump_spec(outputStream *st) const {
|
|
ProjNode::dump_spec(st);
|
|
switch (_ideal_reg) {
|
|
case unmatched_proj: st->print("/unmatched"); break;
|
|
case fat_proj: st->print("/fat"); if (WizardMode) _rout.dump(st); break;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
//=============================================================================
|
|
#ifndef PRODUCT
|
|
void MachIfNode::dump_spec(outputStream *st) const {
|
|
st->print("P=%f, C=%f",_prob, _fcnt);
|
|
}
|
|
#endif
|
|
|
|
//=============================================================================
|
|
uint MachReturnNode::size_of() const { return sizeof(*this); }
|
|
|
|
//------------------------------Registers--------------------------------------
|
|
const RegMask &MachReturnNode::in_RegMask( uint idx ) const {
|
|
return _in_rms[idx];
|
|
}
|
|
|
|
const TypePtr *MachReturnNode::adr_type() const {
|
|
// most returns and calls are assumed to consume & modify all of memory
|
|
// the matcher will copy non-wide adr_types from ideal originals
|
|
return _adr_type;
|
|
}
|
|
|
|
//=============================================================================
|
|
const Type *MachSafePointNode::bottom_type() const { return TypeTuple::MEMBAR; }
|
|
|
|
//------------------------------Registers--------------------------------------
|
|
const RegMask &MachSafePointNode::in_RegMask( uint idx ) const {
|
|
// Values in the domain use the users calling convention, embodied in the
|
|
// _in_rms array of RegMasks.
|
|
if( idx < TypeFunc::Parms ) return _in_rms[idx];
|
|
|
|
if (idx == TypeFunc::Parms &&
|
|
ideal_Opcode() == Op_SafePoint) {
|
|
return MachNode::in_RegMask(idx);
|
|
}
|
|
|
|
// Values outside the domain represent debug info
|
|
assert(in(idx)->ideal_reg() != Op_RegFlags, "flags register is not spillable");
|
|
return *Compile::current()->matcher()->idealreg2spillmask[in(idx)->ideal_reg()];
|
|
}
|
|
|
|
|
|
//=============================================================================
|
|
|
|
bool MachCallNode::cmp( const Node &n ) const
|
|
{ return _tf == ((MachCallNode&)n)._tf; }
|
|
const Type *MachCallNode::bottom_type() const { return tf()->range(); }
|
|
const Type* MachCallNode::Value(PhaseGVN* phase) const { return tf()->range(); }
|
|
|
|
#ifndef PRODUCT
|
|
void MachCallNode::dump_spec(outputStream *st) const {
|
|
st->print("# ");
|
|
if (tf() != NULL) tf()->dump_on(st);
|
|
if (_cnt != COUNT_UNKNOWN) st->print(" C=%f",_cnt);
|
|
if (jvms() != NULL) jvms()->dump_spec(st);
|
|
}
|
|
#endif
|
|
|
|
bool MachCallNode::return_value_is_used() const {
|
|
if (tf()->range()->cnt() == TypeFunc::Parms) {
|
|
// void return
|
|
return false;
|
|
}
|
|
|
|
// find the projection corresponding to the return value
|
|
for (DUIterator_Fast imax, i = fast_outs(imax); i < imax; i++) {
|
|
Node *use = fast_out(i);
|
|
if (!use->is_Proj()) continue;
|
|
if (use->as_Proj()->_con == TypeFunc::Parms) {
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
// Similar to cousin class CallNode::returns_pointer
|
|
// Because this is used in deoptimization, we want the type info, not the data
|
|
// flow info; the interpreter will "use" things that are dead to the optimizer.
|
|
bool MachCallNode::returns_pointer() const {
|
|
const TypeTuple *r = tf()->range();
|
|
return (r->cnt() > TypeFunc::Parms &&
|
|
r->field_at(TypeFunc::Parms)->isa_ptr());
|
|
}
|
|
|
|
//------------------------------Registers--------------------------------------
|
|
const RegMask &MachCallNode::in_RegMask(uint idx) const {
|
|
// Values in the domain use the users calling convention, embodied in the
|
|
// _in_rms array of RegMasks.
|
|
if (idx < tf()->domain()->cnt()) {
|
|
return _in_rms[idx];
|
|
}
|
|
if (idx == mach_constant_base_node_input()) {
|
|
return MachConstantBaseNode::static_out_RegMask();
|
|
}
|
|
// Values outside the domain represent debug info
|
|
return *Compile::current()->matcher()->idealreg2debugmask[in(idx)->ideal_reg()];
|
|
}
|
|
|
|
//=============================================================================
|
|
uint MachCallJavaNode::size_of() const { return sizeof(*this); }
|
|
bool MachCallJavaNode::cmp( const Node &n ) const {
|
|
MachCallJavaNode &call = (MachCallJavaNode&)n;
|
|
return MachCallNode::cmp(call) && _method->equals(call._method) &&
|
|
_override_symbolic_info == call._override_symbolic_info;
|
|
}
|
|
#ifndef PRODUCT
|
|
void MachCallJavaNode::dump_spec(outputStream *st) const {
|
|
if (_method_handle_invoke)
|
|
st->print("MethodHandle ");
|
|
if (_method) {
|
|
_method->print_short_name(st);
|
|
st->print(" ");
|
|
}
|
|
MachCallNode::dump_spec(st);
|
|
}
|
|
#endif
|
|
|
|
//------------------------------Registers--------------------------------------
|
|
const RegMask &MachCallJavaNode::in_RegMask(uint idx) const {
|
|
// Values in the domain use the users calling convention, embodied in the
|
|
// _in_rms array of RegMasks.
|
|
if (idx < tf()->domain()->cnt()) {
|
|
return _in_rms[idx];
|
|
}
|
|
if (idx == mach_constant_base_node_input()) {
|
|
return MachConstantBaseNode::static_out_RegMask();
|
|
}
|
|
// Values outside the domain represent debug info
|
|
Matcher* m = Compile::current()->matcher();
|
|
// If this call is a MethodHandle invoke we have to use a different
|
|
// debugmask which does not include the register we use to save the
|
|
// SP over MH invokes.
|
|
RegMask** debugmask = _method_handle_invoke ? m->idealreg2mhdebugmask : m->idealreg2debugmask;
|
|
return *debugmask[in(idx)->ideal_reg()];
|
|
}
|
|
|
|
//=============================================================================
|
|
uint MachCallStaticJavaNode::size_of() const { return sizeof(*this); }
|
|
bool MachCallStaticJavaNode::cmp( const Node &n ) const {
|
|
MachCallStaticJavaNode &call = (MachCallStaticJavaNode&)n;
|
|
return MachCallJavaNode::cmp(call) && _name == call._name;
|
|
}
|
|
|
|
//----------------------------uncommon_trap_request----------------------------
|
|
// If this is an uncommon trap, return the request code, else zero.
|
|
int MachCallStaticJavaNode::uncommon_trap_request() const {
|
|
if (_name != NULL && !strcmp(_name, "uncommon_trap")) {
|
|
return CallStaticJavaNode::extract_uncommon_trap_request(this);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
#ifndef PRODUCT
|
|
// Helper for summarizing uncommon_trap arguments.
|
|
void MachCallStaticJavaNode::dump_trap_args(outputStream *st) const {
|
|
int trap_req = uncommon_trap_request();
|
|
if (trap_req != 0) {
|
|
char buf[100];
|
|
st->print("(%s)",
|
|
Deoptimization::format_trap_request(buf, sizeof(buf),
|
|
trap_req));
|
|
}
|
|
}
|
|
|
|
void MachCallStaticJavaNode::dump_spec(outputStream *st) const {
|
|
st->print("Static ");
|
|
if (_name != NULL) {
|
|
st->print("wrapper for: %s", _name );
|
|
dump_trap_args(st);
|
|
st->print(" ");
|
|
}
|
|
MachCallJavaNode::dump_spec(st);
|
|
}
|
|
#endif
|
|
|
|
//=============================================================================
|
|
#ifndef PRODUCT
|
|
void MachCallDynamicJavaNode::dump_spec(outputStream *st) const {
|
|
st->print("Dynamic ");
|
|
MachCallJavaNode::dump_spec(st);
|
|
}
|
|
#endif
|
|
//=============================================================================
|
|
uint MachCallRuntimeNode::size_of() const { return sizeof(*this); }
|
|
bool MachCallRuntimeNode::cmp( const Node &n ) const {
|
|
MachCallRuntimeNode &call = (MachCallRuntimeNode&)n;
|
|
return MachCallNode::cmp(call) && !strcmp(_name,call._name);
|
|
}
|
|
#ifndef PRODUCT
|
|
void MachCallRuntimeNode::dump_spec(outputStream *st) const {
|
|
st->print("%s ",_name);
|
|
MachCallNode::dump_spec(st);
|
|
}
|
|
#endif
|
|
//=============================================================================
|
|
uint MachCallNativeNode::size_of() const { return sizeof(*this); }
|
|
bool MachCallNativeNode::cmp( const Node &n ) const {
|
|
MachCallNativeNode &call = (MachCallNativeNode&)n;
|
|
return MachCallNode::cmp(call) && !strcmp(_name,call._name)
|
|
&& _arg_regs == call._arg_regs && _ret_regs == call._ret_regs;
|
|
}
|
|
#ifndef PRODUCT
|
|
void MachCallNativeNode::dump_spec(outputStream *st) const {
|
|
st->print("%s ",_name);
|
|
st->print("_arg_regs: ");
|
|
CallNativeNode::print_regs(_arg_regs, st);
|
|
st->print("_ret_regs: ");
|
|
CallNativeNode::print_regs(_ret_regs, st);
|
|
MachCallNode::dump_spec(st);
|
|
}
|
|
#endif
|
|
//=============================================================================
|
|
// A shared JVMState for all HaltNodes. Indicates the start of debug info
|
|
// is at TypeFunc::Parms. Only required for SOE register spill handling -
|
|
// to indicate where the stack-slot-only debug info inputs begin.
|
|
// There is no other JVM state needed here.
|
|
JVMState jvms_for_throw(0);
|
|
JVMState *MachHaltNode::jvms() const {
|
|
return &jvms_for_throw;
|
|
}
|
|
|
|
uint MachMemBarNode::size_of() const { return sizeof(*this); }
|
|
|
|
const TypePtr *MachMemBarNode::adr_type() const {
|
|
return _adr_type;
|
|
}
|
|
|
|
|
|
//=============================================================================
|
|
#ifndef PRODUCT
|
|
void labelOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
|
|
st->print("B%d", _block_num);
|
|
}
|
|
#endif // PRODUCT
|
|
|
|
//=============================================================================
|
|
#ifndef PRODUCT
|
|
void methodOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
|
|
st->print(INTPTR_FORMAT, _method);
|
|
}
|
|
#endif // PRODUCT
|