1443 lines
105 KiB
C
1443 lines
105 KiB
C
// BEGIN Generated code -- do not edit
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// Generated by aarch64-asmtest.py
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Label back, forth;
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__ bind(back);
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// ArithOp
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__ add(r26, r23, r13, Assembler::LSL, 32); // add x26, x23, x13, LSL #32
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__ sub(r12, r24, r9, Assembler::LSR, 37); // sub x12, x24, x9, LSR #37
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__ adds(r28, r15, r8, Assembler::ASR, 39); // adds x28, x15, x8, ASR #39
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__ subs(r7, r28, r30, Assembler::ASR, 57); // subs x7, x28, x30, ASR #57
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__ addw(r9, r22, r27, Assembler::ASR, 15); // add w9, w22, w27, ASR #15
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__ subw(r3, r13, r17, Assembler::ASR, 30); // sub w3, w13, w17, ASR #30
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__ addsw(r14, r26, r8, Assembler::ASR, 17); // adds w14, w26, w8, ASR #17
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__ subsw(r0, r22, r12, Assembler::ASR, 21); // subs w0, w22, w12, ASR #21
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__ andr(r0, r15, r26, Assembler::LSL, 20); // and x0, x15, x26, LSL #20
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__ orr(r26, r5, r17, Assembler::LSL, 61); // orr x26, x5, x17, LSL #61
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__ eor(r24, r13, r2, Assembler::LSL, 32); // eor x24, x13, x2, LSL #32
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__ ands(r28, r3, r17, Assembler::ASR, 35); // ands x28, x3, x17, ASR #35
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__ andw(r25, r16, r29, Assembler::LSR, 18); // and w25, w16, w29, LSR #18
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__ orrw(r13, r17, r11, Assembler::LSR, 9); // orr w13, w17, w11, LSR #9
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__ eorw(r5, r5, r17, Assembler::LSR, 15); // eor w5, w5, w17, LSR #15
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__ andsw(r2, r23, r27, Assembler::ASR, 26); // ands w2, w23, w27, ASR #26
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__ bic(r27, r28, r16, Assembler::LSR, 45); // bic x27, x28, x16, LSR #45
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__ orn(r8, r25, r26, Assembler::ASR, 37); // orn x8, x25, x26, ASR #37
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__ eon(r29, r17, r13, Assembler::LSR, 63); // eon x29, x17, x13, LSR #63
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__ bics(r28, r24, r2, Assembler::LSR, 31); // bics x28, x24, x2, LSR #31
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__ bicw(r19, r26, r7, Assembler::ASR, 3); // bic w19, w26, w7, ASR #3
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__ ornw(r6, r24, r10, Assembler::ASR, 3); // orn w6, w24, w10, ASR #3
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__ eonw(r4, r21, r1, Assembler::LSR, 29); // eon w4, w21, w1, LSR #29
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__ bicsw(r16, r21, r0, Assembler::LSR, 19); // bics w16, w21, w0, LSR #19
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// AddSubImmOp
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__ addw(r17, r12, 379u); // add w17, w12, #379
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__ addsw(r30, r1, 22u); // adds w30, w1, #22
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__ subw(r29, r5, 126u); // sub w29, w5, #126
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__ subsw(r6, r24, 960u); // subs w6, w24, #960
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__ add(r0, r13, 104u); // add x0, x13, #104
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__ adds(r8, r6, 663u); // adds x8, x6, #663
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__ sub(r10, r5, 516u); // sub x10, x5, #516
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__ subs(r1, r3, 1012u); // subs x1, x3, #1012
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// LogicalImmOp
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__ andw(r6, r11, 4294049777ull); // and w6, w11, #0xfff1fff1
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__ orrw(r28, r5, 4294966791ull); // orr w28, w5, #0xfffffe07
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__ eorw(r1, r20, 134217216ull); // eor w1, w20, #0x7fffe00
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__ andsw(r7, r17, 1048576ull); // ands w7, w17, #0x100000
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__ andr(r14, r12, 9223372036854775808ull); // and x14, x12, #0x8000000000000000
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__ orr(r9, r11, 562675075514368ull); // orr x9, x11, #0x1ffc000000000
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__ eor(r17, r0, 18014398509481728ull); // eor x17, x0, #0x3fffffffffff00
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__ ands(r1, r8, 18446744073705357315ull); // ands x1, x8, #0xffffffffffc00003
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// AbsOp
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__ b(__ pc()); // b .
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__ b(back); // b back
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__ b(forth); // b forth
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__ bl(__ pc()); // bl .
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__ bl(back); // bl back
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__ bl(forth); // bl forth
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// RegAndAbsOp
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__ cbzw(r10, __ pc()); // cbz w10, .
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__ cbzw(r10, back); // cbz w10, back
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__ cbzw(r10, forth); // cbz w10, forth
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__ cbnzw(r8, __ pc()); // cbnz w8, .
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__ cbnzw(r8, back); // cbnz w8, back
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__ cbnzw(r8, forth); // cbnz w8, forth
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__ cbz(r11, __ pc()); // cbz x11, .
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__ cbz(r11, back); // cbz x11, back
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__ cbz(r11, forth); // cbz x11, forth
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__ cbnz(r29, __ pc()); // cbnz x29, .
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__ cbnz(r29, back); // cbnz x29, back
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__ cbnz(r29, forth); // cbnz x29, forth
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__ adr(r19, __ pc()); // adr x19, .
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__ adr(r19, back); // adr x19, back
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__ adr(r19, forth); // adr x19, forth
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__ _adrp(r19, __ pc()); // adrp x19, .
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// RegImmAbsOp
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__ tbz(r22, 6, __ pc()); // tbz x22, #6, .
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__ tbz(r22, 6, back); // tbz x22, #6, back
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__ tbz(r22, 6, forth); // tbz x22, #6, forth
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__ tbnz(r12, 11, __ pc()); // tbnz x12, #11, .
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__ tbnz(r12, 11, back); // tbnz x12, #11, back
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__ tbnz(r12, 11, forth); // tbnz x12, #11, forth
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// MoveWideImmOp
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__ movnw(r0, 6301, 0); // movn w0, #6301, lsl 0
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__ movzw(r7, 20886, 0); // movz w7, #20886, lsl 0
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__ movkw(r27, 18617, 0); // movk w27, #18617, lsl 0
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__ movn(r12, 22998, 16); // movn x12, #22998, lsl 16
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__ movz(r20, 1532, 16); // movz x20, #1532, lsl 16
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__ movk(r8, 5167, 32); // movk x8, #5167, lsl 32
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// BitfieldOp
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__ sbfm(r15, r17, 24, 28); // sbfm x15, x17, #24, #28
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__ bfmw(r15, r9, 14, 25); // bfm w15, w9, #14, #25
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__ ubfmw(r27, r25, 6, 31); // ubfm w27, w25, #6, #31
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__ sbfm(r19, r2, 23, 31); // sbfm x19, x2, #23, #31
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__ bfm(r12, r21, 10, 6); // bfm x12, x21, #10, #6
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__ ubfm(r22, r0, 26, 16); // ubfm x22, x0, #26, #16
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// ExtractOp
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__ extrw(r3, r3, r20, 27); // extr w3, w3, w20, #27
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__ extr(r8, r30, r3, 54); // extr x8, x30, x3, #54
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// CondBranchOp
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__ br(Assembler::EQ, __ pc()); // b.EQ .
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__ br(Assembler::EQ, back); // b.EQ back
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__ br(Assembler::EQ, forth); // b.EQ forth
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__ br(Assembler::NE, __ pc()); // b.NE .
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__ br(Assembler::NE, back); // b.NE back
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__ br(Assembler::NE, forth); // b.NE forth
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__ br(Assembler::HS, __ pc()); // b.HS .
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__ br(Assembler::HS, back); // b.HS back
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__ br(Assembler::HS, forth); // b.HS forth
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__ br(Assembler::CS, __ pc()); // b.CS .
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__ br(Assembler::CS, back); // b.CS back
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__ br(Assembler::CS, forth); // b.CS forth
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__ br(Assembler::LO, __ pc()); // b.LO .
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__ br(Assembler::LO, back); // b.LO back
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__ br(Assembler::LO, forth); // b.LO forth
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__ br(Assembler::CC, __ pc()); // b.CC .
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__ br(Assembler::CC, back); // b.CC back
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__ br(Assembler::CC, forth); // b.CC forth
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__ br(Assembler::MI, __ pc()); // b.MI .
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__ br(Assembler::MI, back); // b.MI back
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__ br(Assembler::MI, forth); // b.MI forth
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__ br(Assembler::PL, __ pc()); // b.PL .
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__ br(Assembler::PL, back); // b.PL back
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__ br(Assembler::PL, forth); // b.PL forth
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__ br(Assembler::VS, __ pc()); // b.VS .
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__ br(Assembler::VS, back); // b.VS back
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__ br(Assembler::VS, forth); // b.VS forth
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__ br(Assembler::VC, __ pc()); // b.VC .
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__ br(Assembler::VC, back); // b.VC back
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__ br(Assembler::VC, forth); // b.VC forth
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__ br(Assembler::HI, __ pc()); // b.HI .
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__ br(Assembler::HI, back); // b.HI back
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__ br(Assembler::HI, forth); // b.HI forth
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__ br(Assembler::LS, __ pc()); // b.LS .
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__ br(Assembler::LS, back); // b.LS back
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__ br(Assembler::LS, forth); // b.LS forth
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__ br(Assembler::GE, __ pc()); // b.GE .
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__ br(Assembler::GE, back); // b.GE back
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__ br(Assembler::GE, forth); // b.GE forth
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__ br(Assembler::LT, __ pc()); // b.LT .
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__ br(Assembler::LT, back); // b.LT back
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__ br(Assembler::LT, forth); // b.LT forth
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__ br(Assembler::GT, __ pc()); // b.GT .
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__ br(Assembler::GT, back); // b.GT back
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__ br(Assembler::GT, forth); // b.GT forth
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__ br(Assembler::LE, __ pc()); // b.LE .
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__ br(Assembler::LE, back); // b.LE back
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__ br(Assembler::LE, forth); // b.LE forth
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__ br(Assembler::AL, __ pc()); // b.AL .
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__ br(Assembler::AL, back); // b.AL back
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__ br(Assembler::AL, forth); // b.AL forth
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__ br(Assembler::NV, __ pc()); // b.NV .
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__ br(Assembler::NV, back); // b.NV back
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__ br(Assembler::NV, forth); // b.NV forth
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// ImmOp
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__ svc(12999); // svc #12999
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__ hvc(2665); // hvc #2665
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__ smc(9002); // smc #9002
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__ brk(14843); // brk #14843
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__ hlt(25964); // hlt #25964
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// Op
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__ nop(); // nop
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__ yield(); // yield
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__ wfe(); // wfe
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__ sev(); // sev
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__ sevl(); // sevl
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__ autia1716(); // autia1716
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__ autiasp(); // autiasp
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__ autiaz(); // autiaz
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__ autib1716(); // autib1716
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__ autibsp(); // autibsp
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__ autibz(); // autibz
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__ pacia1716(); // pacia1716
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__ paciasp(); // paciasp
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__ paciaz(); // paciaz
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__ pacib1716(); // pacib1716
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__ pacibsp(); // pacibsp
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__ pacibz(); // pacibz
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__ eret(); // eret
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__ drps(); // drps
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__ isb(); // isb
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// PostfixExceptionOp
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__ wfi(); // wfi
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__ xpaclri(); // xpaclri
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// SystemOp
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__ dsb(Assembler::ST); // dsb ST
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__ dmb(Assembler::OSHST); // dmb OSHST
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// OneRegOp
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__ br(r16); // br x16
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__ blr(r20); // blr x20
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__ paciza(r10); // paciza x10
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__ pacizb(r27); // pacizb x27
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__ pacdza(r8); // pacdza x8
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__ pacdzb(r0); // pacdzb x0
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__ autiza(r1); // autiza x1
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__ autizb(r21); // autizb x21
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__ autdza(r17); // autdza x17
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__ autdzb(r29); // autdzb x29
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__ xpacd(r29); // xpacd x29
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__ braaz(r28); // braaz x28
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__ brabz(r1); // brabz x1
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__ blraaz(r23); // blraaz x23
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__ blrabz(r21); // blrabz x21
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// PostfixExceptionOneRegOp
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__ xpaci(r20); // xpaci x20
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// LoadStoreExclusiveOp
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__ stxr(r22, r27, r19); // stxr w22, x27, [x19]
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__ stlxr(r11, r16, r6); // stlxr w11, x16, [x6]
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__ ldxr(r17, r0); // ldxr x17, [x0]
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__ ldaxr(r4, r10); // ldaxr x4, [x10]
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__ stlr(r24, r22); // stlr x24, [x22]
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__ ldar(r10, r19); // ldar x10, [x19]
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// LoadStoreExclusiveOp
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__ stxrw(r1, r5, r30); // stxr w1, w5, [x30]
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__ stlxrw(r8, r12, r17); // stlxr w8, w12, [x17]
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__ ldxrw(r9, r14); // ldxr w9, [x14]
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__ ldaxrw(r7, r1); // ldaxr w7, [x1]
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__ stlrw(r5, r16); // stlr w5, [x16]
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__ ldarw(r2, r12); // ldar w2, [x12]
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// LoadStoreExclusiveOp
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__ stxrh(r10, r12, r3); // stxrh w10, w12, [x3]
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__ stlxrh(r28, r14, r26); // stlxrh w28, w14, [x26]
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__ ldxrh(r30, r10); // ldxrh w30, [x10]
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__ ldaxrh(r14, r21); // ldaxrh w14, [x21]
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__ stlrh(r13, r9); // stlrh w13, [x9]
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__ ldarh(r22, r27); // ldarh w22, [x27]
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// LoadStoreExclusiveOp
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__ stxrb(r28, r19, r11); // stxrb w28, w19, [x11]
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__ stlxrb(r30, r19, r2); // stlxrb w30, w19, [x2]
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__ ldxrb(r2, r23); // ldxrb w2, [x23]
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__ ldaxrb(r1, r0); // ldaxrb w1, [x0]
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__ stlrb(r12, r16); // stlrb w12, [x16]
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__ ldarb(r13, r15); // ldarb w13, [x15]
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// LoadStoreExclusiveOp
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__ ldxp(r17, r21, r13); // ldxp x17, x21, [x13]
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__ ldaxp(r11, r30, r8); // ldaxp x11, x30, [x8]
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__ stxp(r24, r13, r11, r1); // stxp w24, x13, x11, [x1]
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__ stlxp(r26, r21, r27, r13); // stlxp w26, x21, x27, [x13]
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// LoadStoreExclusiveOp
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__ ldxpw(r20, r3, r12); // ldxp w20, w3, [x12]
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__ ldaxpw(r6, r1, r29); // ldaxp w6, w1, [x29]
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__ stxpw(r6, r4, r11, r16); // stxp w6, w4, w11, [x16]
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__ stlxpw(r4, r30, r12, r21); // stlxp w4, w30, w12, [x21]
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// base_plus_unscaled_offset
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// LoadStoreOp
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__ str(r6, Address(r27, 97)); // str x6, [x27, 97]
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__ strw(r17, Address(r10, 45)); // str w17, [x10, 45]
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__ strb(r26, Address(r22, -29)); // strb w26, [x22, -29]
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__ strh(r21, Address(r10, -50)); // strh w21, [x10, -50]
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__ ldr(r14, Address(r24, 125)); // ldr x14, [x24, 125]
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__ ldrw(r7, Address(r24, -16)); // ldr w7, [x24, -16]
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__ ldrb(r8, Address(r2, 13)); // ldrb w8, [x2, 13]
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__ ldrh(r30, Address(r25, -61)); // ldrh w30, [x25, -61]
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__ ldrsb(r3, Address(r12, -14)); // ldrsb x3, [x12, -14]
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__ ldrsh(r10, Address(r17, -28)); // ldrsh x10, [x17, -28]
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__ ldrshw(r21, Address(r3, -5)); // ldrsh w21, [x3, -5]
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__ ldrsw(r2, Address(r25, 23)); // ldrsw x2, [x25, 23]
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__ ldrd(v25, Address(r1, -69)); // ldr d25, [x1, -69]
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__ ldrs(v29, Address(r27, 6)); // ldr s29, [x27, 6]
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__ strd(v29, Address(r12, 41)); // str d29, [x12, 41]
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__ strs(v2, Address(r22, -115)); // str s2, [x22, -115]
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// pre
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// LoadStoreOp
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__ str(r26, Address(__ pre(r5, 3))); // str x26, [x5, 3]!
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__ strw(r20, Address(__ pre(r5, -103))); // str w20, [x5, -103]!
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__ strb(r8, Address(__ pre(r12, -25))); // strb w8, [x12, -25]!
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__ strh(r20, Address(__ pre(r2, -57))); // strh w20, [x2, -57]!
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__ ldr(r14, Address(__ pre(r29, -234))); // ldr x14, [x29, -234]!
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__ ldrw(r13, Address(__ pre(r29, 4))); // ldr w13, [x29, 4]!
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__ ldrb(r24, Address(__ pre(r19, -9))); // ldrb w24, [x19, -9]!
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__ ldrh(r3, Address(__ pre(r27, -19))); // ldrh w3, [x27, -19]!
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__ ldrsb(r17, Address(__ pre(r1, -5))); // ldrsb x17, [x1, -5]!
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__ ldrsh(r17, Address(__ pre(r19, -13))); // ldrsh x17, [x19, -13]!
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__ ldrshw(r21, Address(__ pre(r11, -26))); // ldrsh w21, [x11, -26]!
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__ ldrsw(r1, Address(__ pre(r9, -60))); // ldrsw x1, [x9, -60]!
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__ ldrd(v26, Address(__ pre(r23, -247))); // ldr d26, [x23, -247]!
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__ ldrs(v22, Address(__ pre(r21, -127))); // ldr s22, [x21, -127]!
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__ strd(v13, Address(__ pre(r7, -216))); // str d13, [x7, -216]!
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__ strs(v12, Address(__ pre(r13, -104))); // str s12, [x13, -104]!
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// post
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// LoadStoreOp
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__ str(r20, Address(__ post(r5, -237))); // str x20, [x5], -237
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__ strw(r29, Address(__ post(r28, -74))); // str w29, [x28], -74
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__ strb(r4, Address(__ post(r24, -22))); // strb w4, [x24], -22
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__ strh(r13, Address(__ post(r9, -21))); // strh w13, [x9], -21
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__ ldr(r26, Address(__ post(r7, -55))); // ldr x26, [x7], -55
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__ ldrw(r13, Address(__ post(r3, -115))); // ldr w13, [x3], -115
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__ ldrb(r1, Address(__ post(r5, 12))); // ldrb w1, [x5], 12
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__ ldrh(r8, Address(__ post(r13, -34))); // ldrh w8, [x13], -34
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__ ldrsb(r23, Address(__ post(r20, -27))); // ldrsb x23, [x20], -27
|
|
__ ldrsh(r20, Address(__ post(r6, -2))); // ldrsh x20, [x6], -2
|
|
__ ldrshw(r9, Address(__ post(r17, -42))); // ldrsh w9, [x17], -42
|
|
__ ldrsw(r21, Address(__ post(r6, -30))); // ldrsw x21, [x6], -30
|
|
__ ldrd(v16, Address(__ post(r22, -29))); // ldr d16, [x22], -29
|
|
__ ldrs(v9, Address(__ post(r11, -3))); // ldr s9, [x11], -3
|
|
__ strd(v22, Address(__ post(r26, 60))); // str d22, [x26], 60
|
|
__ strs(v16, Address(__ post(r29, -2))); // str s16, [x29], -2
|
|
|
|
// base_plus_reg
|
|
// LoadStoreOp
|
|
__ str(r1, Address(r22, r4, Address::sxtw(0))); // str x1, [x22, w4, sxtw #0]
|
|
__ strw(r23, Address(r30, r13, Address::lsl(2))); // str w23, [x30, x13, lsl #2]
|
|
__ strb(r12, Address(r11, r12, Address::uxtw(0))); // strb w12, [x11, w12, uxtw #0]
|
|
__ strh(r25, Address(r12, r0, Address::lsl(1))); // strh w25, [x12, x0, lsl #1]
|
|
__ ldr(r17, Address(r7, r0, Address::uxtw(3))); // ldr x17, [x7, w0, uxtw #3]
|
|
__ ldrw(r1, Address(r19, r14, Address::uxtw(2))); // ldr w1, [x19, w14, uxtw #2]
|
|
__ ldrb(r12, Address(r2, r9, Address::lsl(0))); // ldrb w12, [x2, x9, lsl #0]
|
|
__ ldrh(r22, Address(r9, r27, Address::sxtw(0))); // ldrh w22, [x9, w27, sxtw #0]
|
|
__ ldrsb(r21, Address(r12, r15, Address::sxtx(0))); // ldrsb x21, [x12, x15, sxtx #0]
|
|
__ ldrsh(r28, Address(r6, r16, Address::lsl(1))); // ldrsh x28, [x6, x16, lsl #1]
|
|
__ ldrshw(r25, Address(r17, r22, Address::sxtw(0))); // ldrsh w25, [x17, w22, sxtw #0]
|
|
__ ldrsw(r4, Address(r17, r29, Address::sxtx(0))); // ldrsw x4, [x17, x29, sxtx #0]
|
|
__ ldrd(v5, Address(r1, r3, Address::sxtx(3))); // ldr d5, [x1, x3, sxtx #3]
|
|
__ ldrs(v24, Address(r17, r13, Address::uxtw(2))); // ldr s24, [x17, w13, uxtw #2]
|
|
__ strd(v17, Address(r17, r23, Address::sxtx(3))); // str d17, [x17, x23, sxtx #3]
|
|
__ strs(v17, Address(r30, r5, Address::sxtw(2))); // str s17, [x30, w5, sxtw #2]
|
|
|
|
// base_plus_scaled_offset
|
|
// LoadStoreOp
|
|
__ str(r29, Address(r11, 14160)); // str x29, [x11, 14160]
|
|
__ strw(r28, Address(r21, 7752)); // str w28, [x21, 7752]
|
|
__ strb(r28, Address(r2, 1746)); // strb w28, [x2, 1746]
|
|
__ strh(r0, Address(r28, 3296)); // strh w0, [x28, 3296]
|
|
__ ldr(r25, Address(r7, 15408)); // ldr x25, [x7, 15408]
|
|
__ ldrw(r0, Address(r3, 6312)); // ldr w0, [x3, 6312]
|
|
__ ldrb(r30, Address(r5, 1992)); // ldrb w30, [x5, 1992]
|
|
__ ldrh(r14, Address(r23, 3194)); // ldrh w14, [x23, 3194]
|
|
__ ldrsb(r10, Address(r19, 1786)); // ldrsb x10, [x19, 1786]
|
|
__ ldrsh(r29, Address(r17, 3482)); // ldrsh x29, [x17, 3482]
|
|
__ ldrshw(r25, Address(r30, 3362)); // ldrsh w25, [x30, 3362]
|
|
__ ldrsw(r17, Address(r2, 7512)); // ldrsw x17, [x2, 7512]
|
|
__ ldrd(v15, Address(r16, 15176)); // ldr d15, [x16, 15176]
|
|
__ ldrs(v12, Address(r30, 6220)); // ldr s12, [x30, 6220]
|
|
__ strd(v1, Address(r1, 15216)); // str d1, [x1, 15216]
|
|
__ strs(v5, Address(r11, 7832)); // str s5, [x11, 7832]
|
|
|
|
// pcrel
|
|
// LoadStoreOp
|
|
__ ldr(r17, back); // ldr x17, back
|
|
__ ldrw(r2, back); // ldr w2, back
|
|
|
|
// LoadStoreOp
|
|
__ prfm(Address(r25, 111)); // prfm PLDL1KEEP, [x25, 111]
|
|
|
|
// LoadStoreOp
|
|
__ prfm(back); // prfm PLDL1KEEP, back
|
|
|
|
// LoadStoreOp
|
|
__ prfm(Address(r14, r27, Address::uxtw(0))); // prfm PLDL1KEEP, [x14, w27, uxtw #0]
|
|
|
|
// LoadStoreOp
|
|
__ prfm(Address(r14, 12328)); // prfm PLDL1KEEP, [x14, 12328]
|
|
|
|
// AddSubCarryOp
|
|
__ adcw(r0, r25, r15); // adc w0, w25, w15
|
|
__ adcsw(r1, r24, r3); // adcs w1, w24, w3
|
|
__ sbcw(r17, r24, r20); // sbc w17, w24, w20
|
|
__ sbcsw(r11, r0, r13); // sbcs w11, w0, w13
|
|
__ adc(r28, r10, r7); // adc x28, x10, x7
|
|
__ adcs(r4, r15, r16); // adcs x4, x15, x16
|
|
__ sbc(r2, r12, r20); // sbc x2, x12, x20
|
|
__ sbcs(r29, r13, r13); // sbcs x29, x13, x13
|
|
|
|
// AddSubExtendedOp
|
|
__ addw(r14, r6, r12, ext::uxtx, 3); // add w14, w6, w12, uxtx #3
|
|
__ addsw(r17, r25, r30, ext::uxtw, 4); // adds w17, w25, w30, uxtw #4
|
|
__ sub(r0, r17, r14, ext::uxtb, 1); // sub x0, x17, x14, uxtb #1
|
|
__ subsw(r9, r24, r29, ext::sxtx, 1); // subs w9, w24, w29, sxtx #1
|
|
__ add(r1, r22, r0, ext::sxtw, 2); // add x1, x22, x0, sxtw #2
|
|
__ adds(r12, r28, r22, ext::uxth, 3); // adds x12, x28, x22, uxth #3
|
|
__ sub(r10, r12, r17, ext::uxtw, 4); // sub x10, x12, x17, uxtw #4
|
|
__ subs(r15, r28, r10, ext::sxtw, 3); // subs x15, x28, x10, sxtw #3
|
|
|
|
// ConditionalCompareOp
|
|
__ ccmnw(r19, r23, 2u, Assembler::LE); // ccmn w19, w23, #2, LE
|
|
__ ccmpw(r17, r9, 6u, Assembler::LO); // ccmp w17, w9, #6, LO
|
|
__ ccmn(r21, r8, 2u, Assembler::CC); // ccmn x21, x8, #2, CC
|
|
__ ccmp(r19, r5, 1u, Assembler::MI); // ccmp x19, x5, #1, MI
|
|
|
|
// ConditionalCompareImmedOp
|
|
__ ccmnw(r22, 17, 12, Assembler::HI); // ccmn w22, #17, #12, HI
|
|
__ ccmpw(r17, 7, 3, Assembler::HS); // ccmp w17, #7, #3, HS
|
|
__ ccmn(r16, 28, 5, Assembler::LT); // ccmn x16, #28, #5, LT
|
|
__ ccmp(r22, 3, 5, Assembler::LS); // ccmp x22, #3, #5, LS
|
|
|
|
// ConditionalSelectOp
|
|
__ cselw(r29, r26, r12, Assembler::LT); // csel w29, w26, w12, LT
|
|
__ csincw(r27, r10, r15, Assembler::CC); // csinc w27, w10, w15, CC
|
|
__ csinvw(r21, r28, r30, Assembler::LS); // csinv w21, w28, w30, LS
|
|
__ csnegw(r9, r27, r30, Assembler::CC); // csneg w9, w27, w30, CC
|
|
__ csel(r29, r15, r29, Assembler::LE); // csel x29, x15, x29, LE
|
|
__ csinc(r25, r21, r4, Assembler::EQ); // csinc x25, x21, x4, EQ
|
|
__ csinv(r17, r21, r29, Assembler::VS); // csinv x17, x21, x29, VS
|
|
__ csneg(r21, r20, r6, Assembler::HI); // csneg x21, x20, x6, HI
|
|
|
|
// TwoRegOp
|
|
__ rbitw(r30, r3); // rbit w30, w3
|
|
__ rev16w(r21, r19); // rev16 w21, w19
|
|
__ revw(r11, r24); // rev w11, w24
|
|
__ clzw(r0, r27); // clz w0, w27
|
|
__ clsw(r25, r14); // cls w25, w14
|
|
__ rbit(r3, r14); // rbit x3, x14
|
|
__ rev16(r17, r7); // rev16 x17, x7
|
|
__ rev32(r15, r24); // rev32 x15, x24
|
|
__ rev(r28, r17); // rev x28, x17
|
|
__ clz(r25, r2); // clz x25, x2
|
|
__ cls(r26, r28); // cls x26, x28
|
|
__ pacia(r5, r25); // pacia x5, x25
|
|
__ pacib(r26, r27); // pacib x26, x27
|
|
__ pacda(r16, r17); // pacda x16, x17
|
|
__ pacdb(r6, r21); // pacdb x6, x21
|
|
__ autia(r12, r0); // autia x12, x0
|
|
__ autib(r4, r12); // autib x4, x12
|
|
__ autda(r27, r17); // autda x27, x17
|
|
__ autdb(r28, r28); // autdb x28, x28
|
|
__ braa(r2, r17); // braa x2, x17
|
|
__ brab(r10, r15); // brab x10, x15
|
|
__ blraa(r14, r14); // blraa x14, x14
|
|
__ blrab(r3, r25); // blrab x3, x25
|
|
|
|
// ThreeRegOp
|
|
__ udivw(r15, r19, r14); // udiv w15, w19, w14
|
|
__ sdivw(r5, r16, r4); // sdiv w5, w16, w4
|
|
__ lslvw(r26, r25, r4); // lslv w26, w25, w4
|
|
__ lsrvw(r2, r2, r12); // lsrv w2, w2, w12
|
|
__ asrvw(r29, r17, r8); // asrv w29, w17, w8
|
|
__ rorvw(r7, r3, r4); // rorv w7, w3, w4
|
|
__ udiv(r25, r4, r26); // udiv x25, x4, x26
|
|
__ sdiv(r25, r4, r17); // sdiv x25, x4, x17
|
|
__ lslv(r0, r26, r17); // lslv x0, x26, x17
|
|
__ lsrv(r23, r15, r21); // lsrv x23, x15, x21
|
|
__ asrv(r28, r17, r27); // asrv x28, x17, x27
|
|
__ rorv(r10, r3, r0); // rorv x10, x3, x0
|
|
__ umulh(r7, r25, r9); // umulh x7, x25, x9
|
|
__ smulh(r6, r15, r29); // smulh x6, x15, x29
|
|
|
|
// FourRegMulOp
|
|
__ maddw(r15, r10, r2, r17); // madd w15, w10, w2, w17
|
|
__ msubw(r7, r11, r11, r23); // msub w7, w11, w11, w23
|
|
__ madd(r7, r29, r23, r14); // madd x7, x29, x23, x14
|
|
__ msub(r27, r11, r11, r4); // msub x27, x11, x11, x4
|
|
__ smaddl(r24, r12, r15, r14); // smaddl x24, w12, w15, x14
|
|
__ smsubl(r20, r11, r28, r13); // smsubl x20, w11, w28, x13
|
|
__ umaddl(r11, r12, r23, r30); // umaddl x11, w12, w23, x30
|
|
__ umsubl(r26, r14, r9, r13); // umsubl x26, w14, w9, x13
|
|
|
|
// ThreeRegFloatOp
|
|
__ fabds(v10, v7, v5); // fabd s10, s7, s5
|
|
__ fmuls(v29, v15, v3); // fmul s29, s15, s3
|
|
__ fdivs(v11, v12, v15); // fdiv s11, s12, s15
|
|
__ fadds(v30, v30, v17); // fadd s30, s30, s17
|
|
__ fsubs(v19, v20, v15); // fsub s19, s20, s15
|
|
__ fabdd(v15, v9, v21); // fabd d15, d9, d21
|
|
__ fmuld(v2, v9, v27); // fmul d2, d9, d27
|
|
__ fdivd(v7, v29, v30); // fdiv d7, d29, d30
|
|
__ faddd(v17, v1, v2); // fadd d17, d1, d2
|
|
__ fsubd(v6, v10, v3); // fsub d6, d10, d3
|
|
|
|
// FourRegFloatOp
|
|
__ fmadds(v24, v11, v7, v1); // fmadd s24, s11, s7, s1
|
|
__ fmsubs(v11, v0, v3, v17); // fmsub s11, s0, s3, s17
|
|
__ fnmadds(v28, v6, v22, v6); // fnmadd s28, s6, s22, s6
|
|
__ fnmadds(v0, v27, v26, v2); // fnmadd s0, s27, s26, s2
|
|
__ fmaddd(v5, v7, v28, v11); // fmadd d5, d7, d28, d11
|
|
__ fmsubd(v25, v13, v11, v23); // fmsub d25, d13, d11, d23
|
|
__ fnmaddd(v19, v8, v17, v21); // fnmadd d19, d8, d17, d21
|
|
__ fnmaddd(v25, v20, v19, v17); // fnmadd d25, d20, d19, d17
|
|
|
|
// TwoRegFloatOp
|
|
__ fmovs(v2, v29); // fmov s2, s29
|
|
__ fabss(v22, v8); // fabs s22, s8
|
|
__ fnegs(v21, v19); // fneg s21, s19
|
|
__ fsqrts(v20, v11); // fsqrt s20, s11
|
|
__ fcvts(v17, v20); // fcvt d17, s20
|
|
__ fmovd(v6, v15); // fmov d6, d15
|
|
__ fabsd(v3, v3); // fabs d3, d3
|
|
__ fnegd(v28, v3); // fneg d28, d3
|
|
__ fsqrtd(v27, v14); // fsqrt d27, d14
|
|
__ fcvtd(v14, v10); // fcvt s14, d10
|
|
|
|
// FloatConvertOp
|
|
__ fcvtzsw(r12, v11); // fcvtzs w12, s11
|
|
__ fcvtzs(r17, v10); // fcvtzs x17, s10
|
|
__ fcvtzdw(r25, v7); // fcvtzs w25, d7
|
|
__ fcvtzd(r7, v14); // fcvtzs x7, d14
|
|
__ scvtfws(v28, r0); // scvtf s28, w0
|
|
__ scvtfs(v22, r0); // scvtf s22, x0
|
|
__ scvtfwd(v12, r23); // scvtf d12, w23
|
|
__ scvtfd(v13, r13); // scvtf d13, x13
|
|
__ fmovs(r7, v14); // fmov w7, s14
|
|
__ fmovd(r7, v8); // fmov x7, d8
|
|
__ fmovs(v20, r17); // fmov s20, w17
|
|
__ fmovd(v28, r30); // fmov d28, x30
|
|
|
|
// TwoRegFloatOp
|
|
__ fcmps(v16, v2); // fcmp s16, s2
|
|
__ fcmpd(v9, v16); // fcmp d9, d16
|
|
__ fcmps(v20, 0.0); // fcmp s20, #0.0
|
|
__ fcmpd(v29, 0.0); // fcmp d29, #0.0
|
|
|
|
// LoadStorePairOp
|
|
__ stpw(r1, r26, Address(r24, -208)); // stp w1, w26, [x24, #-208]
|
|
__ ldpw(r5, r11, Address(r12, 48)); // ldp w5, w11, [x12, #48]
|
|
__ ldpsw(r21, r15, Address(r27, 48)); // ldpsw x21, x15, [x27, #48]
|
|
__ stp(r5, r28, Address(r22, 32)); // stp x5, x28, [x22, #32]
|
|
__ ldp(r27, r17, Address(r19, -32)); // ldp x27, x17, [x19, #-32]
|
|
|
|
// LoadStorePairOp
|
|
__ stpw(r13, r7, Address(__ pre(r26, -176))); // stp w13, w7, [x26, #-176]!
|
|
__ ldpw(r13, r21, Address(__ pre(r6, -48))); // ldp w13, w21, [x6, #-48]!
|
|
__ ldpsw(r20, r30, Address(__ pre(r27, 16))); // ldpsw x20, x30, [x27, #16]!
|
|
__ stp(r21, r5, Address(__ pre(r10, -128))); // stp x21, x5, [x10, #-128]!
|
|
__ ldp(r14, r4, Address(__ pre(r23, -96))); // ldp x14, x4, [x23, #-96]!
|
|
|
|
// LoadStorePairOp
|
|
__ stpw(r29, r12, Address(__ post(r16, 32))); // stp w29, w12, [x16], #32
|
|
__ ldpw(r26, r17, Address(__ post(r27, 96))); // ldp w26, w17, [x27], #96
|
|
__ ldpsw(r4, r20, Address(__ post(r14, -96))); // ldpsw x4, x20, [x14], #-96
|
|
__ stp(r16, r2, Address(__ post(r14, -112))); // stp x16, x2, [x14], #-112
|
|
__ ldp(r23, r24, Address(__ post(r7, -256))); // ldp x23, x24, [x7], #-256
|
|
|
|
// LoadStorePairOp
|
|
__ stnpw(r0, r26, Address(r15, 128)); // stnp w0, w26, [x15, #128]
|
|
__ ldnpw(r26, r6, Address(r8, -208)); // ldnp w26, w6, [x8, #-208]
|
|
__ stnp(r15, r10, Address(r25, -112)); // stnp x15, x10, [x25, #-112]
|
|
__ ldnp(r16, r1, Address(r19, -160)); // ldnp x16, x1, [x19, #-160]
|
|
|
|
// LdStNEONOp
|
|
__ ld1(v27, __ T8B, Address(r30)); // ld1 {v27.8B}, [x30]
|
|
__ ld1(v25, v26, __ T16B, Address(__ post(r3, 32))); // ld1 {v25.16B, v26.16B}, [x3], 32
|
|
__ ld1(v30, v31, v0, __ T1D, Address(__ post(r16, r10))); // ld1 {v30.1D, v31.1D, v0.1D}, [x16], x10
|
|
__ ld1(v16, v17, v18, v19, __ T8H, Address(__ post(r19, 64))); // ld1 {v16.8H, v17.8H, v18.8H, v19.8H}, [x19], 64
|
|
__ ld1r(v23, __ T8B, Address(r24)); // ld1r {v23.8B}, [x24]
|
|
__ ld1r(v8, __ T4S, Address(__ post(r10, 4))); // ld1r {v8.4S}, [x10], 4
|
|
__ ld1r(v9, __ T1D, Address(__ post(r20, r23))); // ld1r {v9.1D}, [x20], x23
|
|
__ ld2(v2, v3, __ T2D, Address(r3)); // ld2 {v2.2D, v3.2D}, [x3]
|
|
__ ld2(v8, v9, __ T4H, Address(__ post(r30, 16))); // ld2 {v8.4H, v9.4H}, [x30], 16
|
|
__ ld2r(v4, v5, __ T16B, Address(r26)); // ld2r {v4.16B, v5.16B}, [x26]
|
|
__ ld2r(v3, v4, __ T2S, Address(__ post(r17, 8))); // ld2r {v3.2S, v4.2S}, [x17], 8
|
|
__ ld2r(v29, v30, __ T2D, Address(__ post(r11, r16))); // ld2r {v29.2D, v30.2D}, [x11], x16
|
|
__ ld3(v1, v2, v3, __ T4S, Address(__ post(r0, r23))); // ld3 {v1.4S, v2.4S, v3.4S}, [x0], x23
|
|
__ ld3(v0, v1, v2, __ T2S, Address(r21)); // ld3 {v0.2S, v1.2S, v2.2S}, [x21]
|
|
__ ld3r(v5, v6, v7, __ T8H, Address(r7)); // ld3r {v5.8H, v6.8H, v7.8H}, [x7]
|
|
__ ld3r(v1, v2, v3, __ T4S, Address(__ post(r7, 12))); // ld3r {v1.4S, v2.4S, v3.4S}, [x7], 12
|
|
__ ld3r(v2, v3, v4, __ T1D, Address(__ post(r5, r15))); // ld3r {v2.1D, v3.1D, v4.1D}, [x5], x15
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__ ld4(v27, v28, v29, v30, __ T8H, Address(__ post(r29, 64))); // ld4 {v27.8H, v28.8H, v29.8H, v30.8H}, [x29], 64
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__ ld4(v24, v25, v26, v27, __ T8B, Address(__ post(r4, r7))); // ld4 {v24.8B, v25.8B, v26.8B, v27.8B}, [x4], x7
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__ ld4r(v15, v16, v17, v18, __ T8B, Address(r23)); // ld4r {v15.8B, v16.8B, v17.8B, v18.8B}, [x23]
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__ ld4r(v14, v15, v16, v17, __ T4H, Address(__ post(r21, 8))); // ld4r {v14.4H, v15.4H, v16.4H, v17.4H}, [x21], 8
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__ ld4r(v20, v21, v22, v23, __ T2S, Address(__ post(r9, r25))); // ld4r {v20.2S, v21.2S, v22.2S, v23.2S}, [x9], x25
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// NEONReduceInstruction
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__ addv(v23, __ T8B, v24); // addv b23, v24.8B
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__ addv(v26, __ T16B, v27); // addv b26, v27.16B
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__ addv(v5, __ T4H, v6); // addv h5, v6.4H
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__ addv(v6, __ T8H, v7); // addv h6, v7.8H
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__ addv(v15, __ T4S, v16); // addv s15, v16.4S
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__ smaxv(v15, __ T8B, v16); // smaxv b15, v16.8B
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__ smaxv(v25, __ T16B, v26); // smaxv b25, v26.16B
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__ smaxv(v16, __ T4H, v17); // smaxv h16, v17.4H
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__ smaxv(v27, __ T8H, v28); // smaxv h27, v28.8H
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__ smaxv(v24, __ T4S, v25); // smaxv s24, v25.4S
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__ fmaxv(v15, __ T4S, v16); // fmaxv s15, v16.4S
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__ sminv(v25, __ T8B, v26); // sminv b25, v26.8B
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__ uminv(v14, __ T8B, v15); // uminv b14, v15.8B
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__ sminv(v10, __ T16B, v11); // sminv b10, v11.16B
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__ uminv(v13, __ T16B, v14); // uminv b13, v14.16B
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__ sminv(v14, __ T4H, v15); // sminv h14, v15.4H
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__ uminv(v20, __ T4H, v21); // uminv h20, v21.4H
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__ sminv(v1, __ T8H, v2); // sminv h1, v2.8H
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__ uminv(v22, __ T8H, v23); // uminv h22, v23.8H
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__ sminv(v30, __ T4S, v31); // sminv s30, v31.4S
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__ uminv(v14, __ T4S, v15); // uminv s14, v15.4S
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__ fminv(v2, __ T4S, v3); // fminv s2, v3.4S
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__ fmaxp(v6, v7, __ S); // fmaxp s6, v7.2S
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__ fmaxp(v3, v4, __ D); // fmaxp d3, v4.2D
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__ fminp(v7, v8, __ S); // fminp s7, v8.2S
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__ fminp(v24, v25, __ D); // fminp d24, v25.2D
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// TwoRegNEONOp
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__ absr(v0, __ T8B, v1); // abs v0.8B, v1.8B
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__ absr(v27, __ T16B, v28); // abs v27.16B, v28.16B
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__ absr(v29, __ T4H, v30); // abs v29.4H, v30.4H
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__ absr(v5, __ T8H, v6); // abs v5.8H, v6.8H
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__ absr(v5, __ T2S, v6); // abs v5.2S, v6.2S
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__ absr(v29, __ T4S, v30); // abs v29.4S, v30.4S
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__ absr(v11, __ T2D, v12); // abs v11.2D, v12.2D
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__ fabs(v25, __ T2S, v26); // fabs v25.2S, v26.2S
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__ fabs(v0, __ T4S, v1); // fabs v0.4S, v1.4S
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__ fabs(v30, __ T2D, v31); // fabs v30.2D, v31.2D
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__ fneg(v0, __ T2S, v1); // fneg v0.2S, v1.2S
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__ fneg(v17, __ T4S, v18); // fneg v17.4S, v18.4S
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__ fneg(v28, __ T2D, v29); // fneg v28.2D, v29.2D
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__ fsqrt(v25, __ T2S, v26); // fsqrt v25.2S, v26.2S
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__ fsqrt(v9, __ T4S, v10); // fsqrt v9.4S, v10.4S
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__ fsqrt(v25, __ T2D, v26); // fsqrt v25.2D, v26.2D
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__ notr(v12, __ T8B, v13); // not v12.8B, v13.8B
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__ notr(v15, __ T16B, v16); // not v15.16B, v16.16B
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// ThreeRegNEONOp
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__ andr(v11, __ T8B, v12, v13); // and v11.8B, v12.8B, v13.8B
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__ andr(v10, __ T16B, v11, v12); // and v10.16B, v11.16B, v12.16B
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__ orr(v17, __ T8B, v18, v19); // orr v17.8B, v18.8B, v19.8B
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__ orr(v24, __ T16B, v25, v26); // orr v24.16B, v25.16B, v26.16B
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__ eor(v21, __ T8B, v22, v23); // eor v21.8B, v22.8B, v23.8B
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__ eor(v23, __ T16B, v24, v25); // eor v23.16B, v24.16B, v25.16B
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__ addv(v0, __ T8B, v1, v2); // add v0.8B, v1.8B, v2.8B
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__ addv(v16, __ T16B, v17, v18); // add v16.16B, v17.16B, v18.16B
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__ addv(v10, __ T4H, v11, v12); // add v10.4H, v11.4H, v12.4H
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__ addv(v6, __ T8H, v7, v8); // add v6.8H, v7.8H, v8.8H
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__ addv(v28, __ T2S, v29, v30); // add v28.2S, v29.2S, v30.2S
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__ addv(v6, __ T4S, v7, v8); // add v6.4S, v7.4S, v8.4S
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__ addv(v5, __ T2D, v6, v7); // add v5.2D, v6.2D, v7.2D
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__ fadd(v5, __ T2S, v6, v7); // fadd v5.2S, v6.2S, v7.2S
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__ fadd(v20, __ T4S, v21, v22); // fadd v20.4S, v21.4S, v22.4S
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__ fadd(v17, __ T2D, v18, v19); // fadd v17.2D, v18.2D, v19.2D
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__ subv(v15, __ T8B, v16, v17); // sub v15.8B, v16.8B, v17.8B
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__ subv(v17, __ T16B, v18, v19); // sub v17.16B, v18.16B, v19.16B
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__ subv(v29, __ T4H, v30, v31); // sub v29.4H, v30.4H, v31.4H
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__ subv(v26, __ T8H, v27, v28); // sub v26.8H, v27.8H, v28.8H
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__ subv(v28, __ T2S, v29, v30); // sub v28.2S, v29.2S, v30.2S
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__ subv(v1, __ T4S, v2, v3); // sub v1.4S, v2.4S, v3.4S
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__ subv(v27, __ T2D, v28, v29); // sub v27.2D, v28.2D, v29.2D
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__ fsub(v0, __ T2S, v1, v2); // fsub v0.2S, v1.2S, v2.2S
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__ fsub(v20, __ T4S, v21, v22); // fsub v20.4S, v21.4S, v22.4S
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__ fsub(v28, __ T2D, v29, v30); // fsub v28.2D, v29.2D, v30.2D
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__ mulv(v15, __ T8B, v16, v17); // mul v15.8B, v16.8B, v17.8B
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__ mulv(v12, __ T16B, v13, v14); // mul v12.16B, v13.16B, v14.16B
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__ mulv(v10, __ T4H, v11, v12); // mul v10.4H, v11.4H, v12.4H
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__ mulv(v28, __ T8H, v29, v30); // mul v28.8H, v29.8H, v30.8H
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__ mulv(v28, __ T2S, v29, v30); // mul v28.2S, v29.2S, v30.2S
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__ mulv(v19, __ T4S, v20, v21); // mul v19.4S, v20.4S, v21.4S
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__ fabd(v22, __ T2S, v23, v24); // fabd v22.2S, v23.2S, v24.2S
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__ fabd(v10, __ T4S, v11, v12); // fabd v10.4S, v11.4S, v12.4S
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__ fabd(v4, __ T2D, v5, v6); // fabd v4.2D, v5.2D, v6.2D
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__ fmul(v30, __ T2S, v31, v0); // fmul v30.2S, v31.2S, v0.2S
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__ fmul(v20, __ T4S, v21, v22); // fmul v20.4S, v21.4S, v22.4S
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__ fmul(v8, __ T2D, v9, v10); // fmul v8.2D, v9.2D, v10.2D
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__ mlav(v30, __ T4H, v31, v0); // mla v30.4H, v31.4H, v0.4H
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__ mlav(v17, __ T8H, v18, v19); // mla v17.8H, v18.8H, v19.8H
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__ mlav(v10, __ T2S, v11, v12); // mla v10.2S, v11.2S, v12.2S
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__ mlav(v27, __ T4S, v28, v29); // mla v27.4S, v28.4S, v29.4S
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__ fmla(v2, __ T2S, v3, v4); // fmla v2.2S, v3.2S, v4.2S
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__ fmla(v24, __ T4S, v25, v26); // fmla v24.4S, v25.4S, v26.4S
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__ fmla(v4, __ T2D, v5, v6); // fmla v4.2D, v5.2D, v6.2D
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__ mlsv(v3, __ T4H, v4, v5); // mls v3.4H, v4.4H, v5.4H
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__ mlsv(v8, __ T8H, v9, v10); // mls v8.8H, v9.8H, v10.8H
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__ mlsv(v22, __ T2S, v23, v24); // mls v22.2S, v23.2S, v24.2S
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__ mlsv(v17, __ T4S, v18, v19); // mls v17.4S, v18.4S, v19.4S
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__ fmls(v13, __ T2S, v14, v15); // fmls v13.2S, v14.2S, v15.2S
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__ fmls(v4, __ T4S, v5, v6); // fmls v4.4S, v5.4S, v6.4S
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__ fmls(v28, __ T2D, v29, v30); // fmls v28.2D, v29.2D, v30.2D
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__ fdiv(v23, __ T2S, v24, v25); // fdiv v23.2S, v24.2S, v25.2S
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__ fdiv(v21, __ T4S, v22, v23); // fdiv v21.4S, v22.4S, v23.4S
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__ fdiv(v25, __ T2D, v26, v27); // fdiv v25.2D, v26.2D, v27.2D
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__ maxv(v24, __ T8B, v25, v26); // smax v24.8B, v25.8B, v26.8B
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__ maxv(v3, __ T16B, v4, v5); // smax v3.16B, v4.16B, v5.16B
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__ maxv(v23, __ T4H, v24, v25); // smax v23.4H, v24.4H, v25.4H
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__ maxv(v26, __ T8H, v27, v28); // smax v26.8H, v27.8H, v28.8H
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__ maxv(v23, __ T2S, v24, v25); // smax v23.2S, v24.2S, v25.2S
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__ maxv(v14, __ T4S, v15, v16); // smax v14.4S, v15.4S, v16.4S
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__ smaxp(v21, __ T8B, v22, v23); // smaxp v21.8B, v22.8B, v23.8B
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__ smaxp(v3, __ T16B, v4, v5); // smaxp v3.16B, v4.16B, v5.16B
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__ smaxp(v23, __ T4H, v24, v25); // smaxp v23.4H, v24.4H, v25.4H
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__ smaxp(v8, __ T8H, v9, v10); // smaxp v8.8H, v9.8H, v10.8H
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__ smaxp(v24, __ T2S, v25, v26); // smaxp v24.2S, v25.2S, v26.2S
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__ smaxp(v19, __ T4S, v20, v21); // smaxp v19.4S, v20.4S, v21.4S
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__ fmax(v15, __ T2S, v16, v17); // fmax v15.2S, v16.2S, v17.2S
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__ fmax(v16, __ T4S, v17, v18); // fmax v16.4S, v17.4S, v18.4S
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__ fmax(v2, __ T2D, v3, v4); // fmax v2.2D, v3.2D, v4.2D
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__ minv(v1, __ T8B, v2, v3); // smin v1.8B, v2.8B, v3.8B
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__ minv(v0, __ T16B, v1, v2); // smin v0.16B, v1.16B, v2.16B
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__ minv(v24, __ T4H, v25, v26); // smin v24.4H, v25.4H, v26.4H
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__ minv(v4, __ T8H, v5, v6); // smin v4.8H, v5.8H, v6.8H
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__ minv(v3, __ T2S, v4, v5); // smin v3.2S, v4.2S, v5.2S
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__ minv(v11, __ T4S, v12, v13); // smin v11.4S, v12.4S, v13.4S
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__ sminp(v30, __ T8B, v31, v0); // sminp v30.8B, v31.8B, v0.8B
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__ sminp(v27, __ T16B, v28, v29); // sminp v27.16B, v28.16B, v29.16B
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__ sminp(v9, __ T4H, v10, v11); // sminp v9.4H, v10.4H, v11.4H
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__ sminp(v25, __ T8H, v26, v27); // sminp v25.8H, v26.8H, v27.8H
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__ sminp(v2, __ T2S, v3, v4); // sminp v2.2S, v3.2S, v4.2S
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__ sminp(v12, __ T4S, v13, v14); // sminp v12.4S, v13.4S, v14.4S
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__ fmin(v17, __ T2S, v18, v19); // fmin v17.2S, v18.2S, v19.2S
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__ fmin(v30, __ T4S, v31, v0); // fmin v30.4S, v31.4S, v0.4S
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__ fmin(v1, __ T2D, v2, v3); // fmin v1.2D, v2.2D, v3.2D
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__ cmeq(v12, __ T8B, v13, v14); // cmeq v12.8B, v13.8B, v14.8B
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__ cmeq(v28, __ T16B, v29, v30); // cmeq v28.16B, v29.16B, v30.16B
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__ cmeq(v0, __ T4H, v1, v2); // cmeq v0.4H, v1.4H, v2.4H
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__ cmeq(v17, __ T8H, v18, v19); // cmeq v17.8H, v18.8H, v19.8H
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__ cmeq(v12, __ T2S, v13, v14); // cmeq v12.2S, v13.2S, v14.2S
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__ cmeq(v17, __ T4S, v18, v19); // cmeq v17.4S, v18.4S, v19.4S
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__ cmeq(v21, __ T2D, v22, v23); // cmeq v21.2D, v22.2D, v23.2D
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__ fcmeq(v12, __ T2S, v13, v14); // fcmeq v12.2S, v13.2S, v14.2S
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__ fcmeq(v27, __ T4S, v28, v29); // fcmeq v27.4S, v28.4S, v29.4S
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__ fcmeq(v29, __ T2D, v30, v31); // fcmeq v29.2D, v30.2D, v31.2D
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__ cmgt(v30, __ T8B, v31, v0); // cmgt v30.8B, v31.8B, v0.8B
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__ cmgt(v1, __ T16B, v2, v3); // cmgt v1.16B, v2.16B, v3.16B
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__ cmgt(v25, __ T4H, v26, v27); // cmgt v25.4H, v26.4H, v27.4H
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__ cmgt(v27, __ T8H, v28, v29); // cmgt v27.8H, v28.8H, v29.8H
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__ cmgt(v4, __ T2S, v5, v6); // cmgt v4.2S, v5.2S, v6.2S
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__ cmgt(v29, __ T4S, v30, v31); // cmgt v29.4S, v30.4S, v31.4S
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__ cmgt(v3, __ T2D, v4, v5); // cmgt v3.2D, v4.2D, v5.2D
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__ cmhi(v6, __ T8B, v7, v8); // cmhi v6.8B, v7.8B, v8.8B
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__ cmhi(v29, __ T16B, v30, v31); // cmhi v29.16B, v30.16B, v31.16B
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__ cmhi(v25, __ T4H, v26, v27); // cmhi v25.4H, v26.4H, v27.4H
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__ cmhi(v17, __ T8H, v18, v19); // cmhi v17.8H, v18.8H, v19.8H
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__ cmhi(v8, __ T2S, v9, v10); // cmhi v8.2S, v9.2S, v10.2S
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|
__ cmhi(v7, __ T4S, v8, v9); // cmhi v7.4S, v8.4S, v9.4S
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|
__ cmhi(v12, __ T2D, v13, v14); // cmhi v12.2D, v13.2D, v14.2D
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|
__ cmhs(v0, __ T8B, v1, v2); // cmhs v0.8B, v1.8B, v2.8B
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|
__ cmhs(v19, __ T16B, v20, v21); // cmhs v19.16B, v20.16B, v21.16B
|
|
__ cmhs(v1, __ T4H, v2, v3); // cmhs v1.4H, v2.4H, v3.4H
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|
__ cmhs(v23, __ T8H, v24, v25); // cmhs v23.8H, v24.8H, v25.8H
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|
__ cmhs(v2, __ T2S, v3, v4); // cmhs v2.2S, v3.2S, v4.2S
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|
__ cmhs(v0, __ T4S, v1, v2); // cmhs v0.4S, v1.4S, v2.4S
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|
__ cmhs(v8, __ T2D, v9, v10); // cmhs v8.2D, v9.2D, v10.2D
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|
__ fcmgt(v23, __ T2S, v24, v25); // fcmgt v23.2S, v24.2S, v25.2S
|
|
__ fcmgt(v25, __ T4S, v26, v27); // fcmgt v25.4S, v26.4S, v27.4S
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|
__ fcmgt(v15, __ T2D, v16, v17); // fcmgt v15.2D, v16.2D, v17.2D
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|
__ cmge(v29, __ T8B, v30, v31); // cmge v29.8B, v30.8B, v31.8B
|
|
__ cmge(v3, __ T16B, v4, v5); // cmge v3.16B, v4.16B, v5.16B
|
|
__ cmge(v10, __ T4H, v11, v12); // cmge v10.4H, v11.4H, v12.4H
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|
__ cmge(v22, __ T8H, v23, v24); // cmge v22.8H, v23.8H, v24.8H
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|
__ cmge(v10, __ T2S, v11, v12); // cmge v10.2S, v11.2S, v12.2S
|
|
__ cmge(v4, __ T4S, v5, v6); // cmge v4.4S, v5.4S, v6.4S
|
|
__ cmge(v17, __ T2D, v18, v19); // cmge v17.2D, v18.2D, v19.2D
|
|
__ fcmge(v1, __ T2S, v2, v3); // fcmge v1.2S, v2.2S, v3.2S
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|
__ fcmge(v11, __ T4S, v12, v13); // fcmge v11.4S, v12.4S, v13.4S
|
|
__ fcmge(v7, __ T2D, v8, v9); // fcmge v7.2D, v8.2D, v9.2D
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|
|
|
// SpecialCases
|
|
__ ccmn(zr, zr, 3u, Assembler::LE); // ccmn xzr, xzr, #3, LE
|
|
__ ccmnw(zr, zr, 5u, Assembler::EQ); // ccmn wzr, wzr, #5, EQ
|
|
__ ccmp(zr, 1, 4u, Assembler::NE); // ccmp xzr, 1, #4, NE
|
|
__ ccmpw(zr, 2, 2, Assembler::GT); // ccmp wzr, 2, #2, GT
|
|
__ extr(zr, zr, zr, 0); // extr xzr, xzr, xzr, 0
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__ stlxp(r0, zr, zr, sp); // stlxp w0, xzr, xzr, [sp]
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|
__ stlxpw(r2, zr, zr, r3); // stlxp w2, wzr, wzr, [x3]
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|
__ stxp(r4, zr, zr, r5); // stxp w4, xzr, xzr, [x5]
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|
__ stxpw(r6, zr, zr, sp); // stxp w6, wzr, wzr, [sp]
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|
__ dup(v0, __ T16B, zr); // dup v0.16b, wzr
|
|
__ dup(v0, __ S, v1); // dup s0, v1.s[0]
|
|
__ mov(v1, __ D, 0, zr); // mov v1.d[0], xzr
|
|
__ mov(v1, __ S, 1, zr); // mov v1.s[1], wzr
|
|
__ mov(v1, __ H, 2, zr); // mov v1.h[2], wzr
|
|
__ mov(v1, __ B, 3, zr); // mov v1.b[3], wzr
|
|
__ smov(r0, v1, __ S, 0); // smov x0, v1.s[0]
|
|
__ smov(r0, v1, __ H, 1); // smov x0, v1.h[1]
|
|
__ smov(r0, v1, __ B, 2); // smov x0, v1.b[2]
|
|
__ umov(r0, v1, __ D, 0); // umov x0, v1.d[0]
|
|
__ umov(r0, v1, __ S, 1); // umov w0, v1.s[1]
|
|
__ umov(r0, v1, __ H, 2); // umov w0, v1.h[2]
|
|
__ umov(r0, v1, __ B, 3); // umov w0, v1.b[3]
|
|
__ fmovhid(r0, v1); // fmov x0, v1.d[1]
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|
__ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); // ld1 {v31.2d, v0.2d}, [x1], x0
|
|
__ fcvtzs(v0, __ T4S, v1); // fcvtzs v0.4s, v1.4s
|
|
__ sve_cpy(z0, __ S, p0, v1); // mov z0.s, p0/m, s1
|
|
__ sve_cpy(z0, __ B, p0, 127, true); // mov z0.b, p0/m, 127
|
|
__ sve_cpy(z1, __ H, p0, -128, true); // mov z1.h, p0/m, -128
|
|
__ sve_cpy(z2, __ S, p0, 32512, true); // mov z2.s, p0/m, 32512
|
|
__ sve_cpy(z5, __ D, p0, -32768, false); // mov z5.d, p0/z, -32768
|
|
__ sve_cpy(z10, __ B, p0, -1, false); // mov z10.b, p0/z, -1
|
|
__ sve_cpy(z11, __ S, p0, -1, false); // mov z11.s, p0/z, -1
|
|
__ sve_inc(r0, __ S); // incw x0
|
|
__ sve_dec(r1, __ H); // dech x1
|
|
__ sve_lsl(z0, __ B, z1, 7); // lsl z0.b, z1.b, #7
|
|
__ sve_lsl(z21, __ H, z1, 15); // lsl z21.h, z1.h, #15
|
|
__ sve_lsl(z0, __ S, z1, 31); // lsl z0.s, z1.s, #31
|
|
__ sve_lsl(z0, __ D, z1, 63); // lsl z0.d, z1.d, #63
|
|
__ sve_lsr(z0, __ B, z1, 7); // lsr z0.b, z1.b, #7
|
|
__ sve_asr(z0, __ H, z11, 15); // asr z0.h, z11.h, #15
|
|
__ sve_lsr(z30, __ S, z1, 31); // lsr z30.s, z1.s, #31
|
|
__ sve_asr(z0, __ D, z1, 63); // asr z0.d, z1.d, #63
|
|
__ sve_lsl(z0, __ B, p0, 0); // lsl z0.b, p0/m, z0.b, #0
|
|
__ sve_lsl(z0, __ B, p0, 5); // lsl z0.b, p0/m, z0.b, #5
|
|
__ sve_lsl(z1, __ H, p1, 15); // lsl z1.h, p1/m, z1.h, #15
|
|
__ sve_lsl(z2, __ S, p2, 31); // lsl z2.s, p2/m, z2.s, #31
|
|
__ sve_lsl(z3, __ D, p3, 63); // lsl z3.d, p3/m, z3.d, #63
|
|
__ sve_lsr(z0, __ B, p0, 1); // lsr z0.b, p0/m, z0.b, #1
|
|
__ sve_lsr(z0, __ B, p0, 8); // lsr z0.b, p0/m, z0.b, #8
|
|
__ sve_lsr(z1, __ H, p1, 15); // lsr z1.h, p1/m, z1.h, #15
|
|
__ sve_lsr(z2, __ S, p2, 7); // lsr z2.s, p2/m, z2.s, #7
|
|
__ sve_lsr(z2, __ S, p2, 31); // lsr z2.s, p2/m, z2.s, #31
|
|
__ sve_lsr(z3, __ D, p3, 63); // lsr z3.d, p3/m, z3.d, #63
|
|
__ sve_asr(z0, __ B, p0, 1); // asr z0.b, p0/m, z0.b, #1
|
|
__ sve_asr(z0, __ B, p0, 7); // asr z0.b, p0/m, z0.b, #7
|
|
__ sve_asr(z1, __ H, p1, 5); // asr z1.h, p1/m, z1.h, #5
|
|
__ sve_asr(z1, __ H, p1, 15); // asr z1.h, p1/m, z1.h, #15
|
|
__ sve_asr(z2, __ S, p2, 31); // asr z2.s, p2/m, z2.s, #31
|
|
__ sve_asr(z3, __ D, p3, 63); // asr z3.d, p3/m, z3.d, #63
|
|
__ sve_addvl(sp, r0, 31); // addvl sp, x0, #31
|
|
__ sve_addpl(r1, sp, -32); // addpl x1, sp, -32
|
|
__ sve_cntp(r8, __ B, p0, p1); // cntp x8, p0, p1.b
|
|
__ sve_dup(z0, __ B, 127); // dup z0.b, 127
|
|
__ sve_dup(z1, __ H, -128); // dup z1.h, -128
|
|
__ sve_dup(z2, __ S, 32512); // dup z2.s, 32512
|
|
__ sve_dup(z7, __ D, -32768); // dup z7.d, -32768
|
|
__ sve_dup(z10, __ B, -1); // dup z10.b, -1
|
|
__ sve_dup(z11, __ S, -1); // dup z11.s, -1
|
|
__ sve_ld1b(z0, __ B, p0, Address(sp)); // ld1b {z0.b}, p0/z, [sp]
|
|
__ sve_ld1b(z0, __ H, p1, Address(sp)); // ld1b {z0.h}, p1/z, [sp]
|
|
__ sve_ld1b(z0, __ S, p2, Address(sp, r8)); // ld1b {z0.s}, p2/z, [sp, x8]
|
|
__ sve_ld1b(z0, __ D, p3, Address(sp, 7)); // ld1b {z0.d}, p3/z, [sp, #7, MUL VL]
|
|
__ sve_ld1h(z10, __ H, p1, Address(sp, -8)); // ld1h {z10.h}, p1/z, [sp, #-8, MUL VL]
|
|
__ sve_ld1w(z20, __ S, p2, Address(r0, 7)); // ld1w {z20.s}, p2/z, [x0, #7, MUL VL]
|
|
__ sve_ld1b(z30, __ B, p3, Address(sp, r8)); // ld1b {z30.b}, p3/z, [sp, x8]
|
|
__ sve_ld1w(z0, __ S, p4, Address(sp, r28)); // ld1w {z0.s}, p4/z, [sp, x28, LSL #2]
|
|
__ sve_ld1d(z11, __ D, p5, Address(r0, r1)); // ld1d {z11.d}, p5/z, [x0, x1, LSL #3]
|
|
__ sve_st1b(z22, __ B, p6, Address(sp)); // st1b {z22.b}, p6, [sp]
|
|
__ sve_st1b(z31, __ B, p7, Address(sp, -8)); // st1b {z31.b}, p7, [sp, #-8, MUL VL]
|
|
__ sve_st1b(z0, __ H, p1, Address(sp)); // st1b {z0.h}, p1, [sp]
|
|
__ sve_st1b(z0, __ S, p2, Address(sp, r8)); // st1b {z0.s}, p2, [sp, x8]
|
|
__ sve_st1b(z0, __ D, p3, Address(sp)); // st1b {z0.d}, p3, [sp]
|
|
__ sve_st1w(z0, __ S, p1, Address(r0, 7)); // st1w {z0.s}, p1, [x0, #7, MUL VL]
|
|
__ sve_st1b(z0, __ B, p2, Address(sp, r1)); // st1b {z0.b}, p2, [sp, x1]
|
|
__ sve_st1h(z0, __ H, p3, Address(sp, r8)); // st1h {z0.h}, p3, [sp, x8, LSL #1]
|
|
__ sve_st1d(z0, __ D, p4, Address(r0, r17)); // st1d {z0.d}, p4, [x0, x17, LSL #3]
|
|
__ sve_ldr(z0, Address(sp)); // ldr z0, [sp]
|
|
__ sve_ldr(z31, Address(sp, -256)); // ldr z31, [sp, #-256, MUL VL]
|
|
__ sve_str(z8, Address(r8, 255)); // str z8, [x8, #255, MUL VL]
|
|
__ sve_cntb(r9); // cntb x9
|
|
__ sve_cnth(r10); // cnth x10
|
|
__ sve_cntw(r11); // cntw x11
|
|
__ sve_cntd(r12); // cntd x12
|
|
__ sve_brka(p2, p0, p2, false); // brka p2.b, p0/z, p2.b
|
|
__ sve_brka(p1, p2, p3, true); // brka p1.b, p2/m, p3.b
|
|
__ sve_brkb(p1, p2, p3, false); // brkb p1.b, p2/z, p3.b
|
|
__ sve_brkb(p2, p3, p4, true); // brkb p2.b, p3/m, p4.b
|
|
__ sve_rev(p0, __ B, p1); // rev p0.b, p1.b
|
|
__ sve_rev(p1, __ H, p2); // rev p1.h, p2.h
|
|
__ sve_rev(p2, __ S, p3); // rev p2.s, p3.s
|
|
__ sve_rev(p3, __ D, p4); // rev p3.d, p4.d
|
|
__ sve_incp(r0, __ B, p2); // incp x0, p2.b
|
|
__ sve_whilelt(p0, __ B, r1, r28); // whilelt p0.b, x1, x28
|
|
__ sve_whilele(p2, __ H, r11, r8); // whilele p2.h, x11, x8
|
|
__ sve_whilelo(p3, __ S, r7, r2); // whilelo p3.s, x7, x2
|
|
__ sve_whilels(p4, __ D, r17, r10); // whilels p4.d, x17, x10
|
|
__ sve_sel(z0, __ B, p0, z1, z2); // sel z0.b, p0, z1.b, z2.b
|
|
__ sve_sel(z4, __ D, p0, z5, z6); // sel z4.d, p0, z5.d, z6.d
|
|
__ sve_cmp(Assembler::EQ, p1, __ B, p0, z0, z1); // cmpeq p1.b, p0/z, z0.b, z1.b
|
|
__ sve_cmp(Assembler::NE, p1, __ H, p0, z2, z3); // cmpne p1.h, p0/z, z2.h, z3.h
|
|
__ sve_cmp(Assembler::GE, p1, __ S, p2, z4, z5); // cmpge p1.s, p2/z, z4.s, z5.s
|
|
__ sve_cmp(Assembler::GT, p1, __ D, p3, z6, z7); // cmpgt p1.d, p3/z, z6.d, z7.d
|
|
__ sve_cmp(Assembler::HI, p1, __ S, p2, z4, z5); // cmphi p1.s, p2/z, z4.s, z5.s
|
|
__ sve_cmp(Assembler::HS, p1, __ D, p3, z6, z7); // cmphs p1.d, p3/z, z6.d, z7.d
|
|
__ sve_cmp(Assembler::EQ, p1, __ B, p4, z0, 15); // cmpeq p1.b, p4/z, z0.b, #15
|
|
__ sve_cmp(Assembler::NE, p1, __ H, p0, z2, -16); // cmpne p1.h, p0/z, z2.h, #-16
|
|
__ sve_cmp(Assembler::LE, p1, __ S, p1, z4, 0); // cmple p1.s, p1/z, z4.s, #0
|
|
__ sve_cmp(Assembler::LT, p1, __ D, p2, z6, -1); // cmplt p1.d, p2/z, z6.d, #-1
|
|
__ sve_cmp(Assembler::GE, p1, __ S, p3, z4, 5); // cmpge p1.s, p3/z, z4.s, #5
|
|
__ sve_cmp(Assembler::GT, p1, __ B, p4, z6, -2); // cmpgt p1.b, p4/z, z6.b, #-2
|
|
__ sve_fcm(Assembler::EQ, p1, __ S, p0, z0, z1); // fcmeq p1.s, p0/z, z0.s, z1.s
|
|
__ sve_fcm(Assembler::NE, p1, __ D, p0, z2, z3); // fcmne p1.d, p0/z, z2.d, z3.d
|
|
__ sve_fcm(Assembler::GT, p1, __ S, p2, z4, z5); // fcmgt p1.s, p2/z, z4.s, z5.s
|
|
__ sve_fcm(Assembler::GE, p1, __ D, p3, z6, z7); // fcmge p1.d, p3/z, z6.d, z7.d
|
|
__ sve_uunpkhi(z0, __ H, z1); // uunpkhi z0.h, z1.b
|
|
__ sve_uunpklo(z4, __ S, z5); // uunpklo z4.s, z5.h
|
|
__ sve_sunpkhi(z6, __ D, z7); // sunpkhi z6.d, z7.s
|
|
__ sve_sunpklo(z10, __ H, z11); // sunpklo z10.h, z11.b
|
|
__ sve_scvtf(z1, __ D, p0, z0, __ S); // scvtf z1.d, p0/m, z0.s
|
|
__ sve_scvtf(z3, __ D, p1, z2, __ D); // scvtf z3.d, p1/m, z2.d
|
|
__ sve_scvtf(z6, __ S, p2, z1, __ D); // scvtf z6.s, p2/m, z1.d
|
|
__ sve_scvtf(z6, __ S, p3, z1, __ S); // scvtf z6.s, p3/m, z1.s
|
|
__ sve_scvtf(z6, __ H, p3, z1, __ S); // scvtf z6.h, p3/m, z1.s
|
|
__ sve_scvtf(z6, __ H, p3, z1, __ D); // scvtf z6.h, p3/m, z1.d
|
|
__ sve_scvtf(z6, __ H, p3, z1, __ H); // scvtf z6.h, p3/m, z1.h
|
|
__ sve_fcvt(z5, __ D, p3, z4, __ S); // fcvt z5.d, p3/m, z4.s
|
|
__ sve_fcvt(z1, __ S, p3, z0, __ D); // fcvt z1.s, p3/m, z0.d
|
|
__ sve_fcvtzs(z19, __ D, p2, z1, __ D); // fcvtzs z19.d, p2/m, z1.d
|
|
__ sve_fcvtzs(z9, __ S, p1, z8, __ S); // fcvtzs z9.s, p1/m, z8.s
|
|
__ sve_fcvtzs(z1, __ S, p2, z0, __ D); // fcvtzs z1.s, p2/m, z0.d
|
|
__ sve_fcvtzs(z1, __ D, p3, z0, __ S); // fcvtzs z1.d, p3/m, z0.s
|
|
__ sve_fcvtzs(z1, __ S, p4, z18, __ H); // fcvtzs z1.s, p4/m, z18.h
|
|
__ sve_lasta(r0, __ B, p0, z15); // lasta w0, p0, z15.b
|
|
__ sve_lastb(r1, __ B, p1, z16); // lastb w1, p1, z16.b
|
|
__ sve_lasta(v0, __ B, p0, z15); // lasta b0, p0, z15.b
|
|
__ sve_lastb(v1, __ B, p1, z16); // lastb b1, p1, z16.b
|
|
__ sve_index(z6, __ S, 1, 1); // index z6.s, #1, #1
|
|
__ sve_cpy(z7, __ H, p3, r5); // cpy z7.h, p3/m, w5
|
|
__ sve_tbl(z16, __ S, z17, z18); // tbl z16.s, {z17.s}, z18.s
|
|
__ sve_ld1w_gather(z15, p0, r5, z16); // ld1w {z15.s}, p0/z, [x5, z16.s, uxtw #2]
|
|
__ sve_ld1d_gather(z15, p0, r5, z16); // ld1d {z15.d}, p0/z, [x5, z16.d, uxtw #3]
|
|
__ sve_st1w_scatter(z15, p0, r5, z16); // st1w {z15.s}, p0, [x5, z16.s, uxtw #2]
|
|
__ sve_st1d_scatter(z15, p0, r5, z16); // st1d {z15.d}, p0, [x5, z16.d, uxtw #3]
|
|
__ sve_and(p0, p1, p2, p3); // and p0.b, p1/z, p2.b, p3.b
|
|
__ sve_ands(p4, p5, p6, p0); // ands p4.b, p5/z, p6.b, p0.b
|
|
__ sve_eor(p0, p1, p2, p3); // eor p0.b, p1/z, p2.b, p3.b
|
|
__ sve_eors(p5, p6, p0, p1); // eors p5.b, p6/z, p0.b, p1.b
|
|
__ sve_orr(p0, p1, p2, p3); // orr p0.b, p1/z, p2.b, p3.b
|
|
__ sve_orrs(p9, p1, p4, p5); // orrs p9.b, p1/z, p4.b, p5.b
|
|
__ sve_bic(p10, p7, p9, p11); // bic p10.b, p7/z, p9.b, p11.b
|
|
__ sve_ptest(p7, p1); // ptest p7, p1.b
|
|
__ sve_ptrue(p1, __ B); // ptrue p1.b
|
|
__ sve_ptrue(p1, __ B, 0b00001); // ptrue p1.b, vl1
|
|
__ sve_ptrue(p1, __ B, 0b00101); // ptrue p1.b, vl5
|
|
__ sve_ptrue(p1, __ B, 0b01001); // ptrue p1.b, vl16
|
|
__ sve_ptrue(p1, __ B, 0b01101); // ptrue p1.b, vl256
|
|
__ sve_ptrue(p2, __ H); // ptrue p2.h
|
|
__ sve_ptrue(p2, __ H, 0b00010); // ptrue p2.h, vl2
|
|
__ sve_ptrue(p2, __ H, 0b00110); // ptrue p2.h, vl6
|
|
__ sve_ptrue(p2, __ H, 0b01010); // ptrue p2.h, vl32
|
|
__ sve_ptrue(p3, __ S); // ptrue p3.s
|
|
__ sve_ptrue(p3, __ S, 0b00011); // ptrue p3.s, vl3
|
|
__ sve_ptrue(p3, __ S, 0b00111); // ptrue p3.s, vl7
|
|
__ sve_ptrue(p3, __ S, 0b01011); // ptrue p3.s, vl64
|
|
__ sve_ptrue(p4, __ D); // ptrue p4.d
|
|
__ sve_ptrue(p4, __ D, 0b00100); // ptrue p4.d, vl4
|
|
__ sve_ptrue(p4, __ D, 0b01000); // ptrue p4.d, vl8
|
|
__ sve_ptrue(p4, __ D, 0b01100); // ptrue p4.d, vl128
|
|
__ sve_pfalse(p7); // pfalse p7.b
|
|
__ sve_uzp1(p0, __ B, p0, p1); // uzp1 p0.b, p0.b, p1.b
|
|
__ sve_uzp1(p0, __ H, p0, p1); // uzp1 p0.h, p0.h, p1.h
|
|
__ sve_uzp1(p0, __ S, p0, p1); // uzp1 p0.s, p0.s, p1.s
|
|
__ sve_uzp1(p0, __ D, p0, p1); // uzp1 p0.d, p0.d, p1.d
|
|
__ sve_uzp2(p0, __ B, p0, p1); // uzp2 p0.b, p0.b, p1.b
|
|
__ sve_uzp2(p0, __ H, p0, p1); // uzp2 p0.h, p0.h, p1.h
|
|
__ sve_uzp2(p0, __ S, p0, p1); // uzp2 p0.s, p0.s, p1.s
|
|
__ sve_uzp2(p0, __ D, p0, p1); // uzp2 p0.d, p0.d, p1.d
|
|
__ sve_punpklo(p1, p0); // punpklo p1.h, p0.b
|
|
__ sve_punpkhi(p1, p0); // punpkhi p1.h, p0.b
|
|
|
|
// FloatImmediateOp
|
|
__ fmovd(v0, 2.0); // fmov d0, #2.0
|
|
__ fmovd(v0, 2.125); // fmov d0, #2.125
|
|
__ fmovd(v0, 4.0); // fmov d0, #4.0
|
|
__ fmovd(v0, 4.25); // fmov d0, #4.25
|
|
__ fmovd(v0, 8.0); // fmov d0, #8.0
|
|
__ fmovd(v0, 8.5); // fmov d0, #8.5
|
|
__ fmovd(v0, 16.0); // fmov d0, #16.0
|
|
__ fmovd(v0, 17.0); // fmov d0, #17.0
|
|
__ fmovd(v0, 0.125); // fmov d0, #0.125
|
|
__ fmovd(v0, 0.1328125); // fmov d0, #0.1328125
|
|
__ fmovd(v0, 0.25); // fmov d0, #0.25
|
|
__ fmovd(v0, 0.265625); // fmov d0, #0.265625
|
|
__ fmovd(v0, 0.5); // fmov d0, #0.5
|
|
__ fmovd(v0, 0.53125); // fmov d0, #0.53125
|
|
__ fmovd(v0, 1.0); // fmov d0, #1.0
|
|
__ fmovd(v0, 1.0625); // fmov d0, #1.0625
|
|
__ fmovd(v0, -2.0); // fmov d0, #-2.0
|
|
__ fmovd(v0, -2.125); // fmov d0, #-2.125
|
|
__ fmovd(v0, -4.0); // fmov d0, #-4.0
|
|
__ fmovd(v0, -4.25); // fmov d0, #-4.25
|
|
__ fmovd(v0, -8.0); // fmov d0, #-8.0
|
|
__ fmovd(v0, -8.5); // fmov d0, #-8.5
|
|
__ fmovd(v0, -16.0); // fmov d0, #-16.0
|
|
__ fmovd(v0, -17.0); // fmov d0, #-17.0
|
|
__ fmovd(v0, -0.125); // fmov d0, #-0.125
|
|
__ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125
|
|
__ fmovd(v0, -0.25); // fmov d0, #-0.25
|
|
__ fmovd(v0, -0.265625); // fmov d0, #-0.265625
|
|
__ fmovd(v0, -0.5); // fmov d0, #-0.5
|
|
__ fmovd(v0, -0.53125); // fmov d0, #-0.53125
|
|
__ fmovd(v0, -1.0); // fmov d0, #-1.0
|
|
__ fmovd(v0, -1.0625); // fmov d0, #-1.0625
|
|
|
|
// LSEOp
|
|
__ swp(Assembler::xword, r10, r15, r17); // swp x10, x15, [x17]
|
|
__ ldadd(Assembler::xword, r2, r10, r12); // ldadd x2, x10, [x12]
|
|
__ ldbic(Assembler::xword, r12, r15, r13); // ldclr x12, x15, [x13]
|
|
__ ldeor(Assembler::xword, r2, r7, r20); // ldeor x2, x7, [x20]
|
|
__ ldorr(Assembler::xword, r26, r16, r4); // ldset x26, x16, [x4]
|
|
__ ldsmin(Assembler::xword, r2, r4, r12); // ldsmin x2, x4, [x12]
|
|
__ ldsmax(Assembler::xword, r16, r21, r16); // ldsmax x16, x21, [x16]
|
|
__ ldumin(Assembler::xword, r16, r11, r21); // ldumin x16, x11, [x21]
|
|
__ ldumax(Assembler::xword, r23, r12, r26); // ldumax x23, x12, [x26]
|
|
|
|
// LSEOp
|
|
__ swpa(Assembler::xword, r23, r28, r14); // swpa x23, x28, [x14]
|
|
__ ldadda(Assembler::xword, r11, r24, r1); // ldadda x11, x24, [x1]
|
|
__ ldbica(Assembler::xword, r12, zr, r10); // ldclra x12, xzr, [x10]
|
|
__ ldeora(Assembler::xword, r16, r7, r2); // ldeora x16, x7, [x2]
|
|
__ ldorra(Assembler::xword, r3, r13, r19); // ldseta x3, x13, [x19]
|
|
__ ldsmina(Assembler::xword, r17, r16, r3); // ldsmina x17, x16, [x3]
|
|
__ ldsmaxa(Assembler::xword, r1, r11, r30); // ldsmaxa x1, x11, [x30]
|
|
__ ldumina(Assembler::xword, r5, r8, r15); // ldumina x5, x8, [x15]
|
|
__ ldumaxa(Assembler::xword, r29, r30, r0); // ldumaxa x29, x30, [x0]
|
|
|
|
// LSEOp
|
|
__ swpal(Assembler::xword, r20, r7, r20); // swpal x20, x7, [x20]
|
|
__ ldaddal(Assembler::xword, r23, r28, r21); // ldaddal x23, x28, [x21]
|
|
__ ldbical(Assembler::xword, r27, r25, r5); // ldclral x27, x25, [x5]
|
|
__ ldeoral(Assembler::xword, r1, r23, r16); // ldeoral x1, x23, [x16]
|
|
__ ldorral(Assembler::xword, zr, r5, r12); // ldsetal xzr, x5, [x12]
|
|
__ ldsminal(Assembler::xword, r9, r28, r15); // ldsminal x9, x28, [x15]
|
|
__ ldsmaxal(Assembler::xword, r29, r22, sp); // ldsmaxal x29, x22, [sp]
|
|
__ lduminal(Assembler::xword, r19, zr, r5); // lduminal x19, xzr, [x5]
|
|
__ ldumaxal(Assembler::xword, r14, r16, sp); // ldumaxal x14, x16, [sp]
|
|
|
|
// LSEOp
|
|
__ swpl(Assembler::xword, r16, r27, r20); // swpl x16, x27, [x20]
|
|
__ ldaddl(Assembler::xword, r16, r12, r11); // ldaddl x16, x12, [x11]
|
|
__ ldbicl(Assembler::xword, r9, r6, r30); // ldclrl x9, x6, [x30]
|
|
__ ldeorl(Assembler::xword, r17, r27, r28); // ldeorl x17, x27, [x28]
|
|
__ ldorrl(Assembler::xword, r30, r7, r10); // ldsetl x30, x7, [x10]
|
|
__ ldsminl(Assembler::xword, r20, r10, r4); // ldsminl x20, x10, [x4]
|
|
__ ldsmaxl(Assembler::xword, r24, r17, r17); // ldsmaxl x24, x17, [x17]
|
|
__ lduminl(Assembler::xword, r22, r3, r29); // lduminl x22, x3, [x29]
|
|
__ ldumaxl(Assembler::xword, r15, r22, r19); // ldumaxl x15, x22, [x19]
|
|
|
|
// LSEOp
|
|
__ swp(Assembler::word, r19, r22, r2); // swp w19, w22, [x2]
|
|
__ ldadd(Assembler::word, r15, r6, r12); // ldadd w15, w6, [x12]
|
|
__ ldbic(Assembler::word, r16, r11, r13); // ldclr w16, w11, [x13]
|
|
__ ldeor(Assembler::word, r23, r1, r30); // ldeor w23, w1, [x30]
|
|
__ ldorr(Assembler::word, r19, r5, r17); // ldset w19, w5, [x17]
|
|
__ ldsmin(Assembler::word, r2, r16, r22); // ldsmin w2, w16, [x22]
|
|
__ ldsmax(Assembler::word, r13, r10, r21); // ldsmax w13, w10, [x21]
|
|
__ ldumin(Assembler::word, r29, r27, r12); // ldumin w29, w27, [x12]
|
|
__ ldumax(Assembler::word, r27, r3, r1); // ldumax w27, w3, [x1]
|
|
|
|
// LSEOp
|
|
__ swpa(Assembler::word, zr, r24, r19); // swpa wzr, w24, [x19]
|
|
__ ldadda(Assembler::word, r17, r9, r28); // ldadda w17, w9, [x28]
|
|
__ ldbica(Assembler::word, r27, r15, r7); // ldclra w27, w15, [x7]
|
|
__ ldeora(Assembler::word, r21, r23, sp); // ldeora w21, w23, [sp]
|
|
__ ldorra(Assembler::word, r25, r2, sp); // ldseta w25, w2, [sp]
|
|
__ ldsmina(Assembler::word, r27, r16, r10); // ldsmina w27, w16, [x10]
|
|
__ ldsmaxa(Assembler::word, r23, r19, r3); // ldsmaxa w23, w19, [x3]
|
|
__ ldumina(Assembler::word, r16, r0, r25); // ldumina w16, w0, [x25]
|
|
__ ldumaxa(Assembler::word, r26, r23, r2); // ldumaxa w26, w23, [x2]
|
|
|
|
// LSEOp
|
|
__ swpal(Assembler::word, r16, r12, r4); // swpal w16, w12, [x4]
|
|
__ ldaddal(Assembler::word, r28, r30, r29); // ldaddal w28, w30, [x29]
|
|
__ ldbical(Assembler::word, r16, r27, r6); // ldclral w16, w27, [x6]
|
|
__ ldeoral(Assembler::word, r9, r29, r15); // ldeoral w9, w29, [x15]
|
|
__ ldorral(Assembler::word, r7, r4, r7); // ldsetal w7, w4, [x7]
|
|
__ ldsminal(Assembler::word, r15, r9, r23); // ldsminal w15, w9, [x23]
|
|
__ ldsmaxal(Assembler::word, r8, r2, r28); // ldsmaxal w8, w2, [x28]
|
|
__ lduminal(Assembler::word, r21, zr, r5); // lduminal w21, wzr, [x5]
|
|
__ ldumaxal(Assembler::word, r27, r0, r17); // ldumaxal w27, w0, [x17]
|
|
|
|
// LSEOp
|
|
__ swpl(Assembler::word, r15, r4, r26); // swpl w15, w4, [x26]
|
|
__ ldaddl(Assembler::word, r8, r28, r22); // ldaddl w8, w28, [x22]
|
|
__ ldbicl(Assembler::word, r27, r27, r25); // ldclrl w27, w27, [x25]
|
|
__ ldeorl(Assembler::word, r23, r0, r4); // ldeorl w23, w0, [x4]
|
|
__ ldorrl(Assembler::word, r6, r16, r0); // ldsetl w6, w16, [x0]
|
|
__ ldsminl(Assembler::word, r4, r15, r1); // ldsminl w4, w15, [x1]
|
|
__ ldsmaxl(Assembler::word, r10, r7, r5); // ldsmaxl w10, w7, [x5]
|
|
__ lduminl(Assembler::word, r10, r28, r7); // lduminl w10, w28, [x7]
|
|
__ ldumaxl(Assembler::word, r20, r23, r21); // ldumaxl w20, w23, [x21]
|
|
|
|
// SHA3SIMDOp
|
|
__ bcax(v5, __ T16B, v10, v8, v16); // bcax v5.16B, v10.16B, v8.16B, v16.16B
|
|
__ eor3(v30, __ T16B, v6, v17, v2); // eor3 v30.16B, v6.16B, v17.16B, v2.16B
|
|
__ rax1(v11, __ T2D, v29, v28); // rax1 v11.2D, v29.2D, v28.2D
|
|
__ xar(v2, __ T2D, v26, v22, 58); // xar v2.2D, v26.2D, v22.2D, #58
|
|
|
|
// SHA512SIMDOp
|
|
__ sha512h(v14, __ T2D, v13, v27); // sha512h q14, q13, v27.2D
|
|
__ sha512h2(v16, __ T2D, v23, v5); // sha512h2 q16, q23, v5.2D
|
|
__ sha512su0(v2, __ T2D, v13); // sha512su0 v2.2D, v13.2D
|
|
__ sha512su1(v10, __ T2D, v15, v10); // sha512su1 v10.2D, v15.2D, v10.2D
|
|
|
|
// SVEBinaryImmOp
|
|
__ sve_add(z26, __ S, 98u); // add z26.s, z26.s, #0x62
|
|
__ sve_sub(z3, __ S, 138u); // sub z3.s, z3.s, #0x8a
|
|
__ sve_and(z4, __ B, 131u); // and z4.b, z4.b, #0x83
|
|
__ sve_eor(z17, __ H, 16368u); // eor z17.h, z17.h, #0x3ff0
|
|
__ sve_orr(z2, __ S, 4164941887u); // orr z2.s, z2.s, #0xf83ff83f
|
|
|
|
// SVEBinaryImmOp
|
|
__ sve_add(z23, __ B, 51u); // add z23.b, z23.b, #0x33
|
|
__ sve_sub(z7, __ S, 104u); // sub z7.s, z7.s, #0x68
|
|
__ sve_and(z27, __ S, 7864320u); // and z27.s, z27.s, #0x780000
|
|
__ sve_eor(z2, __ D, 68719476224u); // eor z2.d, z2.d, #0xffffffe00
|
|
__ sve_orr(z6, __ S, 1056980736u); // orr z6.s, z6.s, #0x3f003f00
|
|
|
|
// SVEBinaryImmOp
|
|
__ sve_add(z12, __ S, 67u); // add z12.s, z12.s, #0x43
|
|
__ sve_sub(z24, __ S, 154u); // sub z24.s, z24.s, #0x9a
|
|
__ sve_and(z0, __ H, 511u); // and z0.h, z0.h, #0x1ff
|
|
__ sve_eor(z19, __ D, 9241386433220968447u); // eor z19.d, z19.d, #0x803fffff803fffff
|
|
__ sve_orr(z6, __ B, 128u); // orr z6.b, z6.b, #0x80
|
|
|
|
// SVEBinaryImmOp
|
|
__ sve_add(z17, __ D, 74u); // add z17.d, z17.d, #0x4a
|
|
__ sve_sub(z10, __ S, 170u); // sub z10.s, z10.s, #0xaa
|
|
__ sve_and(z22, __ D, 17179852800u); // and z22.d, z22.d, #0x3ffffc000
|
|
__ sve_eor(z15, __ S, 8388600u); // eor z15.s, z15.s, #0x7ffff8
|
|
__ sve_orr(z4, __ D, 8064u); // orr z4.d, z4.d, #0x1f80
|
|
|
|
// SVEBinaryImmOp
|
|
__ sve_add(z8, __ S, 162u); // add z8.s, z8.s, #0xa2
|
|
__ sve_sub(z22, __ B, 130u); // sub z22.b, z22.b, #0x82
|
|
__ sve_and(z9, __ S, 4292870159u); // and z9.s, z9.s, #0xffe0000f
|
|
__ sve_eor(z5, __ D, 1150687262887383032u); // eor z5.d, z5.d, #0xff80ff80ff80ff8
|
|
__ sve_orr(z22, __ H, 32256u); // orr z22.h, z22.h, #0x7e00
|
|
|
|
// SVEBinaryImmOp
|
|
__ sve_add(z8, __ S, 134u); // add z8.s, z8.s, #0x86
|
|
__ sve_sub(z25, __ H, 39u); // sub z25.h, z25.h, #0x27
|
|
__ sve_and(z4, __ S, 4186112u); // and z4.s, z4.s, #0x3fe000
|
|
__ sve_eor(z29, __ B, 131u); // eor z29.b, z29.b, #0x83
|
|
__ sve_orr(z29, __ D, 4611685469745315712u); // orr z29.d, z29.d, #0x3fffff803fffff80
|
|
|
|
// SVEVectorOp
|
|
__ sve_add(z2, __ B, z11, z28); // add z2.b, z11.b, z28.b
|
|
__ sve_sub(z7, __ S, z1, z26); // sub z7.s, z1.s, z26.s
|
|
__ sve_fadd(z17, __ D, z14, z8); // fadd z17.d, z14.d, z8.d
|
|
__ sve_fmul(z21, __ D, z24, z5); // fmul z21.d, z24.d, z5.d
|
|
__ sve_fsub(z21, __ D, z17, z22); // fsub z21.d, z17.d, z22.d
|
|
__ sve_abs(z29, __ B, p5, z19); // abs z29.b, p5/m, z19.b
|
|
__ sve_add(z4, __ B, p4, z23); // add z4.b, p4/m, z4.b, z23.b
|
|
__ sve_and(z19, __ D, p1, z23); // and z19.d, p1/m, z19.d, z23.d
|
|
__ sve_asr(z19, __ H, p0, z8); // asr z19.h, p0/m, z19.h, z8.h
|
|
__ sve_bic(z14, __ D, p6, z17); // bic z14.d, p6/m, z14.d, z17.d
|
|
__ sve_cnt(z21, __ B, p1, z30); // cnt z21.b, p1/m, z30.b
|
|
__ sve_eor(z10, __ B, p5, z12); // eor z10.b, p5/m, z10.b, z12.b
|
|
__ sve_lsl(z9, __ S, p1, z24); // lsl z9.s, p1/m, z9.s, z24.s
|
|
__ sve_lsr(z4, __ H, p6, z6); // lsr z4.h, p6/m, z4.h, z6.h
|
|
__ sve_mul(z27, __ S, p6, z13); // mul z27.s, p6/m, z27.s, z13.s
|
|
__ sve_neg(z30, __ S, p5, z22); // neg z30.s, p5/m, z22.s
|
|
__ sve_not(z30, __ H, p7, z9); // not z30.h, p7/m, z9.h
|
|
__ sve_orr(z19, __ D, p1, z20); // orr z19.d, p1/m, z19.d, z20.d
|
|
__ sve_smax(z9, __ H, p2, z13); // smax z9.h, p2/m, z9.h, z13.h
|
|
__ sve_smin(z19, __ H, p0, z24); // smin z19.h, p0/m, z19.h, z24.h
|
|
__ sve_sub(z19, __ S, p3, z17); // sub z19.s, p3/m, z19.s, z17.s
|
|
__ sve_fabs(z16, __ S, p1, z0); // fabs z16.s, p1/m, z0.s
|
|
__ sve_fadd(z11, __ S, p2, z15); // fadd z11.s, p2/m, z11.s, z15.s
|
|
__ sve_fdiv(z15, __ D, p1, z15); // fdiv z15.d, p1/m, z15.d, z15.d
|
|
__ sve_fmax(z5, __ D, p0, z10); // fmax z5.d, p0/m, z5.d, z10.d
|
|
__ sve_fmin(z26, __ S, p0, z0); // fmin z26.s, p0/m, z26.s, z0.s
|
|
__ sve_fmul(z19, __ D, p7, z10); // fmul z19.d, p7/m, z19.d, z10.d
|
|
__ sve_fneg(z3, __ D, p5, z7); // fneg z3.d, p5/m, z7.d
|
|
__ sve_frintm(z28, __ S, p3, z21); // frintm z28.s, p3/m, z21.s
|
|
__ sve_frintn(z26, __ D, p3, z17); // frintn z26.d, p3/m, z17.d
|
|
__ sve_frintp(z17, __ D, p3, z2); // frintp z17.d, p3/m, z2.d
|
|
__ sve_fsqrt(z16, __ S, p5, z20); // fsqrt z16.s, p5/m, z20.s
|
|
__ sve_fsub(z19, __ D, p0, z1); // fsub z19.d, p0/m, z19.d, z1.d
|
|
__ sve_fmad(z17, __ D, p2, z16, z17); // fmad z17.d, p2/m, z16.d, z17.d
|
|
__ sve_fmla(z0, __ S, p1, z2, z23); // fmla z0.s, p1/m, z2.s, z23.s
|
|
__ sve_fmls(z6, __ D, p2, z20, z14); // fmls z6.d, p2/m, z20.d, z14.d
|
|
__ sve_fnmla(z29, __ D, p3, z3, z3); // fnmla z29.d, p3/m, z3.d, z3.d
|
|
__ sve_fnmls(z9, __ S, p0, z24, z27); // fnmls z9.s, p0/m, z24.s, z27.s
|
|
__ sve_mla(z19, __ S, p5, z7, z25); // mla z19.s, p5/m, z7.s, z25.s
|
|
__ sve_mls(z13, __ B, p1, z7, z25); // mls z13.b, p1/m, z7.b, z25.b
|
|
__ sve_and(z21, z17, z17); // and z21.d, z17.d, z17.d
|
|
__ sve_eor(z3, z9, z19); // eor z3.d, z9.d, z19.d
|
|
__ sve_orr(z7, z11, z14); // orr z7.d, z11.d, z14.d
|
|
__ sve_bic(z17, z11, z13); // bic z17.d, z11.d, z13.d
|
|
__ sve_uzp1(z17, __ H, z30, z17); // uzp1 z17.h, z30.h, z17.h
|
|
__ sve_uzp2(z15, __ S, z14, z26); // uzp2 z15.s, z14.s, z26.s
|
|
|
|
// SVEReductionOp
|
|
__ sve_andv(v27, __ H, p5, z7); // andv h27, p5, z7.h
|
|
__ sve_orv(v5, __ H, p7, z27); // orv h5, p7, z27.h
|
|
__ sve_eorv(v0, __ S, p3, z24); // eorv s0, p3, z24.s
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|
__ sve_smaxv(v20, __ S, p0, z3); // smaxv s20, p0, z3.s
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|
__ sve_sminv(v25, __ D, p1, z25); // sminv d25, p1, z25.d
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|
__ sve_fminv(v17, __ S, p4, z1); // fminv s17, p4, z1.s
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|
__ sve_fmaxv(v14, __ S, p7, z13); // fmaxv s14, p7, z13.s
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|
__ sve_fadda(v17, __ D, p0, z30); // fadda d17, p0, d17, z30.d
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|
__ sve_uaddv(v22, __ H, p5, z29); // uaddv d22, p5, z29.h
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|
|
|
__ bind(forth);
|
|
|
|
/*
|
|
*/
|
|
|
|
static const unsigned int insns[] =
|
|
{
|
|
0x8b0d82fa, 0xcb49970c, 0xab889dfc, 0xeb9ee787,
|
|
0x0b9b3ec9, 0x4b9179a3, 0x2b88474e, 0x6b8c56c0,
|
|
0x8a1a51e0, 0xaa11f4ba, 0xca0281b8, 0xea918c7c,
|
|
0x0a5d4a19, 0x2a4b262d, 0x4a513ca5, 0x6a9b6ae2,
|
|
0x8a70b79b, 0xaaba9728, 0xca6dfe3d, 0xea627f1c,
|
|
0x0aa70f53, 0x2aaa0f06, 0x4a6176a4, 0x6a604eb0,
|
|
0x1105ed91, 0x3100583e, 0x5101f8bd, 0x710f0306,
|
|
0x9101a1a0, 0xb10a5cc8, 0xd10810aa, 0xf10fd061,
|
|
0x120cb166, 0x321764bc, 0x52174681, 0x720c0227,
|
|
0x9241018e, 0xb25a2969, 0xd278b411, 0xf26aad01,
|
|
0x14000000, 0x17ffffd7, 0x140003d2, 0x94000000,
|
|
0x97ffffd4, 0x940003cf, 0x3400000a, 0x34fffa2a,
|
|
0x3400798a, 0x35000008, 0x35fff9c8, 0x35007928,
|
|
0xb400000b, 0xb4fff96b, 0xb40078cb, 0xb500001d,
|
|
0xb5fff91d, 0xb500787d, 0x10000013, 0x10fff8b3,
|
|
0x10007813, 0x90000013, 0x36300016, 0x3637f836,
|
|
0x36307796, 0x3758000c, 0x375ff7cc, 0x3758772c,
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|
0x128313a0, 0x528a32c7, 0x7289173b, 0x92ab3acc,
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|
0xd2a0bf94, 0xf2c285e8, 0x9358722f, 0x330e652f,
|
|
0x53067f3b, 0x93577c53, 0xb34a1aac, 0xd35a4016,
|
|
0x13946c63, 0x93c3dbc8, 0x54000000, 0x54fff5a0,
|
|
0x54007500, 0x54000001, 0x54fff541, 0x540074a1,
|
|
0x54000002, 0x54fff4e2, 0x54007442, 0x54000002,
|
|
0x54fff482, 0x540073e2, 0x54000003, 0x54fff423,
|
|
0x54007383, 0x54000003, 0x54fff3c3, 0x54007323,
|
|
0x54000004, 0x54fff364, 0x540072c4, 0x54000005,
|
|
0x54fff305, 0x54007265, 0x54000006, 0x54fff2a6,
|
|
0x54007206, 0x54000007, 0x54fff247, 0x540071a7,
|
|
0x54000008, 0x54fff1e8, 0x54007148, 0x54000009,
|
|
0x54fff189, 0x540070e9, 0x5400000a, 0x54fff12a,
|
|
0x5400708a, 0x5400000b, 0x54fff0cb, 0x5400702b,
|
|
0x5400000c, 0x54fff06c, 0x54006fcc, 0x5400000d,
|
|
0x54fff00d, 0x54006f6d, 0x5400000e, 0x54ffefae,
|
|
0x54006f0e, 0x5400000f, 0x54ffef4f, 0x54006eaf,
|
|
0xd40658e1, 0xd4014d22, 0xd4046543, 0xd4273f60,
|
|
0xd44cad80, 0xd503201f, 0xd503203f, 0xd503205f,
|
|
0xd503209f, 0xd50320bf, 0xd503219f, 0xd50323bf,
|
|
0xd503239f, 0xd50321df, 0xd50323ff, 0xd50323df,
|
|
0xd503211f, 0xd503233f, 0xd503231f, 0xd503215f,
|
|
0xd503237f, 0xd503235f, 0xd69f03e0, 0xd6bf03e0,
|
|
0xd5033fdf, 0xd503207f, 0xd50320ff, 0xd5033e9f,
|
|
0xd50332bf, 0xd61f0200, 0xd63f0280, 0xdac123ea,
|
|
0xdac127fb, 0xdac12be8, 0xdac12fe0, 0xdac133e1,
|
|
0xdac137f5, 0xdac13bf1, 0xdac13ffd, 0xdac147fd,
|
|
0xd61f0b9f, 0xd61f0c3f, 0xd63f0aff, 0xd63f0ebf,
|
|
0xdac143f4, 0xc8167e7b, 0xc80bfcd0, 0xc85f7c11,
|
|
0xc85ffd44, 0xc89ffed8, 0xc8dffe6a, 0x88017fc5,
|
|
0x8808fe2c, 0x885f7dc9, 0x885ffc27, 0x889ffe05,
|
|
0x88dffd82, 0x480a7c6c, 0x481cff4e, 0x485f7d5e,
|
|
0x485ffeae, 0x489ffd2d, 0x48dfff76, 0x081c7d73,
|
|
0x081efc53, 0x085f7ee2, 0x085ffc01, 0x089ffe0c,
|
|
0x08dffded, 0xc87f55b1, 0xc87ff90b, 0xc8382c2d,
|
|
0xc83aedb5, 0x887f0d94, 0x887f87a6, 0x88262e04,
|
|
0x8824b2be, 0xf8061366, 0xb802d151, 0x381e32da,
|
|
0x781ce155, 0xf847d30e, 0xb85f0307, 0x39403448,
|
|
0x785c333e, 0x389f2183, 0x789e422a, 0x78dfb075,
|
|
0xb8817322, 0xfc5bb039, 0xbc40637d, 0xfc02919d,
|
|
0xbc18d2c2, 0xf8003cba, 0xb8199cb4, 0x381e7d88,
|
|
0x781c7c54, 0xf8516fae, 0xb8404fad, 0x385f7e78,
|
|
0x785edf63, 0x389fbc31, 0x789f3e71, 0x78de6d75,
|
|
0xb89c4d21, 0xfc509efa, 0xbc581eb6, 0xfc128ced,
|
|
0xbc198dac, 0xf81134b4, 0xb81b679d, 0x381ea704,
|
|
0x781eb52d, 0xf85c94fa, 0xb858d46d, 0x3840c4a1,
|
|
0x785de5a8, 0x389e5697, 0x789fe4d4, 0x78dd6629,
|
|
0xb89e24d5, 0xfc5e36d0, 0xbc5fd569, 0xfc03c756,
|
|
0xbc1fe7b0, 0xf824cac1, 0xb82d7bd7, 0x382c596c,
|
|
0x78207999, 0xf86058f1, 0xb86e5a61, 0x3869784c,
|
|
0x787bc936, 0x38aff995, 0x78b078dc, 0x78f6ca39,
|
|
0xb8bdea24, 0xfc63f825, 0xbc6d5a38, 0xfc37fa31,
|
|
0xbc25dbd1, 0xf91ba97d, 0xb91e4abc, 0x391b485c,
|
|
0x7919c380, 0xf95e18f9, 0xb958a860, 0x395f20be,
|
|
0x7958f6ee, 0x399bea6a, 0x799b363d, 0x79da47d9,
|
|
0xb99d5851, 0xfd5da60f, 0xbd584fcc, 0xfd1db821,
|
|
0xbd1e9965, 0x58ffdb71, 0x18ffdb42, 0xf886f320,
|
|
0xd8ffdb00, 0xf8bb49c0, 0xf99815c0, 0x1a0f0320,
|
|
0x3a030301, 0x5a140311, 0x7a0d000b, 0x9a07015c,
|
|
0xba1001e4, 0xda140182, 0xfa0d01bd, 0x0b2c6cce,
|
|
0x2b3e5331, 0xcb2e0620, 0x6b3de709, 0x8b20cac1,
|
|
0xab362f8c, 0xcb31518a, 0xeb2acf8f, 0x3a57d262,
|
|
0x7a493226, 0xba4832a2, 0xfa454261, 0x3a518acc,
|
|
0x7a472a23, 0xba5cba05, 0xfa439ac5, 0x1a8cb35d,
|
|
0x1a8f355b, 0x5a9e9395, 0x5a9e3769, 0x9a9dd1fd,
|
|
0x9a8406b9, 0xda9d62b1, 0xda868695, 0x5ac0007e,
|
|
0x5ac00675, 0x5ac00b0b, 0x5ac01360, 0x5ac015d9,
|
|
0xdac001c3, 0xdac004f1, 0xdac00b0f, 0xdac00e3c,
|
|
0xdac01059, 0xdac0179a, 0xdac10325, 0xdac1077a,
|
|
0xdac10a30, 0xdac10ea6, 0xdac1100c, 0xdac11584,
|
|
0xdac11a3b, 0xdac11f9c, 0xd71f0851, 0xd71f0d4f,
|
|
0xd73f09ce, 0xd73f0c79, 0x1ace0a6f, 0x1ac40e05,
|
|
0x1ac4233a, 0x1acc2442, 0x1ac82a3d, 0x1ac42c67,
|
|
0x9ada0899, 0x9ad10c99, 0x9ad12340, 0x9ad525f7,
|
|
0x9adb2a3c, 0x9ac02c6a, 0x9bc97f27, 0x9b5d7de6,
|
|
0x1b02454f, 0x1b0bdd67, 0x9b173ba7, 0x9b0b917b,
|
|
0x9b2f3998, 0x9b3cb574, 0x9bb7798b, 0x9ba9b5da,
|
|
0x7ea5d4ea, 0x1e2309fd, 0x1e2f198b, 0x1e312bde,
|
|
0x1e2f3a93, 0x7ef5d52f, 0x1e7b0922, 0x1e7e1ba7,
|
|
0x1e622831, 0x1e633946, 0x1f070578, 0x1f03c40b,
|
|
0x1f3618dc, 0x1f3a0b60, 0x1f5c2ce5, 0x1f4bddb9,
|
|
0x1f715513, 0x1f734699, 0x1e2043a2, 0x1e20c116,
|
|
0x1e214275, 0x1e21c174, 0x1e22c291, 0x1e6041e6,
|
|
0x1e60c063, 0x1e61407c, 0x1e61c1db, 0x1e62414e,
|
|
0x1e38016c, 0x9e380151, 0x1e7800f9, 0x9e7801c7,
|
|
0x1e22001c, 0x9e220016, 0x1e6202ec, 0x9e6201ad,
|
|
0x1e2601c7, 0x9e660107, 0x1e270234, 0x9e6703dc,
|
|
0x1e222200, 0x1e702120, 0x1e202288, 0x1e6023a8,
|
|
0x29266b01, 0x29462d85, 0x69463f75, 0xa90272c5,
|
|
0xa97e467b, 0x29aa1f4d, 0x29fa54cd, 0x69c27b74,
|
|
0xa9b81555, 0xa9fa12ee, 0x2884321d, 0x28cc477a,
|
|
0x68f451c4, 0xa8b909d0, 0xa8f060f7, 0x281069e0,
|
|
0x2866191a, 0xa8392b2f, 0xa8760670, 0x0c4073db,
|
|
0x4cdfa079, 0x0cca6e1e, 0x4cdf2670, 0x0d40c317,
|
|
0x4ddfc948, 0x0dd7ce89, 0x4c408c62, 0x0cdf87c8,
|
|
0x4d60c344, 0x0dffca23, 0x4df0cd7d, 0x4cd74801,
|
|
0x0c404aa0, 0x4d40e4e5, 0x4ddfe8e1, 0x0dcfeca2,
|
|
0x4cdf07bb, 0x0cc70098, 0x0d60e2ef, 0x0dffe6ae,
|
|
0x0df9e934, 0x0e31bb17, 0x4e31bb7a, 0x0e71b8c5,
|
|
0x4e71b8e6, 0x4eb1ba0f, 0x0e30aa0f, 0x4e30ab59,
|
|
0x0e70aa30, 0x4e70ab9b, 0x4eb0ab38, 0x6e30fa0f,
|
|
0x0e31ab59, 0x2e31a9ee, 0x4e31a96a, 0x6e31a9cd,
|
|
0x0e71a9ee, 0x2e71aab4, 0x4e71a841, 0x6e71aaf6,
|
|
0x4eb1abfe, 0x6eb1a9ee, 0x6eb0f862, 0x7e30f8e6,
|
|
0x7e70f883, 0x7eb0f907, 0x7ef0fb38, 0x0e20b820,
|
|
0x4e20bb9b, 0x0e60bbdd, 0x4e60b8c5, 0x0ea0b8c5,
|
|
0x4ea0bbdd, 0x4ee0b98b, 0x0ea0fb59, 0x4ea0f820,
|
|
0x4ee0fbfe, 0x2ea0f820, 0x6ea0fa51, 0x6ee0fbbc,
|
|
0x2ea1fb59, 0x6ea1f949, 0x6ee1fb59, 0x2e2059ac,
|
|
0x6e205a0f, 0x0e2d1d8b, 0x4e2c1d6a, 0x0eb31e51,
|
|
0x4eba1f38, 0x2e371ed5, 0x6e391f17, 0x0e228420,
|
|
0x4e328630, 0x0e6c856a, 0x4e6884e6, 0x0ebe87bc,
|
|
0x4ea884e6, 0x4ee784c5, 0x0e27d4c5, 0x4e36d6b4,
|
|
0x4e73d651, 0x2e31860f, 0x6e338651, 0x2e7f87dd,
|
|
0x6e7c877a, 0x2ebe87bc, 0x6ea38441, 0x6efd879b,
|
|
0x0ea2d420, 0x4eb6d6b4, 0x4efed7bc, 0x0e319e0f,
|
|
0x4e2e9dac, 0x0e6c9d6a, 0x4e7e9fbc, 0x0ebe9fbc,
|
|
0x4eb59e93, 0x2eb8d6f6, 0x6eacd56a, 0x6ee6d4a4,
|
|
0x2e20dffe, 0x6e36deb4, 0x6e6add28, 0x0e6097fe,
|
|
0x4e739651, 0x0eac956a, 0x4ebd979b, 0x0e24cc62,
|
|
0x4e3acf38, 0x4e66cca4, 0x2e659483, 0x6e6a9528,
|
|
0x2eb896f6, 0x6eb39651, 0x0eafcdcd, 0x4ea6cca4,
|
|
0x4efecfbc, 0x2e39ff17, 0x6e37fed5, 0x6e7bff59,
|
|
0x0e3a6738, 0x4e256483, 0x0e796717, 0x4e7c677a,
|
|
0x0eb96717, 0x4eb065ee, 0x0e37a6d5, 0x4e25a483,
|
|
0x0e79a717, 0x4e6aa528, 0x0ebaa738, 0x4eb5a693,
|
|
0x0e31f60f, 0x4e32f630, 0x4e64f462, 0x0e236c41,
|
|
0x4e226c20, 0x0e7a6f38, 0x4e666ca4, 0x0ea56c83,
|
|
0x4ead6d8b, 0x0e20affe, 0x4e3daf9b, 0x0e6bad49,
|
|
0x4e7baf59, 0x0ea4ac62, 0x4eaeadac, 0x0eb3f651,
|
|
0x4ea0f7fe, 0x4ee3f441, 0x2e2e8dac, 0x6e3e8fbc,
|
|
0x2e628c20, 0x6e738e51, 0x2eae8dac, 0x6eb38e51,
|
|
0x6ef78ed5, 0x0e2ee5ac, 0x4e3de79b, 0x4e7fe7dd,
|
|
0x0e2037fe, 0x4e233441, 0x0e7b3759, 0x4e7d379b,
|
|
0x0ea634a4, 0x4ebf37dd, 0x4ee53483, 0x2e2834e6,
|
|
0x6e3f37dd, 0x2e7b3759, 0x6e733651, 0x2eaa3528,
|
|
0x6ea93507, 0x6eee35ac, 0x2e223c20, 0x6e353e93,
|
|
0x2e633c41, 0x6e793f17, 0x2ea43c62, 0x6ea23c20,
|
|
0x6eea3d28, 0x2eb9e717, 0x6ebbe759, 0x6ef1e60f,
|
|
0x0e3f3fdd, 0x4e253c83, 0x0e6c3d6a, 0x4e783ef6,
|
|
0x0eac3d6a, 0x4ea63ca4, 0x4ef33e51, 0x2e23e441,
|
|
0x6e2de58b, 0x6e69e507, 0xba5fd3e3, 0x3a5f03e5,
|
|
0xfa411be4, 0x7a42cbe2, 0x93df03ff, 0xc820ffff,
|
|
0x8822fc7f, 0xc8247cbf, 0x88267fff, 0x4e010fe0,
|
|
0x5e040420, 0x4e081fe1, 0x4e0c1fe1, 0x4e0a1fe1,
|
|
0x4e071fe1, 0x4e042c20, 0x4e062c20, 0x4e052c20,
|
|
0x4e083c20, 0x0e0c3c20, 0x0e0a3c20, 0x0e073c20,
|
|
0x9eae0020, 0x4cc0ac3f, 0x4ea1b820, 0x05a08020,
|
|
0x05104fe0, 0x05505001, 0x05906fe2, 0x05d03005,
|
|
0x05101fea, 0x05901feb, 0x04b0e3e0, 0x0470e7e1,
|
|
0x042f9c20, 0x043f9c35, 0x047f9c20, 0x04ff9c20,
|
|
0x04299420, 0x04319160, 0x0461943e, 0x04a19020,
|
|
0x04038100, 0x040381a0, 0x040387e1, 0x04438be2,
|
|
0x04c38fe3, 0x040181e0, 0x04018100, 0x04018621,
|
|
0x04418b22, 0x04418822, 0x04818c23, 0x040081e0,
|
|
0x04008120, 0x04008761, 0x04008621, 0x04408822,
|
|
0x04808c23, 0x042053ff, 0x047f5401, 0x25208028,
|
|
0x2538cfe0, 0x2578d001, 0x25b8efe2, 0x25f8f007,
|
|
0x2538dfea, 0x25b8dfeb, 0xa400a3e0, 0xa420a7e0,
|
|
0xa4484be0, 0xa467afe0, 0xa4a8a7ea, 0xa547a814,
|
|
0xa4084ffe, 0xa55c53e0, 0xa5e1540b, 0xe400fbf6,
|
|
0xe408ffff, 0xe420e7e0, 0xe4484be0, 0xe460efe0,
|
|
0xe547e400, 0xe4014be0, 0xe4a84fe0, 0xe5f15000,
|
|
0x858043e0, 0x85a043ff, 0xe59f5d08, 0x0420e3e9,
|
|
0x0460e3ea, 0x04a0e3eb, 0x04e0e3ec, 0x25104042,
|
|
0x25104871, 0x25904861, 0x25904c92, 0x05344020,
|
|
0x05744041, 0x05b44062, 0x05f44083, 0x252c8840,
|
|
0x253c1420, 0x25681572, 0x25a21ce3, 0x25ea1e34,
|
|
0x0522c020, 0x05e6c0a4, 0x2401a001, 0x2443a051,
|
|
0x24858881, 0x24c78cd1, 0x24850891, 0x24c70cc1,
|
|
0x250f9001, 0x25508051, 0x25802491, 0x25df28c1,
|
|
0x25850c81, 0x251e10d1, 0x65816001, 0x65c36051,
|
|
0x65854891, 0x65c74cc1, 0x05733820, 0x05b238a4,
|
|
0x05f138e6, 0x0570396a, 0x65d0a001, 0x65d6a443,
|
|
0x65d4a826, 0x6594ac26, 0x6554ac26, 0x6556ac26,
|
|
0x6552ac26, 0x65cbac85, 0x65caac01, 0x65dea833,
|
|
0x659ca509, 0x65d8a801, 0x65dcac01, 0x655cb241,
|
|
0x0520a1e0, 0x0521a601, 0x052281e0, 0x05238601,
|
|
0x04a14026, 0x0568aca7, 0x05b23230, 0x853040af,
|
|
0xc5b040af, 0xe57080af, 0xe5b080af, 0x25034440,
|
|
0x254054c4, 0x25034640, 0x25415a05, 0x25834440,
|
|
0x25c54489, 0x250b5d3a, 0x2550dc20, 0x2518e3e1,
|
|
0x2518e021, 0x2518e0a1, 0x2518e121, 0x2518e1a1,
|
|
0x2558e3e2, 0x2558e042, 0x2558e0c2, 0x2558e142,
|
|
0x2598e3e3, 0x2598e063, 0x2598e0e3, 0x2598e163,
|
|
0x25d8e3e4, 0x25d8e084, 0x25d8e104, 0x25d8e184,
|
|
0x2518e407, 0x05214800, 0x05614800, 0x05a14800,
|
|
0x05e14800, 0x05214c00, 0x05614c00, 0x05a14c00,
|
|
0x05e14c00, 0x05304001, 0x05314001, 0x1e601000,
|
|
0x1e603000, 0x1e621000, 0x1e623000, 0x1e641000,
|
|
0x1e643000, 0x1e661000, 0x1e663000, 0x1e681000,
|
|
0x1e683000, 0x1e6a1000, 0x1e6a3000, 0x1e6c1000,
|
|
0x1e6c3000, 0x1e6e1000, 0x1e6e3000, 0x1e701000,
|
|
0x1e703000, 0x1e721000, 0x1e723000, 0x1e741000,
|
|
0x1e743000, 0x1e761000, 0x1e763000, 0x1e781000,
|
|
0x1e783000, 0x1e7a1000, 0x1e7a3000, 0x1e7c1000,
|
|
0x1e7c3000, 0x1e7e1000, 0x1e7e3000, 0xf82a822f,
|
|
0xf822018a, 0xf82c11af, 0xf8222287, 0xf83a3090,
|
|
0xf8225184, 0xf8304215, 0xf83072ab, 0xf837634c,
|
|
0xf8b781dc, 0xf8ab0038, 0xf8ac115f, 0xf8b02047,
|
|
0xf8a3326d, 0xf8b15070, 0xf8a143cb, 0xf8a571e8,
|
|
0xf8bd601e, 0xf8f48287, 0xf8f702bc, 0xf8fb10b9,
|
|
0xf8e12217, 0xf8ff3185, 0xf8e951fc, 0xf8fd43f6,
|
|
0xf8f370bf, 0xf8ee63f0, 0xf870829b, 0xf870016c,
|
|
0xf86913c6, 0xf871239b, 0xf87e3147, 0xf874508a,
|
|
0xf8784231, 0xf87673a3, 0xf86f6276, 0xb8338056,
|
|
0xb82f0186, 0xb83011ab, 0xb83723c1, 0xb8333225,
|
|
0xb82252d0, 0xb82d42aa, 0xb83d719b, 0xb83b6023,
|
|
0xb8bf8278, 0xb8b10389, 0xb8bb10ef, 0xb8b523f7,
|
|
0xb8b933e2, 0xb8bb5150, 0xb8b74073, 0xb8b07320,
|
|
0xb8ba6057, 0xb8f0808c, 0xb8fc03be, 0xb8f010db,
|
|
0xb8e921fd, 0xb8e730e4, 0xb8ef52e9, 0xb8e84382,
|
|
0xb8f570bf, 0xb8fb6220, 0xb86f8344, 0xb86802dc,
|
|
0xb87b133b, 0xb8772080, 0xb8663010, 0xb864502f,
|
|
0xb86a40a7, 0xb86a70fc, 0xb87462b7, 0xce284145,
|
|
0xce1108de, 0xce7c8fab, 0xce96eb42, 0xce7b81ae,
|
|
0xce6586f0, 0xcec081a2, 0xce6a89ea, 0x25a0cc5a,
|
|
0x25a1d143, 0x05800e44, 0x05406531, 0x05002d42,
|
|
0x2520c677, 0x25a1cd07, 0x0580687b, 0x0543bb42,
|
|
0x050044a6, 0x25a0c86c, 0x25a1d358, 0x05800500,
|
|
0x05400ad3, 0x05000e06, 0x25e0c951, 0x25a1d54a,
|
|
0x05839276, 0x0540ea6f, 0x0503c8a4, 0x25a0d448,
|
|
0x2521d056, 0x058059c9, 0x05406d05, 0x05003cb6,
|
|
0x25a0d0c8, 0x2561c4f9, 0x05809904, 0x05400e5d,
|
|
0x0500cadd, 0x043c0162, 0x04ba0427, 0x65c801d1,
|
|
0x65c50b15, 0x65d60635, 0x0416b67d, 0x040012e4,
|
|
0x04da06f3, 0x04508113, 0x04db1a2e, 0x041aa7d5,
|
|
0x0419158a, 0x04938709, 0x045198c4, 0x049019bb,
|
|
0x0497b6de, 0x045ebd3e, 0x04d80693, 0x044809a9,
|
|
0x044a0313, 0x04810e33, 0x049ca410, 0x658089eb,
|
|
0x65cd85ef, 0x65c68145, 0x6587801a, 0x65c29d53,
|
|
0x04ddb4e3, 0x6582aebc, 0x65c0ae3a, 0x65c1ac51,
|
|
0x658db690, 0x65c18033, 0x65f18a11, 0x65b70440,
|
|
0x65ee2a86, 0x65e34c7d, 0x65bb6309, 0x049954f3,
|
|
0x041964ed, 0x04313235, 0x04b33123, 0x046e3167,
|
|
0x04ed3171, 0x05716bd1, 0x05ba6dcf, 0x045a34fb,
|
|
0x04583f65, 0x04992f00, 0x04882074, 0x04ca2739,
|
|
0x65873031, 0x65863dae, 0x65d823d1, 0x044137b6,
|
|
|
|
};
|
|
// END Generated code -- do not edit
|