283 lines
9.9 KiB
C++
283 lines
9.9 KiB
C++
/*
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* Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#ifndef SHARE_C1_C1_LIRASSEMBLER_HPP
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#define SHARE_C1_C1_LIRASSEMBLER_HPP
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#include "c1/c1_CodeStubs.hpp"
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#include "ci/ciMethodData.hpp"
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#include "oops/methodData.hpp"
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#include "utilities/macros.hpp"
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class Compilation;
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class ScopeValue;
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class BarrierSet;
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class LIR_Assembler: public CompilationResourceObj {
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private:
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C1_MacroAssembler* _masm;
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CodeStubList* _slow_case_stubs;
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BarrierSet* _bs;
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Compilation* _compilation;
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FrameMap* _frame_map;
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BlockBegin* _current_block;
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Instruction* _pending_non_safepoint;
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int _pending_non_safepoint_offset;
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Label _unwind_handler_entry;
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#ifdef ASSERT
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BlockList _branch_target_blocks;
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void check_no_unbound_labels();
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#endif
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FrameMap* frame_map() const { return _frame_map; }
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void set_current_block(BlockBegin* b) { _current_block = b; }
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BlockBegin* current_block() const { return _current_block; }
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// non-safepoint debug info management
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void flush_debug_info(int before_pc_offset) {
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if (_pending_non_safepoint != NULL) {
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if (_pending_non_safepoint_offset < before_pc_offset)
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record_non_safepoint_debug_info();
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_pending_non_safepoint = NULL;
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}
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}
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void process_debug_info(LIR_Op* op);
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void record_non_safepoint_debug_info();
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// unified bailout support
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void bailout(const char* msg) const { compilation()->bailout(msg); }
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bool bailed_out() const { return compilation()->bailed_out(); }
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// code emission patterns and accessors
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void check_codespace();
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bool needs_icache(ciMethod* method) const;
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// returns offset of icache check
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int check_icache();
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void jobject2reg(jobject o, Register reg);
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void jobject2reg_with_patching(Register reg, CodeEmitInfo* info);
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void metadata2reg(Metadata* o, Register reg);
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void klass2reg_with_patching(Register reg, CodeEmitInfo* info);
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void emit_stubs(CodeStubList* stub_list);
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// addresses
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Address as_Address(LIR_Address* addr);
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Address as_Address_lo(LIR_Address* addr);
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Address as_Address_hi(LIR_Address* addr);
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// debug information
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void add_call_info(int pc_offset, CodeEmitInfo* cinfo);
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void add_debug_info_for_branch(CodeEmitInfo* info);
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void add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo);
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void add_debug_info_for_div0_here(CodeEmitInfo* info);
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ImplicitNullCheckStub* add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo);
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ImplicitNullCheckStub* add_debug_info_for_null_check_here(CodeEmitInfo* info);
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void set_24bit_FPU();
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void reset_FPU();
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void fpop();
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void fxch(int i);
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void fld(int i);
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void ffree(int i);
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void breakpoint();
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void push(LIR_Opr opr);
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void pop(LIR_Opr opr);
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// patching
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void append_patching_stub(PatchingStub* stub);
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void patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info);
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void comp_op(LIR_Condition condition, LIR_Opr src, LIR_Opr result, LIR_Op2* op);
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PatchingStub::PatchID patching_id(CodeEmitInfo* info);
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public:
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LIR_Assembler(Compilation* c);
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~LIR_Assembler();
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C1_MacroAssembler* masm() const { return _masm; }
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Compilation* compilation() const { return _compilation; }
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ciMethod* method() const { return compilation()->method(); }
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CodeOffsets* offsets() const { return _compilation->offsets(); }
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int code_offset() const;
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address pc() const;
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int initial_frame_size_in_bytes() const;
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int bang_size_in_bytes() const;
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// test for constants which can be encoded directly in instructions
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static bool is_small_constant(LIR_Opr opr);
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static LIR_Opr receiverOpr();
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static LIR_Opr osrBufferPointer();
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// stubs
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void emit_slow_case_stubs();
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void emit_static_call_stub();
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void append_code_stub(CodeStub* op);
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void add_call_info_here(CodeEmitInfo* info) { add_call_info(code_offset(), info); }
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// code patterns
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int emit_exception_handler();
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int emit_unwind_handler();
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void emit_exception_entries(ExceptionInfoList* info_list);
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int emit_deopt_handler();
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void emit_code(BlockList* hir);
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void emit_block(BlockBegin* block);
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void emit_lir_list(LIR_List* list);
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// any last minute peephole optimizations are performed here. In
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// particular sparc uses this for delay slot filling.
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void peephole(LIR_List* list);
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void return_op(LIR_Opr result);
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// returns offset of poll instruction
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int safepoint_poll(LIR_Opr result, CodeEmitInfo* info);
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void const2reg (LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info);
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void const2stack(LIR_Opr src, LIR_Opr dest);
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void const2mem (LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide);
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void reg2stack (LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack);
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void reg2reg (LIR_Opr src, LIR_Opr dest);
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void reg2mem (LIR_Opr src, LIR_Opr dest, BasicType type,
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LIR_PatchCode patch_code, CodeEmitInfo* info,
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bool pop_fpu_stack, bool wide, bool unaligned);
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void stack2reg (LIR_Opr src, LIR_Opr dest, BasicType type);
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void stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type);
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void mem2reg (LIR_Opr src, LIR_Opr dest, BasicType type,
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LIR_PatchCode patch_code,
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CodeEmitInfo* info, bool wide, bool unaligned);
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void shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp);
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void shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest);
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void move_regs(Register from_reg, Register to_reg);
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void swap_reg(Register a, Register b);
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void emit_op0(LIR_Op0* op);
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void emit_op1(LIR_Op1* op);
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void emit_op2(LIR_Op2* op);
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void emit_op3(LIR_Op3* op);
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void emit_opBranch(LIR_OpBranch* op);
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void emit_opLabel(LIR_OpLabel* op);
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void emit_arraycopy(LIR_OpArrayCopy* op);
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void emit_updatecrc32(LIR_OpUpdateCRC32* op);
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void emit_opConvert(LIR_OpConvert* op);
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void emit_alloc_obj(LIR_OpAllocObj* op);
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void emit_alloc_array(LIR_OpAllocArray* op);
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void emit_opTypeCheck(LIR_OpTypeCheck* op);
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void emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null);
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void emit_compare_and_swap(LIR_OpCompareAndSwap* op);
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void emit_lock(LIR_OpLock* op);
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void emit_call(LIR_OpJavaCall* op);
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void emit_rtcall(LIR_OpRTCall* op);
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void emit_profile_call(LIR_OpProfileCall* op);
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void emit_profile_type(LIR_OpProfileType* op);
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void emit_delay(LIR_OpDelay* op);
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void arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack);
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void arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info);
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void intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op);
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#ifdef ASSERT
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void emit_assert(LIR_OpAssert* op);
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#endif
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void logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest);
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void roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack);
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void move_op(LIR_Opr src, LIR_Opr result, BasicType type,
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LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned, bool wide);
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void volatile_move_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info);
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void comp_mem_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); // info set for null exceptions
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void comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr result, LIR_Op2* op);
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void cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr result, BasicType type);
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void call( LIR_OpJavaCall* op, relocInfo::relocType rtype);
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void ic_call( LIR_OpJavaCall* op);
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void vtable_call( LIR_OpJavaCall* op);
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void osr_entry();
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void build_frame();
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void throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info);
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void unwind_op(LIR_Opr exceptionOop);
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void monitor_address(int monitor_ix, LIR_Opr dst);
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void align_backward_branch_target();
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void align_call(LIR_Code code);
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void negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp = LIR_OprFact::illegalOpr);
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void leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code = lir_patch_none, CodeEmitInfo* info = NULL);
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void rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info);
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void membar();
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void membar_acquire();
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void membar_release();
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void membar_loadload();
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void membar_storestore();
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void membar_loadstore();
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void membar_storeload();
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void on_spin_wait();
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void get_thread(LIR_Opr result);
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void verify_oop_map(CodeEmitInfo* info);
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void atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp);
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#include CPU_HEADER(c1_LIRAssembler)
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public:
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static int call_stub_size() {
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if (UseAOT) {
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return _call_stub_size + _call_aot_stub_size;
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} else {
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return _call_stub_size;
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}
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}
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static int exception_handler_size() {
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return _exception_handler_size;
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}
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static int deopt_handler_size() {
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return _deopt_handler_size;
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}
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};
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#endif // SHARE_C1_C1_LIRASSEMBLER_HPP
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