9c458decf5
Add src/cpu/aarch64/vm/* interpreter, shared runtime files. Reviewed-by: kvn, roland, coleenp, twisti
413 lines
10 KiB
C++
413 lines
10 KiB
C++
/*
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* Copyright (c) 2014, Red Hat Inc. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#ifndef _DECODE_H
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#define _DECODE_H
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#include <sys/types.h>
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#include "cpustate_aarch64.hpp"
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// bitfield immediate expansion helper
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extern int expandLogicalImmediate(u_int32_t immN, u_int32_t immr,
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u_int32_t imms, u_int64_t &bimm);
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/*
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* codes used in conditional instructions
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*
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* these are passed to conditional operations to identify which
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* condition to test for
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*/
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enum CondCode {
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EQ = 0b0000, // meaning Z == 1
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NE = 0b0001, // meaning Z == 0
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HS = 0b0010, // meaning C == 1
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CS = HS,
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LO = 0b0011, // meaning C == 0
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CC = LO,
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MI = 0b0100, // meaning N == 1
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PL = 0b0101, // meaning N == 0
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VS = 0b0110, // meaning V == 1
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VC = 0b0111, // meaning V == 0
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HI = 0b1000, // meaning C == 1 && Z == 0
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LS = 0b1001, // meaning !(C == 1 && Z == 0)
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GE = 0b1010, // meaning N == V
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LT = 0b1011, // meaning N != V
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GT = 0b1100, // meaning Z == 0 && N == V
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LE = 0b1101, // meaning !(Z == 0 && N == V)
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AL = 0b1110, // meaning ANY
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NV = 0b1111 // ditto
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};
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/*
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* certain addressing modes for load require pre or post writeback of
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* the computed address to a base register
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*/
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enum WriteBack {
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Post = 0,
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Pre = 1
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};
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/*
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* certain addressing modes for load require an offset to
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* be optionally scaled so the decode needs to pass that
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* through to the execute routine
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*/
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enum Scaling {
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Unscaled = 0,
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Scaled = 1
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};
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/*
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* when we do have to scale we do so by shifting using
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* log(bytes in data element - 1) as the shift count.
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* so we don't have to scale offsets when loading
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* bytes.
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*/
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enum ScaleShift {
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ScaleShift16 = 1,
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ScaleShift32 = 2,
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ScaleShift64 = 3,
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ScaleShift128 = 4
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};
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/*
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* one of the addressing modes for load requires a 32-bit register
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* value to be either zero- or sign-extended for these instructions
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* UXTW or SXTW should be passed
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*
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* arithmetic register data processing operations can optionally
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* extend a portion of the second register value for these
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* instructions the value supplied must identify the portion of the
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* register which is to be zero- or sign-exended
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*/
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enum Extension {
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UXTB = 0,
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UXTH = 1,
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UXTW = 2,
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UXTX = 3,
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SXTB = 4,
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SXTH = 5,
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SXTW = 6,
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SXTX = 7
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};
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/*
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* arithmetic and logical register data processing operations
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* optionally perform a shift on the second register value
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*/
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enum Shift {
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LSL = 0,
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LSR = 1,
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ASR = 2,
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ROR = 3
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};
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/*
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* bit twiddling helpers for instruction decode
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*/
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// 32 bit mask with bits [hi,...,lo] set
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static inline u_int32_t mask32(int hi = 31, int lo = 0)
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{
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int nbits = (hi + 1) - lo;
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return ((1 << nbits) - 1) << lo;
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}
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static inline u_int64_t mask64(int hi = 63, int lo = 0)
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{
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int nbits = (hi + 1) - lo;
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return ((1L << nbits) - 1) << lo;
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}
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// pick bits [hi,...,lo] from val
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static inline u_int32_t pick32(u_int32_t val, int hi = 31, int lo = 0)
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{
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return (val & mask32(hi, lo));
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}
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// pick bits [hi,...,lo] from val
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static inline u_int64_t pick64(u_int64_t val, int hi = 31, int lo = 0)
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{
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return (val & mask64(hi, lo));
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}
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// pick bits [hi,...,lo] from val and shift to [(hi-(newlo - lo)),newlo]
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static inline u_int32_t pickshift32(u_int32_t val, int hi = 31,
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int lo = 0, int newlo = 0)
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{
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u_int32_t bits = pick32(val, hi, lo);
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if (lo < newlo) {
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return (bits << (newlo - lo));
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} else {
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return (bits >> (lo - newlo));
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}
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}
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// mask [hi,lo] and shift down to start at bit 0
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static inline u_int32_t pickbits32(u_int32_t val, int hi = 31, int lo = 0)
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{
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return (pick32(val, hi, lo) >> lo);
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}
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// mask [hi,lo] and shift down to start at bit 0
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static inline u_int64_t pickbits64(u_int64_t val, int hi = 63, int lo = 0)
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{
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return (pick64(val, hi, lo) >> lo);
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}
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/*
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* decode registers, immediates and constants of various types
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*/
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static inline GReg greg(u_int32_t val, int lo)
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{
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return (GReg)pickbits32(val, lo + 4, lo);
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}
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static inline VReg vreg(u_int32_t val, int lo)
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{
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return (VReg)pickbits32(val, lo + 4, lo);
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}
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static inline u_int32_t uimm(u_int32_t val, int hi, int lo)
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{
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return pickbits32(val, hi, lo);
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}
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static inline int32_t simm(u_int32_t val, int hi = 31, int lo = 0) {
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union {
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u_int32_t u;
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int32_t n;
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};
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u = val << (31 - hi);
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n = n >> (31 - hi + lo);
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return n;
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}
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static inline int64_t simm(u_int64_t val, int hi = 63, int lo = 0) {
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union {
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u_int64_t u;
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int64_t n;
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};
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u = val << (63 - hi);
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n = n >> (63 - hi + lo);
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return n;
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}
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static inline Shift shift(u_int32_t val, int lo)
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{
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return (Shift)pickbits32(val, lo+1, lo);
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}
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static inline Extension extension(u_int32_t val, int lo)
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{
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return (Extension)pickbits32(val, lo+2, lo);
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}
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static inline Scaling scaling(u_int32_t val, int lo)
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{
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return (Scaling)pickbits32(val, lo, lo);
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}
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static inline WriteBack writeback(u_int32_t val, int lo)
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{
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return (WriteBack)pickbits32(val, lo, lo);
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}
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static inline CondCode condcode(u_int32_t val, int lo)
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{
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return (CondCode)pickbits32(val, lo+3, lo);
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}
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/*
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* operation decode
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*/
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// bits [28,25] are the primary dispatch vector
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static inline u_int32_t dispatchGroup(u_int32_t val)
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{
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return pickshift32(val, 28, 25, 0);
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}
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/*
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* the 16 possible values for bits [28,25] identified by tags which
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* map them to the 5 main instruction groups LDST, DPREG, ADVSIMD,
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* BREXSYS and DPIMM.
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*
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* An extra group PSEUDO is included in one of the unallocated ranges
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* for simulator-specific pseudo-instructions.
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*/
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enum DispatchGroup {
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GROUP_PSEUDO_0000,
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GROUP_UNALLOC_0001,
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GROUP_UNALLOC_0010,
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GROUP_UNALLOC_0011,
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GROUP_LDST_0100,
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GROUP_DPREG_0101,
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GROUP_LDST_0110,
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GROUP_ADVSIMD_0111,
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GROUP_DPIMM_1000,
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GROUP_DPIMM_1001,
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GROUP_BREXSYS_1010,
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GROUP_BREXSYS_1011,
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GROUP_LDST_1100,
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GROUP_DPREG_1101,
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GROUP_LDST_1110,
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GROUP_ADVSIMD_1111
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};
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// bits [31, 29] of a Pseudo are the secondary dispatch vector
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static inline u_int32_t dispatchPseudo(u_int32_t val)
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{
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return pickshift32(val, 31, 29, 0);
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}
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/*
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* the 8 possible values for bits [31,29] in a Pseudo Instruction.
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* Bits [28,25] are always 0000.
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*/
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enum DispatchPseudo {
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PSEUDO_UNALLOC_000, // unallocated
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PSEUDO_UNALLOC_001, // ditto
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PSEUDO_UNALLOC_010, // ditto
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PSEUDO_UNALLOC_011, // ditto
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PSEUDO_UNALLOC_100, // ditto
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PSEUDO_UNALLOC_101, // ditto
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PSEUDO_CALLOUT_110, // CALLOUT -- bits [24,0] identify call/ret sig
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PSEUDO_HALT_111 // HALT -- bits [24, 0] identify halt code
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};
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// bits [25, 23] of a DPImm are the secondary dispatch vector
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static inline u_int32_t dispatchDPImm(u_int32_t instr)
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{
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return pickshift32(instr, 25, 23, 0);
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}
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/*
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* the 8 possible values for bits [25,23] in a Data Processing Immediate
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* Instruction. Bits [28,25] are always 100_.
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*/
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enum DispatchDPImm {
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DPIMM_PCADR_000, // PC-rel-addressing
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DPIMM_PCADR_001, // ditto
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DPIMM_ADDSUB_010, // Add/Subtract (immediate)
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DPIMM_ADDSUB_011, // ditto
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DPIMM_LOG_100, // Logical (immediate)
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DPIMM_MOV_101, // Move Wide (immediate)
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DPIMM_BITF_110, // Bitfield
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DPIMM_EXTR_111 // Extract
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};
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// bits [29,28:26] of a LS are the secondary dispatch vector
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static inline u_int32_t dispatchLS(u_int32_t instr)
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{
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return (pickshift32(instr, 29, 28, 1) |
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pickshift32(instr, 26, 26, 0));
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}
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/*
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* the 8 possible values for bits [29,28:26] in a Load/Store
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* Instruction. Bits [28,25] are always _1_0
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*/
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enum DispatchLS {
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LS_EXCL_000, // Load/store exclusive (includes some unallocated)
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LS_ADVSIMD_001, // AdvSIMD load/store (various -- includes some unallocated)
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LS_LIT_010, // Load register literal (includes some unallocated)
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LS_LIT_011, // ditto
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LS_PAIR_100, // Load/store register pair (various)
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LS_PAIR_101, // ditto
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LS_OTHER_110, // other load/store formats
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LS_OTHER_111 // ditto
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};
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// bits [28:24:21] of a DPReg are the secondary dispatch vector
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static inline u_int32_t dispatchDPReg(u_int32_t instr)
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{
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return (pickshift32(instr, 28, 28, 2) |
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pickshift32(instr, 24, 24, 1) |
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pickshift32(instr, 21, 21, 0));
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}
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/*
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* the 8 possible values for bits [28:24:21] in a Data Processing
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* Register Instruction. Bits [28,25] are always _101
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*/
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enum DispatchDPReg {
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DPREG_LOG_000, // Logical (shifted register)
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DPREG_LOG_001, // ditto
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DPREG_ADDSHF_010, // Add/subtract (shifted register)
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DPREG_ADDEXT_011, // Add/subtract (extended register)
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DPREG_ADDCOND_100, // Add/subtract (with carry) AND
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// Cond compare/select AND
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// Data Processing (1/2 source)
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DPREG_UNALLOC_101, // Unallocated
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DPREG_3SRC_110, // Data Processing (3 source)
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DPREG_3SRC_111 // Data Processing (3 source)
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};
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// bits [31,29] of a BrExSys are the secondary dispatch vector
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static inline u_int32_t dispatchBrExSys(u_int32_t instr)
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{
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return pickbits32(instr, 31, 29);
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}
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/*
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* the 8 possible values for bits [31,29] in a Branch/Exception/System
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* Instruction. Bits [28,25] are always 101_
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*/
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enum DispatchBr {
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BR_IMM_000, // Unconditional branch (immediate)
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BR_IMMCMP_001, // Compare & branch (immediate) AND
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// Test & branch (immediate)
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BR_IMMCOND_010, // Conditional branch (immediate) AND Unallocated
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BR_UNALLOC_011, // Unallocated
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BR_IMM_100, // Unconditional branch (immediate)
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BR_IMMCMP_101, // Compare & branch (immediate) AND
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// Test & branch (immediate)
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BR_REG_110, // Unconditional branch (register) AND System AND
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// Excn gen AND Unallocated
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BR_UNALLOC_111 // Unallocated
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};
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/*
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* TODO still need to provide secondary decode and dispatch for
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* AdvSIMD Insructions with instr[28,25] = 0111 or 1111
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*/
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#endif // ifndef DECODE_H
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