315 lines
13 KiB
C++
315 lines
13 KiB
C++
/*
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* Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#ifndef SHARE_VM_RUNTIME_ORDERACCESS_HPP
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#define SHARE_VM_RUNTIME_ORDERACCESS_HPP
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#include "memory/allocation.hpp"
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#include "runtime/atomic.hpp"
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// Memory Access Ordering Model
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//
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// This interface is based on the JSR-133 Cookbook for Compiler Writers.
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//
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// In the following, the terms 'previous', 'subsequent', 'before',
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// 'after', 'preceding' and 'succeeding' refer to program order. The
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// terms 'down' and 'below' refer to forward load or store motion
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// relative to program order, while 'up' and 'above' refer to backward
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// motion.
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//
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// We define four primitive memory barrier operations.
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//
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// LoadLoad: Load1(s); LoadLoad; Load2
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//
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// Ensures that Load1 completes (obtains the value it loads from memory)
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// before Load2 and any subsequent load operations. Loads before Load1
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// may *not* float below Load2 and any subsequent load operations.
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//
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// StoreStore: Store1(s); StoreStore; Store2
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//
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// Ensures that Store1 completes (the effect on memory of Store1 is made
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// visible to other processors) before Store2 and any subsequent store
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// operations. Stores before Store1 may *not* float below Store2 and any
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// subsequent store operations.
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//
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// LoadStore: Load1(s); LoadStore; Store2
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//
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// Ensures that Load1 completes before Store2 and any subsequent store
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// operations. Loads before Load1 may *not* float below Store2 and any
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// subsequent store operations.
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//
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// StoreLoad: Store1(s); StoreLoad; Load2
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//
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// Ensures that Store1 completes before Load2 and any subsequent load
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// operations. Stores before Store1 may *not* float below Load2 and any
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// subsequent load operations.
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//
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// We define two further barriers: acquire and release.
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//
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// Conceptually, acquire/release semantics form unidirectional and
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// asynchronous barriers w.r.t. a synchronizing load(X) and store(X) pair.
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// They should always be used in pairs to publish (release store) and
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// access (load acquire) some implicitly understood shared data between
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// threads in a relatively cheap fashion not requiring storeload. If not
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// used in such a pair, it is advised to use a membar instead:
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// acquire/release only make sense as pairs.
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//
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// T1: access_shared_data
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// T1: ]release
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// T1: (...)
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// T1: store(X)
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//
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// T2: load(X)
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// T2: (...)
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// T2: acquire[
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// T2: access_shared_data
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//
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// It is guaranteed that if T2: load(X) synchronizes with (observes the
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// value written by) T1: store(X), then the memory accesses before the T1:
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// ]release happen before the memory accesses after the T2: acquire[.
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//
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// Total Store Order (TSO) machines can be seen as machines issuing a
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// release store for each store and a load acquire for each load. Therefore
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// there is an inherent resemblence between TSO and acquire/release
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// semantics. TSO can be seen as an abstract machine where loads are
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// executed immediately when encountered (hence loadload reordering not
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// happening) but enqueues stores in a FIFO queue
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// for asynchronous serialization (neither storestore or loadstore
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// reordering happening). The only reordering happening is storeload due to
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// the queue asynchronously serializing stores (yet in order).
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//
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// Acquire/release semantics essentially exploits this asynchronicity: when
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// the load(X) acquire[ observes the store of ]release store(X), the
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// accesses before the release must have happened before the accesses after
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// acquire.
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//
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// The API offers both stand-alone acquire() and release() as well as bound
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// load_acquire() and release_store(). It is guaranteed that these are
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// semantically equivalent w.r.t. the defined model. However, since
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// stand-alone acquire()/release() does not know which previous
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// load/subsequent store is considered the synchronizing load/store, they
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// may be more conservative in implementations. We advise using the bound
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// variants whenever possible.
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//
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// Finally, we define a "fence" operation, as a bidirectional barrier.
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// It guarantees that any memory access preceding the fence is not
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// reordered w.r.t. any memory accesses subsequent to the fence in program
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// order. This may be used to prevent sequences of loads from floating up
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// above sequences of stores.
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//
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// The following table shows the implementations on some architectures:
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//
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// Constraint x86 sparc TSO ppc
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// ---------------------------------------------------------------------------
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// fence LoadStore | lock membar #StoreLoad sync
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// StoreStore | addl 0,(sp)
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// LoadLoad |
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// StoreLoad
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//
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// release LoadStore | lwsync
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// StoreStore
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//
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// acquire LoadLoad | lwsync
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// LoadStore
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//
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// release_store <store> <store> lwsync
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// <store>
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//
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// release_store_fence xchg <store> lwsync
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// membar #StoreLoad <store>
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// sync
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//
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//
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// load_acquire <load> <load> <load>
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// lwsync
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//
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// Ordering a load relative to preceding stores requires a StoreLoad,
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// which implies a membar #StoreLoad between the store and load under
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// sparc-TSO. On x86, we use explicitly locked add.
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//
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// Conventional usage is to issue a load_acquire for ordered loads. Use
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// release_store for ordered stores when you care only that prior stores
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// are visible before the release_store, but don't care exactly when the
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// store associated with the release_store becomes visible. Use
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// release_store_fence to update values like the thread state, where we
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// don't want the current thread to continue until all our prior memory
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// accesses (including the new thread state) are visible to other threads.
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// This is equivalent to the volatile semantics of the Java Memory Model.
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//
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// C++ Volatile Semantics
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//
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// C++ volatile semantics prevent compiler re-ordering between
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// volatile memory accesses. However, reordering between non-volatile
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// and volatile memory accesses is in general undefined. For compiler
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// reordering constraints taking non-volatile memory accesses into
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// consideration, a compiler barrier has to be used instead. Some
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// compiler implementations may choose to enforce additional
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// constraints beyond those required by the language. Note also that
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// both volatile semantics and compiler barrier do not prevent
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// hardware reordering.
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//
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// os::is_MP Considered Redundant
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//
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// Callers of this interface do not need to test os::is_MP() before
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// issuing an operation. The test is taken care of by the implementation
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// of the interface (depending on the vm version and platform, the test
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// may or may not be actually done by the implementation).
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//
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//
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// A Note on Memory Ordering and Cache Coherency
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//
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// Cache coherency and memory ordering are orthogonal concepts, though they
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// interact. E.g., all existing itanium machines are cache-coherent, but
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// the hardware can freely reorder loads wrt other loads unless it sees a
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// load-acquire instruction. All existing sparc machines are cache-coherent
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// and, unlike itanium, TSO guarantees that the hardware orders loads wrt
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// loads and stores, and stores wrt to each other.
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//
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// Consider the implementation of loadload. *If* your platform *isn't*
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// cache-coherent, then loadload must not only prevent hardware load
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// instruction reordering, but it must *also* ensure that subsequent
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// loads from addresses that could be written by other processors (i.e.,
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// that are broadcast by other processors) go all the way to the first
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// level of memory shared by those processors and the one issuing
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// the loadload.
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//
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// So if we have a MP that has, say, a per-processor D$ that doesn't see
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// writes by other processors, and has a shared E$ that does, the loadload
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// barrier would have to make sure that either
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//
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// 1. cache lines in the issuing processor's D$ that contained data from
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// addresses that could be written by other processors are invalidated, so
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// subsequent loads from those addresses go to the E$, (it could do this
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// by tagging such cache lines as 'shared', though how to tell the hardware
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// to do the tagging is an interesting problem), or
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//
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// 2. there never are such cache lines in the issuing processor's D$, which
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// means all references to shared data (however identified: see above)
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// bypass the D$ (i.e., are satisfied from the E$).
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//
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// If your machine doesn't have an E$, substitute 'main memory' for 'E$'.
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//
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// Either of these alternatives is a pain, so no current machine we know of
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// has incoherent caches.
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//
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// If loadload didn't have these properties, the store-release sequence for
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// publishing a shared data structure wouldn't work, because a processor
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// trying to read data newly published by another processor might go to
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// its own incoherent caches to satisfy the read instead of to the newly
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// written shared memory.
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//
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//
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// NOTE WELL!!
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//
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// A Note on MutexLocker and Friends
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//
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// See mutexLocker.hpp. We assume throughout the VM that MutexLocker's
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// and friends' constructors do a fence, a lock and an acquire *in that
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// order*. And that their destructors do a release and unlock, in *that*
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// order. If their implementations change such that these assumptions
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// are violated, a whole lot of code will break.
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enum ScopedFenceType {
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X_ACQUIRE
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, RELEASE_X
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, RELEASE_X_FENCE
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};
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template <ScopedFenceType T>
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class ScopedFenceGeneral: public StackObj {
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public:
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void prefix() {}
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void postfix() {}
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};
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template <ScopedFenceType T>
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class ScopedFence : public ScopedFenceGeneral<T> {
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void *const _field;
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public:
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ScopedFence(void *const field) : _field(field) { prefix(); }
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~ScopedFence() { postfix(); }
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void prefix() { ScopedFenceGeneral<T>::prefix(); }
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void postfix() { ScopedFenceGeneral<T>::postfix(); }
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};
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class OrderAccess : private Atomic {
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public:
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// barriers
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static void loadload();
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static void storestore();
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static void loadstore();
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static void storeload();
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static void acquire();
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static void release();
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static void fence();
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template <typename T>
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static T load_acquire(const volatile T* p);
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template <typename T, typename D>
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static void release_store(volatile D* p, T v);
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template <typename T, typename D>
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static void release_store_fence(volatile D* p, T v);
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private:
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// This is a helper that invokes the StubRoutines::fence_entry()
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// routine if it exists, It should only be used by platforms that
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// don't have another way to do the inline assembly.
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static void StubRoutines_fence();
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// Give platforms a variation point to specialize.
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template<size_t byte_size, ScopedFenceType type> struct PlatformOrderedStore;
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template<size_t byte_size, ScopedFenceType type> struct PlatformOrderedLoad;
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template<typename FieldType, ScopedFenceType FenceType>
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static void ordered_store(volatile FieldType* p, FieldType v);
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template<typename FieldType, ScopedFenceType FenceType>
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static FieldType ordered_load(const volatile FieldType* p);
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};
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// The following methods can be specialized using simple template specialization
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// in the platform specific files for optimization purposes. Otherwise the
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// generalized variant is used.
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template<size_t byte_size, ScopedFenceType type>
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struct OrderAccess::PlatformOrderedStore {
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template <typename T>
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void operator()(T v, volatile T* p) const {
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ordered_store<T, type>(p, v);
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}
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};
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template<size_t byte_size, ScopedFenceType type>
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struct OrderAccess::PlatformOrderedLoad {
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template <typename T>
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T operator()(const volatile T* p) const {
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return ordered_load<T, type>(p);
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}
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};
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#endif // SHARE_VM_RUNTIME_ORDERACCESS_HPP
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