525 lines
19 KiB
C++
525 lines
19 KiB
C++
/*
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* Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#include "precompiled.hpp"
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#include "jvm.h"
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#include "asm/macroAssembler.inline.hpp"
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#include "logging/log.hpp"
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#include "logging/logStream.hpp"
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#include "memory/resourceArea.hpp"
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#include "oops/compressedOops.hpp"
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#include "runtime/java.hpp"
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#include "runtime/os.hpp"
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#include "runtime/stubCodeGenerator.hpp"
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#include "vm_version_sparc.hpp"
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#include <sys/mman.h>
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uint VM_Version::_L2_data_cache_line_size = 0;
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void VM_Version::initialize() {
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assert(_features != 0, "System pre-initialization is not complete.");
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guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
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PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
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PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
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PrefetchFieldsAhead = prefetch_fields_ahead();
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// Allocation prefetch settings
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AllocatePrefetchDistance = allocate_prefetch_distance();
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AllocatePrefetchStyle = allocate_prefetch_style();
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intx cache_line_size = prefetch_data_size();
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if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize)) {
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AllocatePrefetchStepSize = MAX2(AllocatePrefetchStepSize, cache_line_size);
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}
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if (AllocatePrefetchInstr == 1) {
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if (!has_blk_init()) {
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warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable");
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FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
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}
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if (cache_line_size <= 0) {
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warning("Cache-line size must be known for AllocatePrefetchInstr 1 to work");
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FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
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}
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}
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UseSSE = false; // Only used on x86 and x64.
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_supports_cx8 = true; // All SPARC V9 implementations.
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_supports_atomic_getset4 = true; // Using the 'swap' instruction.
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if (has_fast_ind_br() && FLAG_IS_DEFAULT(UseInlineCaches)) {
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// Indirect and direct branches are cost equivalent.
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FLAG_SET_DEFAULT(UseInlineCaches, false);
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}
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// Align loops on the proper instruction boundary to fill the instruction
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// fetch buffer.
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if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
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FLAG_SET_DEFAULT(OptoLoopAlignment, VM_Version::insn_fetch_alignment);
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}
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// 32-bit oops don't make sense for the 64-bit VM on SPARC since the 32-bit
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// VM has the same registers and smaller objects.
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CompressedOops::set_shift(LogMinObjAlignmentInBytes);
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CompressedKlassPointers::set_shift(LogKlassAlignmentInBytes);
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#ifdef COMPILER2
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if (has_fast_ind_br() && FLAG_IS_DEFAULT(UseJumpTables)) {
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// Indirect and direct branches are cost equivalent.
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FLAG_SET_DEFAULT(UseJumpTables, true);
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}
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// Entry and loop tops are aligned to fill the instruction fetch buffer.
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if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
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FLAG_SET_DEFAULT(InteriorEntryAlignment, VM_Version::insn_fetch_alignment);
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}
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if (UseTLAB && cache_line_size > 0 &&
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FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
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if (has_fast_bis()) {
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// Use BIS instruction for TLAB allocation prefetch.
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FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
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}
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else if (has_sparc5()) {
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// Use prefetch instruction to avoid partial RAW issue on Core C4 processors,
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// also use prefetch style 3.
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FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
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if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
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FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
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}
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}
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}
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if (AllocatePrefetchInstr == 1) {
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// Use allocation prefetch style 3 because BIS instructions require
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// aligned memory addresses.
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FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
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}
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if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
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if (AllocatePrefetchInstr == 0) {
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// Use different prefetch distance without BIS
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FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
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} else {
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// Use smaller prefetch distance with BIS
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FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
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}
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}
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// We increase the number of prefetched cache lines, to use just a bit more
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// aggressive approach, when the L2-cache line size is small (32 bytes), or
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// when running on newer processor implementations, such as the Core C4.
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bool inc_prefetch = cache_line_size > 0 && (cache_line_size < 64 || has_sparc5());
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if (inc_prefetch) {
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// We use a factor two for small cache line sizes (as before) but a slightly
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// more conservative increase when running on more recent hardware that will
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// benefit from just a bit more aggressive prefetching.
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if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
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const int ap_lns = AllocatePrefetchLines;
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const int ap_inc = cache_line_size < 64 ? ap_lns : (ap_lns + 1) / 2;
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FLAG_SET_ERGO(AllocatePrefetchLines, ap_lns + ap_inc);
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}
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if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
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const int ip_lns = AllocateInstancePrefetchLines;
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const int ip_inc = cache_line_size < 64 ? ip_lns : (ip_lns + 1) / 2;
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FLAG_SET_ERGO(AllocateInstancePrefetchLines, ip_lns + ip_inc);
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}
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}
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#endif /* COMPILER2 */
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// Use hardware population count instruction if available.
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if (has_popc()) {
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if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
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FLAG_SET_DEFAULT(UsePopCountInstruction, true);
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}
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} else if (UsePopCountInstruction) {
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warning("POPC instruction is not available on this CPU");
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FLAG_SET_DEFAULT(UsePopCountInstruction, false);
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}
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// Use compare and branch instructions if available.
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if (has_cbcond()) {
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if (FLAG_IS_DEFAULT(UseCBCond)) {
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FLAG_SET_DEFAULT(UseCBCond, true);
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}
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} else if (UseCBCond) {
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warning("CBCOND instruction is not available on this CPU");
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FLAG_SET_DEFAULT(UseCBCond, false);
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}
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// Use 'mpmul' instruction if available.
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if (has_mpmul()) {
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if (FLAG_IS_DEFAULT(UseMPMUL)) {
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FLAG_SET_DEFAULT(UseMPMUL, true);
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}
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} else if (UseMPMUL) {
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warning("MPMUL instruction is not available on this CPU");
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FLAG_SET_DEFAULT(UseMPMUL, false);
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}
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assert(BlockZeroingLowLimit > 0, "invalid value");
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if (has_blk_zeroing() && cache_line_size > 0) {
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if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
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FLAG_SET_DEFAULT(UseBlockZeroing, true);
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}
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} else if (UseBlockZeroing) {
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warning("BIS zeroing instructions are not available on this CPU");
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FLAG_SET_DEFAULT(UseBlockZeroing, false);
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}
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assert(BlockCopyLowLimit > 0, "invalid value");
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if (has_blk_zeroing() && cache_line_size > 0) {
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if (FLAG_IS_DEFAULT(UseBlockCopy)) {
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FLAG_SET_DEFAULT(UseBlockCopy, true);
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}
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} else if (UseBlockCopy) {
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warning("BIS instructions are not available or expensive on this CPU");
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FLAG_SET_DEFAULT(UseBlockCopy, false);
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}
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#ifdef COMPILER2
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if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
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FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
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}
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// Currently not supported anywhere.
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FLAG_SET_DEFAULT(UseFPUForSpilling, false);
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MaxVectorSize = 8;
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assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
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#endif
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assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
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assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
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char buf[512];
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jio_snprintf(buf, sizeof(buf),
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"%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s"
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"%s%s%s%s%s%s%s%s%s" "%s%s%s%s%s%s%s%s%s"
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"%s%s%s%s%s%s%s",
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(has_v9() ? "v9" : ""),
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(has_popc() ? ", popc" : ""),
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(has_vis1() ? ", vis1" : ""),
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(has_vis2() ? ", vis2" : ""),
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(has_blk_init() ? ", blk_init" : ""),
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(has_fmaf() ? ", fmaf" : ""),
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(has_hpc() ? ", hpc" : ""),
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(has_ima() ? ", ima" : ""),
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(has_aes() ? ", aes" : ""),
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(has_des() ? ", des" : ""),
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(has_kasumi() ? ", kas" : ""),
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(has_camellia() ? ", cam" : ""),
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(has_md5() ? ", md5" : ""),
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(has_sha1() ? ", sha1" : ""),
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(has_sha256() ? ", sha256" : ""),
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(has_sha512() ? ", sha512" : ""),
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(has_mpmul() ? ", mpmul" : ""),
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(has_mont() ? ", mont" : ""),
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(has_pause() ? ", pause" : ""),
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(has_cbcond() ? ", cbcond" : ""),
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(has_crc32c() ? ", crc32c" : ""),
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(has_athena_plus() ? ", athena_plus" : ""),
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(has_vis3b() ? ", vis3b" : ""),
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(has_adi() ? ", adi" : ""),
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(has_sparc5() ? ", sparc5" : ""),
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(has_mwait() ? ", mwait" : ""),
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(has_xmpmul() ? ", xmpmul" : ""),
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(has_xmont() ? ", xmont" : ""),
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(has_pause_nsec() ? ", pause_nsec" : ""),
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(has_vamask() ? ", vamask" : ""),
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(has_sparc6() ? ", sparc6" : ""),
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(has_dictunp() ? ", dictunp" : ""),
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(has_fpcmpshl() ? ", fpcmpshl" : ""),
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(has_rle() ? ", rle" : ""),
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(has_sha3() ? ", sha3" : ""),
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(has_athena_plus2()? ", athena_plus2" : ""),
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(has_vis3c() ? ", vis3c" : ""),
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(has_sparc5b() ? ", sparc5b" : ""),
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(has_mme() ? ", mme" : ""),
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(has_fast_idiv() ? ", *idiv" : ""),
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(has_fast_rdpc() ? ", *rdpc" : ""),
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(has_fast_bis() ? ", *bis" : ""),
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(has_fast_ld() ? ", *ld" : ""),
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(has_fast_cmove() ? ", *cmove" : ""),
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(has_fast_ind_br() ? ", *ind_br" : ""),
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(has_blk_zeroing() ? ", *blk_zeroing" : ""));
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assert(strlen(buf) >= 2, "must be");
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_features_string = os::strdup(buf);
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log_info(os, cpu)("SPARC features detected: %s", _features_string);
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// UseVIS is set to the smallest of what hardware supports and what the command
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// line requires, i.e. you cannot set UseVIS to 3 on older UltraSparc which do
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// not support it.
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if (UseVIS > 3) UseVIS = 3;
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if (UseVIS < 0) UseVIS = 0;
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if (!has_vis3()) // Drop to 2 if no VIS3 support
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UseVIS = MIN2((intx)2, UseVIS);
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if (!has_vis2()) // Drop to 1 if no VIS2 support
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UseVIS = MIN2((intx)1, UseVIS);
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if (!has_vis1()) // Drop to 0 if no VIS1 support
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UseVIS = 0;
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if (has_aes()) {
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if (FLAG_IS_DEFAULT(UseAES)) {
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FLAG_SET_DEFAULT(UseAES, true);
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}
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if (!UseAES) {
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if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
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warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
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}
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FLAG_SET_DEFAULT(UseAESIntrinsics, false);
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} else {
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// The AES intrinsic stubs require AES instruction support (of course)
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// but also require VIS3 mode or higher for instructions it use.
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if (UseVIS > 2) {
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if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
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FLAG_SET_DEFAULT(UseAESIntrinsics, true);
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}
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} else {
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if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
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warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled.");
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}
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FLAG_SET_DEFAULT(UseAESIntrinsics, false);
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}
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}
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} else if (UseAES || UseAESIntrinsics) {
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if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
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warning("AES instructions are not available on this CPU");
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FLAG_SET_DEFAULT(UseAES, false);
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}
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if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
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warning("AES intrinsics are not available on this CPU");
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FLAG_SET_DEFAULT(UseAESIntrinsics, false);
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}
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}
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if (UseAESCTRIntrinsics) {
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warning("AES/CTR intrinsics are not available on this CPU");
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FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
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}
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// GHASH/GCM intrinsics
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if (has_vis3() && (UseVIS > 2)) {
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if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
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UseGHASHIntrinsics = true;
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}
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} else if (UseGHASHIntrinsics) {
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if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
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warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
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FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
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}
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if (has_fmaf()) {
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if (FLAG_IS_DEFAULT(UseFMA)) {
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UseFMA = true;
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}
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} else if (UseFMA) {
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warning("FMA instructions are not available on this CPU");
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FLAG_SET_DEFAULT(UseFMA, false);
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}
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// SHA1, SHA256, and SHA512 instructions were added to SPARC at different times
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if (has_sha1() || has_sha256() || has_sha512()) {
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if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
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if (FLAG_IS_DEFAULT(UseSHA)) {
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FLAG_SET_DEFAULT(UseSHA, true);
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}
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} else {
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if (UseSHA) {
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warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
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FLAG_SET_DEFAULT(UseSHA, false);
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}
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}
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} else if (UseSHA) {
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warning("SHA instructions are not available on this CPU");
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FLAG_SET_DEFAULT(UseSHA, false);
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}
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if (UseSHA && has_sha1()) {
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if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
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FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
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}
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} else if (UseSHA1Intrinsics) {
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warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
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FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
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}
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if (UseSHA && has_sha256()) {
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if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
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FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
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}
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} else if (UseSHA256Intrinsics) {
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warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
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FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
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}
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if (UseSHA && has_sha512()) {
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if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
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FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
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}
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} else if (UseSHA512Intrinsics) {
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warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
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FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
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}
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if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
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FLAG_SET_DEFAULT(UseSHA, false);
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}
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if (has_crc32c()) {
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if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
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if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
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FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
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}
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} else {
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if (UseCRC32CIntrinsics) {
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warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
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FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
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}
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}
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} else if (UseCRC32CIntrinsics) {
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warning("CRC32C instruction is not available on this CPU");
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FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
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}
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if (UseVIS > 2) {
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if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
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FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
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}
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} else if (UseAdler32Intrinsics) {
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warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
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FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
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}
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if (UseVIS > 2) {
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if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
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FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
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}
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} else if (UseCRC32Intrinsics) {
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warning("SPARC CRC32 intrinsics require VIS3 instructions support. Intrinsics will be disabled");
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FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
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}
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if (UseVIS > 2) {
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if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
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FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, true);
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}
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} else if (UseMultiplyToLenIntrinsic) {
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warning("SPARC multiplyToLen intrinsics require VIS3 instructions support. Intrinsics will be disabled");
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FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
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}
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if (UseVectorizedMismatchIntrinsic) {
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warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
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FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
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}
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if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
|
|
(cache_line_size > ContendedPaddingWidth))
|
|
ContendedPaddingWidth = cache_line_size;
|
|
|
|
// This machine does not allow unaligned memory accesses
|
|
if (UseUnalignedAccesses) {
|
|
if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
|
|
warning("Unaligned memory access is not available on this CPU");
|
|
FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
|
|
}
|
|
|
|
if (log_is_enabled(Info, os, cpu)) {
|
|
ResourceMark rm;
|
|
LogStream ls(Log(os, cpu)::info());
|
|
outputStream* log = &ls;
|
|
log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
|
|
log->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
|
|
log->print("Allocation");
|
|
if (AllocatePrefetchStyle <= 0) {
|
|
log->print(": no prefetching");
|
|
} else {
|
|
log->print(" prefetching: ");
|
|
if (AllocatePrefetchInstr == 0) {
|
|
log->print("PREFETCH");
|
|
} else if (AllocatePrefetchInstr == 1) {
|
|
log->print("BIS");
|
|
}
|
|
if (AllocatePrefetchLines > 1) {
|
|
log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
|
|
} else {
|
|
log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
|
|
}
|
|
}
|
|
if (PrefetchCopyIntervalInBytes > 0) {
|
|
log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
|
|
}
|
|
if (PrefetchScanIntervalInBytes > 0) {
|
|
log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
|
|
}
|
|
if (PrefetchFieldsAhead > 0) {
|
|
log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
|
|
}
|
|
if (ContendedPaddingWidth > 0) {
|
|
log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
|
|
}
|
|
}
|
|
}
|
|
|
|
void VM_Version::print_features() {
|
|
tty->print("ISA features [0x%0" PRIx64 "]:", _features);
|
|
if (_features_string != NULL) {
|
|
tty->print(" %s", _features_string);
|
|
}
|
|
tty->cr();
|
|
}
|
|
|
|
void VM_Version::determine_features() {
|
|
platform_features(); // platform_features() is os_arch specific.
|
|
|
|
assert(has_v9(), "must be");
|
|
|
|
if (UseNiagaraInstrs) { // Limit code generation to Niagara.
|
|
_features &= niagara1_msk;
|
|
}
|
|
}
|
|
|
|
static uint64_t saved_features = 0;
|
|
|
|
void VM_Version::allow_all() {
|
|
saved_features = _features;
|
|
_features = full_feature_msk;
|
|
}
|
|
|
|
void VM_Version::revert() {
|
|
_features = saved_features;
|
|
}
|